[PATCH 00/11] arm: Remove FPA support from gas/binutils

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* [PATCH 00/11] arm: Remove FPA support from gas/binutils
@ 2024-06-03 11:49 Richard Earnshaw
  2024-06-03 11:49 ` [PATCH 01/11] arm: remove FPA related tests Richard Earnshaw
                   ` (10 more replies)
  0 siblings, 11 replies; 14+ messages in thread
From: Richard Earnshaw @ 2024-06-03 11:49 UTC (permalink / raw)
  To: binutils; +Cc: nickc, Richard Earnshaw

As trailed when removing the support for the Maverick co-processor
(https://sourceware.org/pipermail/binutils/2024-May/133947.html), this
patch series removes support for the FPA co-processor as well.
Support for both co-processors was removed from GCC about 12 years
ago.

This patch set is slightly more involved than the one for Maverick
though as it affects the default behaviour of the tools in a few
cases, especially on coff-based targets where we do not default a
default floating point format and pick the default up from the
selected CPU.  To avoid silent code changes I've opted to set the
default for those cases such that they generate an error if the output
might have changed when no FPA instructions were generated; this
affects certain directives such as .float or .double, since the FPA
had a different format for floating-point values.


Richard Earnshaw (11):
  arm: remove FPA related tests
  arm: rename FPU_ARCH_VFP to FPU_ARCH_SOFTVFP
  arm: default to softvfp on armv6 or later cores
  arm: adjust FPU selection logic
  arm: redirect fp constant data directives through a wrapper
  arm: change default FPUs from FPA to none
  arm: remove options to select the FPA
  arm: remove FPA instructions from assembler
  arm: remove disassembly support for the FPA co-processor
  arm: minor documentation cleanup given removal of FPA
  NEWS: arm: note that FPA support has been removed

 binutils/NEWS                                 |    4 +
 gas/config/tc-arm.c                           | 1056 +++--------------
 gas/config/te-armeabi.h                       |    2 +-
 gas/config/te-armfbsdvfp.h                    |    2 +-
 gas/config/te-armlinuxeabi.h                  |    2 +-
 gas/config/te-nacl.h                          |    2 +-
 gas/doc/c-arm.texi                            |   12 +-
 gas/testsuite/gas/all/gas.exp                 |    2 +
 gas/testsuite/gas/arm/attr-mfpu-arm7500fe.d   |   11 -
 gas/testsuite/gas/arm/attr-mfpu-fpa.d         |   11 -
 gas/testsuite/gas/arm/attr-mfpu-fpa10.d       |   11 -
 gas/testsuite/gas/arm/attr-mfpu-fpa11.d       |   11 -
 gas/testsuite/gas/arm/attr-mfpu-fpe.d         |   11 -
 gas/testsuite/gas/arm/attr-mfpu-fpe2.d        |   11 -
 gas/testsuite/gas/arm/attr-mfpu-fpe3.d        |   11 -
 gas/testsuite/gas/arm/attr-mfpu-softfpa.d     |   11 -
 gas/testsuite/gas/arm/attr-override-mcpu.s    |    2 +-
 gas/testsuite/gas/arm/bfloat16-directive-be.d |    2 +-
 gas/testsuite/gas/arm/bfloat16-directive-le.d |    2 +-
 .../gas/arm/copro-arm_v2plus-arm_v2.d         |    6 +-
 .../arm/copro-thumb_v6t2plus-thumb_v6t2-1.d   |    6 +-
 gas/testsuite/gas/arm/float.d                 |  131 --
 gas/testsuite/gas/arm/float.s                 |  163 ---
 gas/testsuite/gas/arm/float16-bad.d           |    1 +
 gas/testsuite/gas/arm/float16-be.d            |    2 +-
 .../gas/arm/float16-format-opt-bad.d          |    2 +-
 gas/testsuite/gas/arm/float16-le.d            |    2 +-
 gas/testsuite/gas/arm/fp-directive-bad.d      |    4 +
 gas/testsuite/gas/arm/fp-directive-bad.l      |    7 +
 gas/testsuite/gas/arm/fp-directive.d          |    9 +
 gas/testsuite/gas/arm/fp-directive.s          |    7 +
 gas/testsuite/gas/arm/fp-save.d               |    9 -
 gas/testsuite/gas/arm/fp-save.s               |    4 -
 gas/testsuite/gas/arm/fpa-dyadic.d            |  166 ---
 gas/testsuite/gas/arm/fpa-dyadic.s            |  172 ---
 gas/testsuite/gas/arm/fpa-mem.d               |   34 -
 gas/testsuite/gas/arm/fpa-mem.s               |   32 -
 gas/testsuite/gas/arm/fpa-monadic.d           |  202 ----
 gas/testsuite/gas/arm/fpa-monadic.s           |  210 ----
 .../gas/arm/group-reloc-ldc-encoding-bad.l    |  192 ---
 .../gas/arm/group-reloc-ldc-encoding-bad.s    |   72 +-
 .../gas/arm/group-reloc-ldc-parsing-bad.l     |   80 --
 .../gas/arm/group-reloc-ldc-parsing-bad.s     |   20 +-
 gas/testsuite/gas/arm/group-reloc-ldc.d       |  336 ++----
 gas/testsuite/gas/arm/group-reloc-ldc.s       |   45 -
 gas/testsuite/gas/arm/le-fpconst.d            |   11 -
 gas/testsuite/gas/arm/le-fpconst.s            |    8 -
 include/opcode/arm.h                          |   12 +-
 opcodes/arm-dis.c                             |  197 +--
 49 files changed, 369 insertions(+), 2949 deletions(-)
 delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-arm7500fe.d
 delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-fpa.d
 delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-fpa10.d
 delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-fpa11.d
 delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-fpe.d
 delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-fpe2.d
 delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-fpe3.d
 delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-softfpa.d
 delete mode 100644 gas/testsuite/gas/arm/float.d
 delete mode 100644 gas/testsuite/gas/arm/float.s
 create mode 100644 gas/testsuite/gas/arm/fp-directive-bad.d
 create mode 100644 gas/testsuite/gas/arm/fp-directive-bad.l
 create mode 100644 gas/testsuite/gas/arm/fp-directive.d
 create mode 100644 gas/testsuite/gas/arm/fp-directive.s
 delete mode 100644 gas/testsuite/gas/arm/fp-save.d
 delete mode 100644 gas/testsuite/gas/arm/fp-save.s
 delete mode 100644 gas/testsuite/gas/arm/fpa-dyadic.d
 delete mode 100644 gas/testsuite/gas/arm/fpa-dyadic.s
 delete mode 100644 gas/testsuite/gas/arm/fpa-mem.d
 delete mode 100644 gas/testsuite/gas/arm/fpa-mem.s
 delete mode 100644 gas/testsuite/gas/arm/fpa-monadic.d
 delete mode 100644 gas/testsuite/gas/arm/fpa-monadic.s
 delete mode 100644 gas/testsuite/gas/arm/le-fpconst.d
 delete mode 100644 gas/testsuite/gas/arm/le-fpconst.s

-- 
2.34.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 01/11] arm: remove FPA related tests
  2024-06-03 11:49 [PATCH 00/11] arm: Remove FPA support from gas/binutils Richard Earnshaw
@ 2024-06-03 11:49 ` Richard Earnshaw
  2024-06-03 11:49 ` [PATCH 02/11] arm: rename FPU_ARCH_VFP to FPU_ARCH_SOFTVFP Richard Earnshaw
                   ` (9 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Richard Earnshaw @ 2024-06-03 11:49 UTC (permalink / raw)
  To: binutils; +Cc: nickc, Richard Earnshaw

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="3DUTF-8"; format=3Dfixed, Size: 2828 bytes --]


Remove various tests of the FPA instruction set and relocation support.
---
 gas/testsuite/gas/arm/attr-mfpu-arm7500fe.d   |  11 -
 gas/testsuite/gas/arm/attr-mfpu-fpa.d         |  11 -
 gas/testsuite/gas/arm/attr-mfpu-fpa10.d       |  11 -
 gas/testsuite/gas/arm/attr-mfpu-fpa11.d       |  11 -
 gas/testsuite/gas/arm/attr-mfpu-fpe.d         |  11 -
 gas/testsuite/gas/arm/attr-mfpu-fpe2.d        |  11 -
 gas/testsuite/gas/arm/attr-mfpu-fpe3.d        |  11 -
 gas/testsuite/gas/arm/attr-mfpu-softfpa.d     |  11 -
 gas/testsuite/gas/arm/attr-override-mcpu.s    |   2 +-
 gas/testsuite/gas/arm/float.d                 | 131 -------
 gas/testsuite/gas/arm/float.s                 | 163 ---------
 gas/testsuite/gas/arm/fp-save.d               |   9 -
 gas/testsuite/gas/arm/fp-save.s               |   4 -
 gas/testsuite/gas/arm/fpa-dyadic.d            | 166 ---------
 gas/testsuite/gas/arm/fpa-dyadic.s            | 172 ---------
 gas/testsuite/gas/arm/fpa-mem.d               |  34 --
 gas/testsuite/gas/arm/fpa-mem.s               |  32 --
 gas/testsuite/gas/arm/fpa-monadic.d           | 202 -----------
 gas/testsuite/gas/arm/fpa-monadic.s           | 210 -----------
 .../gas/arm/group-reloc-ldc-encoding-bad.l    | 192 ----------
 .../gas/arm/group-reloc-ldc-encoding-bad.s    |  72 ++--
 .../gas/arm/group-reloc-ldc-parsing-bad.l     |  80 -----
 .../gas/arm/group-reloc-ldc-parsing-bad.s     |  20 +-
 gas/testsuite/gas/arm/group-reloc-ldc.d       | 336 ++++--------------
 gas/testsuite/gas/arm/group-reloc-ldc.s       |  45 ---
 gas/testsuite/gas/arm/le-fpconst.d            |  11 -
 gas/testsuite/gas/arm/le-fpconst.s            |   8 -
 27 files changed, 119 insertions(+), 1858 deletions(-)
 delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-arm7500fe.d
 delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-fpa.d
 delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-fpa10.d
 delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-fpa11.d
 delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-fpe.d
 delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-fpe2.d
 delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-fpe3.d
 delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-softfpa.d
 delete mode 100644 gas/testsuite/gas/arm/float.d
 delete mode 100644 gas/testsuite/gas/arm/float.s
 delete mode 100644 gas/testsuite/gas/arm/fp-save.d
 delete mode 100644 gas/testsuite/gas/arm/fp-save.s
 delete mode 100644 gas/testsuite/gas/arm/fpa-dyadic.d
 delete mode 100644 gas/testsuite/gas/arm/fpa-dyadic.s
 delete mode 100644 gas/testsuite/gas/arm/fpa-mem.d
 delete mode 100644 gas/testsuite/gas/arm/fpa-mem.s
 delete mode 100644 gas/testsuite/gas/arm/fpa-monadic.d
 delete mode 100644 gas/testsuite/gas/arm/fpa-monadic.s
 delete mode 100644 gas/testsuite/gas/arm/le-fpconst.d
 delete mode 100644 gas/testsuite/gas/arm/le-fpconst.s


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 3D"0001-arm-remove-FPA-related-te= --]
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diff --git a/gas/testsuite/gas/arm/attr-mfpu-arm7500fe.d b/gas/testsuite/ga=
s/arm/attr-mfpu-arm7500fe.d
deleted file mode 100644
index 8279d6f5d0c..00000000000
--- a/gas/testsuite/gas/arm/attr-mfpu-arm7500fe.d
+++ /dev/null
@@ -1,11 +0,0 @@
-# name: attributes for -mfpu=3Darm7500fe
-# source: blank.s
-# as: -mfpu=3Darm7500fe
-# readelf: -A
-# This test is only valid on EABI based ports.
-# target: *-*-*eabi* *-*-nacl*
-
-Attribute Section: aeabi
-File Attributes
-  Tag_ARM_ISA_use: Yes
-  Tag_THUMB_ISA_use: Thumb-1
diff --git a/gas/testsuite/gas/arm/attr-mfpu-fpa.d b/gas/testsuite/gas/arm/=
attr-mfpu-fpa.d
deleted file mode 100644
index 498d46a2b15..00000000000
--- a/gas/testsuite/gas/arm/attr-mfpu-fpa.d
+++ /dev/null
@@ -1,11 +0,0 @@
-# name: attributes for -mfpu=3Dfpa
-# source: blank.s
-# as: -mfpu=3Dfpa
-# readelf: -A
-# This test is only valid on EABI based ports.
-# target: *-*-*eabi* *-*-nacl*
-
-Attribute Section: aeabi
-File Attributes
-  Tag_ARM_ISA_use: Yes
-  Tag_THUMB_ISA_use: Thumb-1
diff --git a/gas/testsuite/gas/arm/attr-mfpu-fpa10.d b/gas/testsuite/gas/ar=
m/attr-mfpu-fpa10.d
deleted file mode 100644
index 73b25f0ea12..00000000000
--- a/gas/testsuite/gas/arm/attr-mfpu-fpa10.d
+++ /dev/null
@@ -1,11 +0,0 @@
-# name: attributes for -mfpu=3Dfpa10
-# source: blank.s
-# as: -mfpu=3Dfpa10
-# readelf: -A
-# This test is only valid on EABI based ports.
-# target: *-*-*eabi* *-*-nacl*
-
-Attribute Section: aeabi
-File Attributes
-  Tag_ARM_ISA_use: Yes
-  Tag_THUMB_ISA_use: Thumb-1
diff --git a/gas/testsuite/gas/arm/attr-mfpu-fpa11.d b/gas/testsuite/gas/ar=
m/attr-mfpu-fpa11.d
deleted file mode 100644
index 4c655f241bf..00000000000
--- a/gas/testsuite/gas/arm/attr-mfpu-fpa11.d
+++ /dev/null
@@ -1,11 +0,0 @@
-# name: attributes for -mfpu=3Dfpa11
-# source: blank.s
-# as: -mfpu=3Dfpa11
-# readelf: -A
-# This test is only valid on EABI based ports.
-# target: *-*-*eabi* *-*-nacl*
-
-Attribute Section: aeabi
-File Attributes
-  Tag_ARM_ISA_use: Yes
-  Tag_THUMB_ISA_use: Thumb-1
diff --git a/gas/testsuite/gas/arm/attr-mfpu-fpe.d b/gas/testsuite/gas/arm/=
attr-mfpu-fpe.d
deleted file mode 100644
index 536acfb15f4..00000000000
--- a/gas/testsuite/gas/arm/attr-mfpu-fpe.d
+++ /dev/null
@@ -1,11 +0,0 @@
-# name: attributes for -mfpu=3Dfpe
-# source: blank.s
-# as: -mfpu=3Dfpe
-# readelf: -A
-# This test is only valid on EABI based ports.
-# target: *-*-*eabi* *-*-nacl*
-
-Attribute Section: aeabi
-File Attributes
-  Tag_ARM_ISA_use: Yes
-  Tag_THUMB_ISA_use: Thumb-1
diff --git a/gas/testsuite/gas/arm/attr-mfpu-fpe2.d b/gas/testsuite/gas/arm=
/attr-mfpu-fpe2.d
deleted file mode 100644
index 29638ecf4ee..00000000000
--- a/gas/testsuite/gas/arm/attr-mfpu-fpe2.d
+++ /dev/null
@@ -1,11 +0,0 @@
-# name: attributes for -mfpu=3Dfpe2
-# source: blank.s
-# as: -mfpu=3Dfpe2
-# readelf: -A
-# This test is only valid on EABI based ports.
-# target: *-*-*eabi* *-*-nacl*
-
-Attribute Section: aeabi
-File Attributes
-  Tag_ARM_ISA_use: Yes
-  Tag_THUMB_ISA_use: Thumb-1
diff --git a/gas/testsuite/gas/arm/attr-mfpu-fpe3.d b/gas/testsuite/gas/arm=
/attr-mfpu-fpe3.d
deleted file mode 100644
index 9f13b0fb416..00000000000
--- a/gas/testsuite/gas/arm/attr-mfpu-fpe3.d
+++ /dev/null
@@ -1,11 +0,0 @@
-# name: attributes for -mfpu=3Dfpe3
-# source: blank.s
-# as: -mfpu=3Dfpe3
-# readelf: -A
-# This test is only valid on EABI based ports.
-# target: *-*-*eabi* *-*-nacl*
-
-Attribute Section: aeabi
-File Attributes
-  Tag_ARM_ISA_use: Yes
-  Tag_THUMB_ISA_use: Thumb-1
diff --git a/gas/testsuite/gas/arm/attr-mfpu-softfpa.d b/gas/testsuite/gas/=
arm/attr-mfpu-softfpa.d
deleted file mode 100644
index 8eb432b4bf9..00000000000
--- a/gas/testsuite/gas/arm/attr-mfpu-softfpa.d
+++ /dev/null
@@ -1,11 +0,0 @@
-# name: attributes for -mfpu=3Dsoftfpa
-# source: blank.s
-# as: -mfpu=3Dsoftfpa
-# readelf: -A
-# This test is only valid on EABI based ports.
-# target: *-*-*eabi* *-*-nacl*
-
-Attribute Section: aeabi
-File Attributes
-  Tag_ARM_ISA_use: Yes
-  Tag_THUMB_ISA_use: Thumb-1
diff --git a/gas/testsuite/gas/arm/attr-override-mcpu.s b/gas/testsuite/gas=
/arm/attr-override-mcpu.s
index bc7a04c8d60..f924aa7fad5 100644
--- a/gas/testsuite/gas/arm/attr-override-mcpu.s
+++ b/gas/testsuite/gas/arm/attr-override-mcpu.s
@@ -1,2 +1,2 @@
 	.cpu arm7tdmi
-	.fpu softfpa
+	.fpu softvfp
diff --git a/gas/testsuite/gas/arm/float.d b/gas/testsuite/gas/arm/float.d
deleted file mode 100644
index 9faaf209158..00000000000
--- a/gas/testsuite/gas/arm/float.d
+++ /dev/null
@@ -1,131 +0,0 @@
-# name: Core floating point instructions
-# as: -mcpu=3Darm7tdmi -mfpu=3Dfpa
-# objdump: -dr --prefix-addresses --show-raw-insn
-
-.*: +file format .*arm.*
-
-Disassembly of section .text:
-0+000 <[^>]+> ee088101 ?	mvfe	f0, f1
-0+004 <[^>]+> 0e08b105 ?	mvfeqe	f3, f5
-0+008 <[^>]+> 0e00c189 ?	mvfeqd	f4, #1\.0
-0+00c <[^>]+> ee00c107 ?	mvfs	f4, f7
-0+010 <[^>]+> ee008121 ?	mvfsp	f0, f1
-0+014 <[^>]+> ee00b1c4 ?	mvfdm	f3, f4
-0+018 <[^>]+> ee08f167 ?	mvfez	f7, f7
-0+01c <[^>]+> ee09010a ?	adfe	f0, f1, #2\.0
-0+020 <[^>]+> 0e0a110e ?	adfeqe	f1, f2, #0\.5
-0+024 <[^>]+> ee043145 ?	adfsm	f3, f4, f5
-0+028 <[^>]+> ee20018a ?	sufd	f0, f0, #2\.0
-0+02c <[^>]+> ee22110f ?	sufs	f1, f2, #10\.0
-0+030 <[^>]+> 1e2c3165 ?	sufneez	f3, f4, f5
-0+034 <[^>]+> ee311108 ?	rsfs	f1, f1, #0\.0
-0+038 <[^>]+> ee3031ad ?	rsfdp	f3, f0, #5\.0
-0+03c <[^>]+> de367180 ?	rsfled	f7, f6, f0
-0+040 <[^>]+> ee100180 ?	mufd	f0, f0, f0
-0+044 <[^>]+> ee1a116b ?	mufez	f1, f2, #3\.0
-0+048 <[^>]+> ee10010c ?	mufs	f0, f0, #4\.0
-0+04c <[^>]+> ee400189 ?	dvfd	f0, f0, #1\.0
-0+050 <[^>]+> ee49016f ?	dvfez	f0, f1, #10\.0
-0+054 <[^>]+> 4e443145 ?	dvfmism	f3, f4, f5
-0+058 <[^>]+> ee59010f ?	rdfe	f0, f1, #10\.0
-0+05c <[^>]+> ee573109 ?	rdfs	f3, f7, #1\.0
-0+060 <[^>]+> 3e5441a3 ?	rdfccdp	f4, f4, f3
-0+064 <[^>]+> ee620183 ?	powd	f0, f2, f3
-0+068 <[^>]+> ee63110f ?	pows	f1, f3, #10\.0
-0+06c <[^>]+> 2e6f4169 ?	powcsez	f4, f7, #1\.0
-0+070 <[^>]+> ee767107 ?	rpws	f7, f6, f7
-0+074 <[^>]+> 0e710182 ?	rpweqd	f0, f1, f2
-0+078 <[^>]+> ee7a2143 ?	rpwem	f2, f2, f3
-0+07c <[^>]+> ee82118b ?	rmfd	f1, f2, #3\.0
-0+080 <[^>]+> 6e843104 ?	rmfvss	f3, f4, f4
-0+084 <[^>]+> ee8f4120 ?	rmfep	f4, f7, f0
-0+088 <[^>]+> ee910102 ?	fmls	f0, f1, f2
-0+08c <[^>]+> 0e931105 ?	fmleqs	f1, f3, f5
-0+090 <[^>]+> 5e964160 ?	fmlplsz	f4, f6, f0
-0+094 <[^>]+> eea3110f ?	fdvs	f1, f3, #10\.0
-0+098 <[^>]+> eea10122 ?	fdvsp	f0, f1, f2
-0+09c <[^>]+> 2ea44144 ?	fdvcssm	f4, f4, f4
-0+0a0 <[^>]+> eeb11109 ?	frds	f1, f1, #1\.0
-0+0a4 <[^>]+> ceb12100 ?	frdgts	f2, f1, f0
-0+0a8 <[^>]+> ceb44165 ?	frdgtsz	f4, f4, f5
-0+0ac <[^>]+> eec10182 ?	pold	f0, f1, f2
-0+0b0 <[^>]+> eec6416b ?	polsz	f4, f6, #3\.0
-0+0b4 <[^>]+> 0ece5107 ?	poleqe	f5, f6, f7
-0+0b8 <[^>]+> ee108101 ?	mnfs	f0, f1
-0+0bc <[^>]+> ee10818b ?	mnfd	f0, #3\.0
-0+0c0 <[^>]+> ee18816c ?	mnfez	f0, #4\.0
-0+0c4 <[^>]+> 0e188165 ?	mnfeqez	f0, f5
-0+0c8 <[^>]+> ee108124 ?	mnfsp	f0, f4
-0+0cc <[^>]+> ee1091c7 ?	mnfdm	f1, f7
-0+0d0 <[^>]+> ee208181 ?	absd	f0, f1
-0+0d4 <[^>]+> ee20912b ?	abssp	f1, #3\.0
-0+0d8 <[^>]+> 0e28c105 ?	abseqe	f4, f5
-0+0dc <[^>]+> ee309102 ?	rnds	f1, f2
-0+0e0 <[^>]+> ee30b184 ?	rndd	f3, f4
-0+0e4 <[^>]+> 0e38e16c ?	rndeqez	f6, #4\.0
-0+0e8 <[^>]+> ee40d105 ?	sqts	f5, f5
-0+0ec <[^>]+> ee40e1a6 ?	sqtdp	f6, f6
-0+0f0 <[^>]+> 5e48f166 ?	sqtplez	f7, f6
-0+0f4 <[^>]+> ee50810f ?	logs	f0, #10\.0
-0+0f8 <[^>]+> ee58810f ?	loge	f0, #10\.0
-0+0fc <[^>]+> 1e5081e1 ?	lognedz	f0, f1
-0+100 <[^>]+> ee689102 ?	lgne	f1, f2
-0+104 <[^>]+> ee6091e3 ?	lgndz	f1, f3
-0+108 <[^>]+> 7e60b104 ?	lgnvcs	f3, f4
-0+10c <[^>]+> ee709103 ?	exps	f1, f3
-0+110 <[^>]+> ee78b14f ?	expem	f3, #10\.0
-0+114 <[^>]+> 5e70e187 ?	exppld	f6, f7
-0+118 <[^>]+> ee808181 ?	sind	f0, f1
-0+11c <[^>]+> ee809142 ?	sinsm	f1, f2
-0+120 <[^>]+> ce88c10d ?	singte	f4, #5\.0
-0+124 <[^>]+> ee909183 ?	cosd	f1, f3
-0+128 <[^>]+> ee98c145 ?	cosem	f4, f5
-0+12c <[^>]+> 1e90e1a1 ?	cosnedp	f6, f1
-0+130 <[^>]+> eea89105 ?	tane	f1, f5
-0+134 <[^>]+> eea0c167 ?	tansz	f4, f7
-0+138 <[^>]+> aea091ec ?	tangedz	f1, #4\.0
-0+13c <[^>]+> eeb8c105 ?	asne	f4, f5
-0+140 <[^>]+> eeb0e12e ?	asnsp	f6, #0\.5
-0+144 <[^>]+> 4eb0d1e5 ?	asnmidz	f5, f5
-0+148 <[^>]+> eec0d106 ?	acss	f5, f6
-0+14c <[^>]+> eec0e180 ?	acsd	f6, f0
-0+150 <[^>]+> 2ec8914e ?	acscsem	f1, #0\.5
-0+154 <[^>]+> eed88105 ?	atne	f0, f5
-0+158 <[^>]+> eed0916d ?	atnsz	f1, #5\.0
-0+15c <[^>]+> bed0b182 ?	atnltd	f3, f2
-0+160 <[^>]+> eee8d104 ?	urde	f5, f4
-0+164 <[^>]+> eef8e105 ?	nrme	f6, f5
-0+168 <[^>]+> 5ef0f1e5 ?	nrmpldz	f7, f5
-0+16c <[^>]+> ee008130 ?	fltsp	f0, r8
-0+170 <[^>]+> ee090110 ?	flte	f1, r0
-0+174 <[^>]+> 0e0571f0 ?	flteqdz	f5, r7
-0+178 <[^>]+> ee100111 ?	fix	r0, f1
-0+17c <[^>]+> ee101177 ?	fixz	r1, f7
-0+180 <[^>]+> 2e105155 ?	fixcsm	r5, f5
-0+184 <[^>]+> ee400110 ?	wfc	r0
-0+188 <[^>]+> ee201110 ?	wfs	r1
-0+18c <[^>]+> 0e302110 ?	rfseq	r2
-0+190 <[^>]+> ee504110 ?	rfc	r4
-0+194 <[^>]+> ee90f119 ?	cmf	f0, #1\.0
-0+198 <[^>]+> ee91f112 ?	cmf	f1, f2
-0+19c <[^>]+> 0e90f111 ?	cmfeq	f0, f1
-0+1a0 <[^>]+> eeb0f11b ?	cnf	f0, #3\.0
-0+1a4 <[^>]+> eeb1f11e ?	cnf	f1, #0\.5
-0+1a8 <[^>]+> 6eb3f114 ?	cnfvs	f3, f4
-0+1ac <[^>]+> eed0f111 ?	cmfe	f0, f1
-0+1b0 <[^>]+> 0ed1f112 ?	cmfeeq	f1, f2
-0+1b4 <[^>]+> 0ed3f11d ?	cmfeeq	f3, #5\.0
-0+1b8 <[^>]+> eef1f113 ?	cnfe	f1, f3
-0+1bc <[^>]+> 0ef3f114 ?	cnfeeq	f3, f4
-0+1c0 <[^>]+> 0ef4f117 ?	cnfeeq	f4, f7
-0+1c4 <[^>]+> eef4f11d ?	cnfe	f4, #5\.0
-0+1c8 <[^>]+> ed900200 ?	lfm	f0, 4, \[r0\]
-0+1cc <[^>]+> ed900200 ?	lfm	f0, 4, \[r0\]
-0+1d0 <[^>]+> ed911210 ?	lfm	f1, 4, \[r1, #64\].*
-0+1d4 <[^>]+> edae22ff ?	sfm	f2, 4, \[lr, #1020\]!.*
-0+1d8 <[^>]+> 0c68f2ff ?	sfmeq	f7, 3, \[r8\], #-1020.*
-0+1dc <[^>]+> eddf6200 ?	lfm	f6, 2, \[pc\]	@ .* <l\+.*>
-0+1e0 <[^>]+> eca8f203 ?	sfm	f7, 1, \[r8\], #12
-0+1e4 <[^>]+> 0d16520c ?	lfmeq	f5, 4, \[r6, #-48\].*
-0+1e8 <[^>]+> 1d42c209 ?	sfmne	f4, 3, \[r2, #-36\].*
-0+1ec <[^>]+> 1d62c209 ?	sfmne	f4, 3, \[r2, #-36\]!.*
diff --git a/gas/testsuite/gas/arm/float.s b/gas/testsuite/gas/arm/float.s
deleted file mode 100644
index 437d298ddd5..00000000000
--- a/gas/testsuite/gas/arm/float.s
+++ /dev/null
@@ -1,163 +0,0 @@
-	.text
-	.align 0
-l:
-	mvfe	f0, f1
-	mvfeqe	f3, f5
-	mvfeqd	f4, #1.0
-	mvfs	f4, f7
-	mvfsp	f0, f1
-	mvfdm	f3, f4
-	mvfez	f7, f7
-
-	adfe	f0, f1, #2.0
-	adfeqe	f1, f2, #0.5
-	adfsm	f3, f4, f5
-=09
-	sufd	f0, f0, #2.0
-	sufs	f1, f2, #10.0
-	sufneez f3, f4, f5
-
-	rsfs	f1, f1, #0.0
-	rsfdp	f3, f0, #5.0
-	rsfled	f7, f6, f0
-
-	mufd	f0, f0, f0
-	mufez	f1, f2, #3.0
-	mufals	f0, f0, #4.0
-
-	dvfd	f0, f0, #1.0000
-	dvfez	f0, f1, #10e0
-	dvfmism f3, f4, f5
-
-	rdfe	f0, f1, #1.0e1
-	rdfs	f3, f7, #0f1
-	rdfccdp	f4, f4, f3
-
-	powd	f0, f2, f3
-	pows	f1, f3, #0e1e1
-	powcsez	f4, f7, #1
-
-	rpws	f7, f6, f7
-	rpweqd	f0, f1, f2
-	rpwem	f2, f2, f3
-
-	rmfd	f1, f2, #3
-	rmfvss	f3, f4, f4
-	rmfep	f4, f7, f0
-
-	fmls	f0, f1, f2
-	fmleqs	f1, f3, f5
-	fmlplsz	f4, f6, f0
-
-	fdvs	f1, f3, #10
-	fdvsp	f0, f1, f2
-	fdvhssm	f4, f4, f4
-
-	frds	f1, f1, #1.0
-	frdgts	f2, f1, f0
-	frdgtsz	f4, f4, f5
-
-	pold	f0, f1, f2
-	polsz	f4, f6, #3.0
-	poleqe	f5, f6, f7
-
-	mnfs	f0, f1
-	mnfd	f0, #3.0
-	mnfez	f0, #4.0
-	mnfeqez f0, f5
-	mnfsp	f0, f4
-	mnfdm	f1, f7
-
-	absd	f0, f1
-	abssp	f1, #3.0
-	abseqe	f4, f5
-
-	rnds	f1, f2
-	rndd	f3, f4
-	rndeqez	f6, #4.0
-
-	sqts	f5, f5
-	sqtdp	f6, f6
-	sqtplez f7, f6
-
-	logs	f0, #10
-	loge	f0, #0f10
-	lognedz	f0, f1
-
-	lgne	f1, f2
-	lgndz	f1, f3
-	lgnvcs	f3, f4
-
-	exps	f1, f3
-	expem	f3, #10.0
-	exppld	f6, f7
-
-	sind	f0, f1
-	sinsm	f1, f2
-	singte	f4, #5
-
-	cosd	f1, f3
-	cosem	f4, f5
-	cosnedp	f6, f1
-
-	tane	f1, f5
-	tansz	f4, f7
-	tangedz	f1, #4.0
-
-	asne	f4, f5
-	asnsp	f6, #5e-1
-	asnmidz	f5, f5
-
-	acss	f5, f6
-	acsd	f6, f0
-	acshsem	f1, #0.05e1
-
-	atne	f0, f5
-	atnsz	f1, #5
-	atnltd	f3, f2
-
-	urde	f5, f4
-	nrme	f6, f5
-	nrmpldz	f7, f5
-
-	fltsp	f0, r8
-	flte	f1, r0
-	flteqdz	f5, r7
-
-	fix	r0, f1
-	fixz	r1, f7
-	fixcsm	r5, f5
-
-	wfc	r0
-	wfs	r1
-	rfseq	r2
-	rfc	r4
-
-	cmf	f0, #1
-	cmf	f1, f2
-	cmfeq	f0, f1
-
-	cnf	f0, #3
-	cnf	f1, #0.5
-	cnfvs	f3, f4
-
-	cmfe	f0, f1
-	cmfeeq	f1, f2
-	cmfeqe	f3, #5.0
-
-	cnfe	f1, f3
-	cnfeeq	f3, f4
-	cnfeqe	f4, f7
-	cnfale	f4, #5.0
-
-	lfm	f0, 4, [r0]
-	lfm	f0, 4, [r0, #0]
-	lfm	f1, 4, [r1, #64]
-	sfm	f2, 4, [r14, #1020]!
-	sfmeq	f7, 3, [r8], #-1020
-
-	lfmfd	f6, 2, [r15]
-	sfmea	f7, 1, [r8]!
-	lfmeqea	f5, 4, [r6]
-	sfmnefd	f4, 3, [r2]
-	sfmnefd	f4, 3, [r2]!
diff --git a/gas/testsuite/gas/arm/fp-save.d b/gas/testsuite/gas/arm/fp-sav=
e.d
deleted file mode 100644
index 7c367ddca43..00000000000
--- a/gas/testsuite/gas/arm/fp-save.d
+++ /dev/null
@@ -1,9 +0,0 @@
-#objdump: -dr --prefix-addresses --show-raw-insn
-#name: PR5712 - saving FP registers
-#notarget: *-*-pe *-*-wince
-#as: -mfpu=3Dfpa
-
-.*: *file format .*arm.*
-
-Disassembly of section .text:
-0+00 <[^>]*> ed2dc203[ 	]+sfm[ 	]+f4, 1, \[sp, #-12\]!
diff --git a/gas/testsuite/gas/arm/fp-save.s b/gas/testsuite/gas/arm/fp-sav=
e.s
deleted file mode 100644
index d0a572aab40..00000000000
--- a/gas/testsuite/gas/arm/fp-save.s
+++ /dev/null
@@ -1,4 +0,0 @@
-	.fnstart=0D
-	sfmfd   f4, 1, [sp]!=0D
-	.save f4, 1=0D
-	.fnend=0D
diff --git a/gas/testsuite/gas/arm/fpa-dyadic.d b/gas/testsuite/gas/arm/fpa=
-dyadic.d
deleted file mode 100644
index f603bbff841..00000000000
--- a/gas/testsuite/gas/arm/fpa-dyadic.d
+++ /dev/null
@@ -1,166 +0,0 @@
-#objdump: -dr --prefix-addresses --show-raw-insn
-#name: FPA Dyadic instructions
-#as: -mfpu=3Dfpa -mcpu=3Darm7m
-
-# Test FPA Dyadic instructions
-# This test should work for both big and little-endian assembly.
-
-.*: *file format .*arm.*
-
-Disassembly of section .text:
-0+000 <[^>]*> ee000100 ?	adfs	f0, f0, f0
-0+004 <[^>]*> ee000120 ?	adfsp	f0, f0, f0
-0+008 <[^>]*> ee000140 ?	adfsm	f0, f0, f0
-0+00c <[^>]*> ee000160 ?	adfsz	f0, f0, f0
-0+010 <[^>]*> ee000180 ?	adfd	f0, f0, f0
-0+014 <[^>]*> ee0001a0 ?	adfdp	f0, f0, f0
-0+018 <[^>]*> ee0001c0 ?	adfdm	f0, f0, f0
-0+01c <[^>]*> ee0001e0 ?	adfdz	f0, f0, f0
-0+020 <[^>]*> ee080100 ?	adfe	f0, f0, f0
-0+024 <[^>]*> ee080120 ?	adfep	f0, f0, f0
-0+028 <[^>]*> ee080140 ?	adfem	f0, f0, f0
-0+02c <[^>]*> ee080160 ?	adfez	f0, f0, f0
-0+030 <[^>]*> ee200100 ?	sufs	f0, f0, f0
-0+034 <[^>]*> ee200120 ?	sufsp	f0, f0, f0
-0+038 <[^>]*> ee200140 ?	sufsm	f0, f0, f0
-0+03c <[^>]*> ee200160 ?	sufsz	f0, f0, f0
-0+040 <[^>]*> ee200180 ?	sufd	f0, f0, f0
-0+044 <[^>]*> ee2001a0 ?	sufdp	f0, f0, f0
-0+048 <[^>]*> ee2001c0 ?	sufdm	f0, f0, f0
-0+04c <[^>]*> ee2001e0 ?	sufdz	f0, f0, f0
-0+050 <[^>]*> ee280100 ?	sufe	f0, f0, f0
-0+054 <[^>]*> ee280120 ?	sufep	f0, f0, f0
-0+058 <[^>]*> ee280140 ?	sufem	f0, f0, f0
-0+05c <[^>]*> ee280160 ?	sufez	f0, f0, f0
-0+060 <[^>]*> ee300100 ?	rsfs	f0, f0, f0
-0+064 <[^>]*> ee300120 ?	rsfsp	f0, f0, f0
-0+068 <[^>]*> ee300140 ?	rsfsm	f0, f0, f0
-0+06c <[^>]*> ee300160 ?	rsfsz	f0, f0, f0
-0+070 <[^>]*> ee300180 ?	rsfd	f0, f0, f0
-0+074 <[^>]*> ee3001a0 ?	rsfdp	f0, f0, f0
-0+078 <[^>]*> ee3001c0 ?	rsfdm	f0, f0, f0
-0+07c <[^>]*> ee3001e0 ?	rsfdz	f0, f0, f0
-0+080 <[^>]*> ee380100 ?	rsfe	f0, f0, f0
-0+084 <[^>]*> ee380120 ?	rsfep	f0, f0, f0
-0+088 <[^>]*> ee380140 ?	rsfem	f0, f0, f0
-0+08c <[^>]*> ee380160 ?	rsfez	f0, f0, f0
-0+090 <[^>]*> ee100100 ?	mufs	f0, f0, f0
-0+094 <[^>]*> ee100120 ?	mufsp	f0, f0, f0
-0+098 <[^>]*> ee100140 ?	mufsm	f0, f0, f0
-0+09c <[^>]*> ee100160 ?	mufsz	f0, f0, f0
-0+0a0 <[^>]*> ee100180 ?	mufd	f0, f0, f0
-0+0a4 <[^>]*> ee1001a0 ?	mufdp	f0, f0, f0
-0+0a8 <[^>]*> ee1001c0 ?	mufdm	f0, f0, f0
-0+0ac <[^>]*> ee1001e0 ?	mufdz	f0, f0, f0
-0+0b0 <[^>]*> ee180100 ?	mufe	f0, f0, f0
-0+0b4 <[^>]*> ee180120 ?	mufep	f0, f0, f0
-0+0b8 <[^>]*> ee180140 ?	mufem	f0, f0, f0
-0+0bc <[^>]*> ee180160 ?	mufez	f0, f0, f0
-0+0c0 <[^>]*> ee400100 ?	dvfs	f0, f0, f0
-0+0c4 <[^>]*> ee400120 ?	dvfsp	f0, f0, f0
-0+0c8 <[^>]*> ee400140 ?	dvfsm	f0, f0, f0
-0+0cc <[^>]*> ee400160 ?	dvfsz	f0, f0, f0
-0+0d0 <[^>]*> ee400180 ?	dvfd	f0, f0, f0
-0+0d4 <[^>]*> ee4001a0 ?	dvfdp	f0, f0, f0
-0+0d8 <[^>]*> ee4001c0 ?	dvfdm	f0, f0, f0
-0+0dc <[^>]*> ee4001e0 ?	dvfdz	f0, f0, f0
-0+0e0 <[^>]*> ee480100 ?	dvfe	f0, f0, f0
-0+0e4 <[^>]*> ee480120 ?	dvfep	f0, f0, f0
-0+0e8 <[^>]*> ee480140 ?	dvfem	f0, f0, f0
-0+0ec <[^>]*> ee480160 ?	dvfez	f0, f0, f0
-0+0f0 <[^>]*> ee500100 ?	rdfs	f0, f0, f0
-0+0f4 <[^>]*> ee500120 ?	rdfsp	f0, f0, f0
-0+0f8 <[^>]*> ee500140 ?	rdfsm	f0, f0, f0
-0+0fc <[^>]*> ee500160 ?	rdfsz	f0, f0, f0
-0+100 <[^>]*> ee500180 ?	rdfd	f0, f0, f0
-0+104 <[^>]*> ee5001a0 ?	rdfdp	f0, f0, f0
-0+108 <[^>]*> ee5001c0 ?	rdfdm	f0, f0, f0
-0+10c <[^>]*> ee5001e0 ?	rdfdz	f0, f0, f0
-0+110 <[^>]*> ee580100 ?	rdfe	f0, f0, f0
-0+114 <[^>]*> ee580120 ?	rdfep	f0, f0, f0
-0+118 <[^>]*> ee580140 ?	rdfem	f0, f0, f0
-0+11c <[^>]*> ee580160 ?	rdfez	f0, f0, f0
-0+120 <[^>]*> ee600100 ?	pows	f0, f0, f0
-0+124 <[^>]*> ee600120 ?	powsp	f0, f0, f0
-0+128 <[^>]*> ee600140 ?	powsm	f0, f0, f0
-0+12c <[^>]*> ee600160 ?	powsz	f0, f0, f0
-0+130 <[^>]*> ee600180 ?	powd	f0, f0, f0
-0+134 <[^>]*> ee6001a0 ?	powdp	f0, f0, f0
-0+138 <[^>]*> ee6001c0 ?	powdm	f0, f0, f0
-0+13c <[^>]*> ee6001e0 ?	powdz	f0, f0, f0
-0+140 <[^>]*> ee680100 ?	powe	f0, f0, f0
-0+144 <[^>]*> ee680120 ?	powep	f0, f0, f0
-0+148 <[^>]*> ee680140 ?	powem	f0, f0, f0
-0+14c <[^>]*> ee680160 ?	powez	f0, f0, f0
-0+150 <[^>]*> ee700100 ?	rpws	f0, f0, f0
-0+154 <[^>]*> ee700120 ?	rpwsp	f0, f0, f0
-0+158 <[^>]*> ee700140 ?	rpwsm	f0, f0, f0
-0+15c <[^>]*> ee700160 ?	rpwsz	f0, f0, f0
-0+160 <[^>]*> ee700180 ?	rpwd	f0, f0, f0
-0+164 <[^>]*> ee7001a0 ?	rpwdp	f0, f0, f0
-0+168 <[^>]*> ee7001c0 ?	rpwdm	f0, f0, f0
-0+16c <[^>]*> ee7001e0 ?	rpwdz	f0, f0, f0
-0+170 <[^>]*> ee780100 ?	rpwe	f0, f0, f0
-0+174 <[^>]*> ee780120 ?	rpwep	f0, f0, f0
-0+178 <[^>]*> ee780140 ?	rpwem	f0, f0, f0
-0+17c <[^>]*> ee780160 ?	rpwez	f0, f0, f0
-0+180 <[^>]*> ee800100 ?	rmfs	f0, f0, f0
-0+184 <[^>]*> ee800120 ?	rmfsp	f0, f0, f0
-0+188 <[^>]*> ee800140 ?	rmfsm	f0, f0, f0
-0+18c <[^>]*> ee800160 ?	rmfsz	f0, f0, f0
-0+190 <[^>]*> ee800180 ?	rmfd	f0, f0, f0
-0+194 <[^>]*> ee8001a0 ?	rmfdp	f0, f0, f0
-0+198 <[^>]*> ee8001c0 ?	rmfdm	f0, f0, f0
-0+19c <[^>]*> ee8001e0 ?	rmfdz	f0, f0, f0
-0+1a0 <[^>]*> ee880100 ?	rmfe	f0, f0, f0
-0+1a4 <[^>]*> ee880120 ?	rmfep	f0, f0, f0
-0+1a8 <[^>]*> ee880140 ?	rmfem	f0, f0, f0
-0+1ac <[^>]*> ee880160 ?	rmfez	f0, f0, f0
-0+1b0 <[^>]*> ee900100 ?	fmls	f0, f0, f0
-0+1b4 <[^>]*> ee900120 ?	fmlsp	f0, f0, f0
-0+1b8 <[^>]*> ee900140 ?	fmlsm	f0, f0, f0
-0+1bc <[^>]*> ee900160 ?	fmlsz	f0, f0, f0
-0+1c0 <[^>]*> ee900180 ?	fmld	f0, f0, f0
-0+1c4 <[^>]*> ee9001a0 ?	fmldp	f0, f0, f0
-0+1c8 <[^>]*> ee9001c0 ?	fmldm	f0, f0, f0
-0+1cc <[^>]*> ee9001e0 ?	fmldz	f0, f0, f0
-0+1d0 <[^>]*> ee980100 ?	fmle	f0, f0, f0
-0+1d4 <[^>]*> ee980120 ?	fmlep	f0, f0, f0
-0+1d8 <[^>]*> ee980140 ?	fmlem	f0, f0, f0
-0+1dc <[^>]*> ee980160 ?	fmlez	f0, f0, f0
-0+1e0 <[^>]*> eea00100 ?	fdvs	f0, f0, f0
-0+1e4 <[^>]*> eea00120 ?	fdvsp	f0, f0, f0
-0+1e8 <[^>]*> eea00140 ?	fdvsm	f0, f0, f0
-0+1ec <[^>]*> eea00160 ?	fdvsz	f0, f0, f0
-0+1f0 <[^>]*> eea00180 ?	fdvd	f0, f0, f0
-0+1f4 <[^>]*> eea001a0 ?	fdvdp	f0, f0, f0
-0+1f8 <[^>]*> eea001c0 ?	fdvdm	f0, f0, f0
-0+1fc <[^>]*> eea001e0 ?	fdvdz	f0, f0, f0
-0+200 <[^>]*> eea80100 ?	fdve	f0, f0, f0
-0+204 <[^>]*> eea80120 ?	fdvep	f0, f0, f0
-0+208 <[^>]*> eea80140 ?	fdvem	f0, f0, f0
-0+20c <[^>]*> eea80160 ?	fdvez	f0, f0, f0
-0+210 <[^>]*> eeb00100 ?	frds	f0, f0, f0
-0+214 <[^>]*> eeb00120 ?	frdsp	f0, f0, f0
-0+218 <[^>]*> eeb00140 ?	frdsm	f0, f0, f0
-0+21c <[^>]*> eeb00160 ?	frdsz	f0, f0, f0
-0+220 <[^>]*> eeb00180 ?	frdd	f0, f0, f0
-0+224 <[^>]*> eeb001a0 ?	frddp	f0, f0, f0
-0+228 <[^>]*> eeb001c0 ?	frddm	f0, f0, f0
-0+22c <[^>]*> eeb001e0 ?	frddz	f0, f0, f0
-0+230 <[^>]*> eeb80100 ?	frde	f0, f0, f0
-0+234 <[^>]*> eeb80120 ?	frdep	f0, f0, f0
-0+238 <[^>]*> eeb80140 ?	frdem	f0, f0, f0
-0+23c <[^>]*> eeb80160 ?	frdez	f0, f0, f0
-0+240 <[^>]*> eec00100 ?	pols	f0, f0, f0
-0+244 <[^>]*> eec00120 ?	polsp	f0, f0, f0
-0+248 <[^>]*> eec00140 ?	polsm	f0, f0, f0
-0+24c <[^>]*> eec00160 ?	polsz	f0, f0, f0
-0+250 <[^>]*> eec00180 ?	pold	f0, f0, f0
-0+254 <[^>]*> eec001a0 ?	poldp	f0, f0, f0
-0+258 <[^>]*> eec001c0 ?	poldm	f0, f0, f0
-0+25c <[^>]*> eec001e0 ?	poldz	f0, f0, f0
-0+260 <[^>]*> eec80100 ?	pole	f0, f0, f0
-0+264 <[^>]*> eec80120 ?	polep	f0, f0, f0
-0+268 <[^>]*> eec80140 ?	polem	f0, f0, f0
-0+26c <[^>]*> eec80160 ?	polez	f0, f0, f0
diff --git a/gas/testsuite/gas/arm/fpa-dyadic.s b/gas/testsuite/gas/arm/fpa=
-dyadic.s
deleted file mode 100644
index aebcd2b9c2e..00000000000
--- a/gas/testsuite/gas/arm/fpa-dyadic.s
+++ /dev/null
@@ -1,172 +0,0 @@
-	.text
-	.globl F
-F:
-	adfs	f0, f0, f0
-	adfsp	f0, f0, f0
-	adfsm	f0, f0, f0
-	adfsz	f0, f0, f0
-	adfd	f0, f0, f0
-	adfdp	f0, f0, f0
-	adfdm	f0, f0, f0
-	adfdz	f0, f0, f0
-	adfe	f0, f0, f0
-	adfep	f0, f0, f0
-	adfem	f0, f0, f0
-	adfez	f0, f0, f0
-
-	sufs	f0, f0, f0
-	sufsp	f0, f0, f0
-	sufsm	f0, f0, f0
-	sufsz	f0, f0, f0
-	sufd	f0, f0, f0
-	sufdp	f0, f0, f0
-	sufdm	f0, f0, f0
-	sufdz	f0, f0, f0
-	sufe	f0, f0, f0
-	sufep	f0, f0, f0
-	sufem	f0, f0, f0
-	sufez	f0, f0, f0
-
-	rsfs	f0, f0, f0
-	rsfsp	f0, f0, f0
-	rsfsm	f0, f0, f0
-	rsfsz	f0, f0, f0
-	rsfd	f0, f0, f0
-	rsfdp	f0, f0, f0
-	rsfdm	f0, f0, f0
-	rsfdz	f0, f0, f0
-	rsfe	f0, f0, f0
-	rsfep	f0, f0, f0
-	rsfem	f0, f0, f0
-	rsfez	f0, f0, f0
-
-	mufs	f0, f0, f0
-	mufsp	f0, f0, f0
-	mufsm	f0, f0, f0
-	mufsz	f0, f0, f0
-	mufd	f0, f0, f0
-	mufdp	f0, f0, f0
-	mufdm	f0, f0, f0
-	mufdz	f0, f0, f0
-	mufe	f0, f0, f0
-	mufep	f0, f0, f0
-	mufem	f0, f0, f0
-	mufez	f0, f0, f0
-
-	dvfs	f0, f0, f0
-	dvfsp	f0, f0, f0
-	dvfsm	f0, f0, f0
-	dvfsz	f0, f0, f0
-	dvfd	f0, f0, f0
-	dvfdp	f0, f0, f0
-	dvfdm	f0, f0, f0
-	dvfdz	f0, f0, f0
-	dvfe	f0, f0, f0
-	dvfep	f0, f0, f0
-	dvfem	f0, f0, f0
-	dvfez	f0, f0, f0
-
-	rdfs	f0, f0, f0
-	rdfsp	f0, f0, f0
-	rdfsm	f0, f0, f0
-	rdfsz	f0, f0, f0
-	rdfd	f0, f0, f0
-	rdfdp	f0, f0, f0
-	rdfdm	f0, f0, f0
-	rdfdz	f0, f0, f0
-	rdfe	f0, f0, f0
-	rdfep	f0, f0, f0
-	rdfem	f0, f0, f0
-	rdfez	f0, f0, f0
-
-	pows	f0, f0, f0
-	powsp	f0, f0, f0
-	powsm	f0, f0, f0
-	powsz	f0, f0, f0
-	powd	f0, f0, f0
-	powdp	f0, f0, f0
-	powdm	f0, f0, f0
-	powdz	f0, f0, f0
-	powe	f0, f0, f0
-	powep	f0, f0, f0
-	powem	f0, f0, f0
-	powez	f0, f0, f0
-
-	rpws	f0, f0, f0
-	rpwsp	f0, f0, f0
-	rpwsm	f0, f0, f0
-	rpwsz	f0, f0, f0
-	rpwd	f0, f0, f0
-	rpwdp	f0, f0, f0
-	rpwdm	f0, f0, f0
-	rpwdz	f0, f0, f0
-	rpwe	f0, f0, f0
-	rpwep	f0, f0, f0
-	rpwem	f0, f0, f0
-	rpwez	f0, f0, f0
-
-	rmfs	f0, f0, f0
-	rmfsp	f0, f0, f0
-	rmfsm	f0, f0, f0
-	rmfsz	f0, f0, f0
-	rmfd	f0, f0, f0
-	rmfdp	f0, f0, f0
-	rmfdm	f0, f0, f0
-	rmfdz	f0, f0, f0
-	rmfe	f0, f0, f0
-	rmfep	f0, f0, f0
-	rmfem	f0, f0, f0
-	rmfez	f0, f0, f0
-
-	fmls	f0, f0, f0
-	fmlsp	f0, f0, f0
-	fmlsm	f0, f0, f0
-	fmlsz	f0, f0, f0
-	fmld	f0, f0, f0
-	fmldp	f0, f0, f0
-	fmldm	f0, f0, f0
-	fmldz	f0, f0, f0
-	fmle	f0, f0, f0
-	fmlep	f0, f0, f0
-	fmlem	f0, f0, f0
-	fmlez	f0, f0, f0
-
-	fdvs	f0, f0, f0
-	fdvsp	f0, f0, f0
-	fdvsm	f0, f0, f0
-	fdvsz	f0, f0, f0
-	fdvd	f0, f0, f0
-	fdvdp	f0, f0, f0
-	fdvdm	f0, f0, f0
-	fdvdz	f0, f0, f0
-	fdve	f0, f0, f0
-	fdvep	f0, f0, f0
-	fdvem	f0, f0, f0
-	fdvez	f0, f0, f0
-
-	frds	f0, f0, f0
-	frdsp	f0, f0, f0
-	frdsm	f0, f0, f0
-	frdsz	f0, f0, f0
-	frdd	f0, f0, f0
-	frddp	f0, f0, f0
-	frddm	f0, f0, f0
-	frddz	f0, f0, f0
-	frde	f0, f0, f0
-	frdep	f0, f0, f0
-	frdem	f0, f0, f0
-	frdez	f0, f0, f0
-
-	pols	f0, f0, f0
-	polsp	f0, f0, f0
-	polsm	f0, f0, f0
-	polsz	f0, f0, f0
-	pold	f0, f0, f0
-	poldp	f0, f0, f0
-	poldm	f0, f0, f0
-	poldz	f0, f0, f0
-	pole	f0, f0, f0
-	polep	f0, f0, f0
-	polem	f0, f0, f0
-	polez	f0, f0, f0
-
diff --git a/gas/testsuite/gas/arm/fpa-mem.d b/gas/testsuite/gas/arm/fpa-me=
m.d
deleted file mode 100644
index 4a638e1f900..00000000000
--- a/gas/testsuite/gas/arm/fpa-mem.d
+++ /dev/null
@@ -1,34 +0,0 @@
-#objdump: -dr --prefix-addresses --show-raw-insn
-#name: FPA memory insructions
-#as: -mfpu=3Dfpa10 -mcpu=3Darm7m
-
-# Test FPA memory instructions
-# This test should work for both big and little-endian assembly.
-
-.*: *file format .*arm.*
-
-Disassembly of section .text:
-0+00 <[^>]*> ed900100 ?	ldfs	f0, \[r0\]
-0+04 <[^>]*> ec300101 ?	ldfs	f0, \[r0\], #-4
-0+08 <[^>]*> ed908100 ?	ldfd	f0, \[r0\]
-0+0c <[^>]*> ec308101 ?	ldfd	f0, \[r0\], #-4
-0+10 <[^>]*> edd00100 ?	ldfe	f0, \[r0\]
-0+14 <[^>]*> ec700101 ?	ldfe	f0, \[r0\], #-4
-0+18 <[^>]*> edd08100 ?	ldfp	f0, \[r0\]
-0+1c <[^>]*> ec708101 ?	ldfp	f0, \[r0\], #-4
-0+20 <[^>]*> ed800100 ?	stfs	f0, \[r0\]
-0+24 <[^>]*> ec200101 ?	stfs	f0, \[r0\], #-4
-0+28 <[^>]*> ed808100 ?	stfd	f0, \[r0\]
-0+2c <[^>]*> ec208101 ?	stfd	f0, \[r0\], #-4
-0+30 <[^>]*> edc00100 ?	stfe	f0, \[r0\]
-0+34 <[^>]*> ec600101 ?	stfe	f0, \[r0\], #-4
-0+38 <[^>]*> edc08100 ?	stfp	f0, \[r0\]
-0+3c <[^>]*> ec608101 ?	stfp	f0, \[r0\], #-4
-0+40 <[^>]*> ed900200 ?	lfm	f0, 4, \[r0\]
-0+44 <[^>]*> ed900200 ?	lfm	f0, 4, \[r0\]
-0+48 <[^>]*> ed10020c ?	lfm	f0, 4, \[r0, #-48\].*
-0+4c <[^>]*> ed800200 ?	sfm	f0, 4, \[r0\]
-0+50 <[^>]*> ed00020c ?	sfm	f0, 4, \[r0, #-48\].*
-0+54 <[^>]*> ed800200 ?	sfm	f0, 4, \[r0\]
-0+58 <[^>]*> 5d800100 ?	stfpls	f0, \[r0\]
-0+5c <[^>]*> 5d800100 ?	stfpls	f0, \[r0\]
diff --git a/gas/testsuite/gas/arm/fpa-mem.s b/gas/testsuite/gas/arm/fpa-me=
m.s
deleted file mode 100644
index bcb4ae3ae86..00000000000
--- a/gas/testsuite/gas/arm/fpa-mem.s
+++ /dev/null
@@ -1,32 +0,0 @@
-	.text
-	.globl F
-F:
-	ldfs	f0, [r0]
-	ldfs	f0, [r0], #-4
-	ldfd	f0, [r0]
-	ldfd	f0, [r0], #-4
-	ldfe	f0, [r0]
-	ldfe	f0, [r0], #-4
-	ldfp	f0, [r0]
-	ldfp	f0, [r0], #-4
-
-	stfs	f0, [r0]
-	stfs	f0, [r0], #-4
-	stfd	f0, [r0]
-	stfd	f0, [r0], #-4
-	stfe	f0, [r0]
-	stfe	f0, [r0], #-4
-	stfp	f0, [r0]
-	stfp	f0, [r0], #-4
-	lfm	f0, 4, [r0]
-	lfmfd	f0, 4, [r0]
-	lfmea	f0, 4, [r0]
-	sfm	f0, 4, [r0]
-	sfmfd	f0, 4, [r0]
-	sfmea	f0, 4, [r0]
-=09
-	# Test mnemonic that is ambiguous between infix and suffic
-	# condition codes
-	stfpls	f0, [r0]
-	.syntax unified
-	stfpls	f0, [r0]
diff --git a/gas/testsuite/gas/arm/fpa-monadic.d b/gas/testsuite/gas/arm/fp=
a-monadic.d
deleted file mode 100644
index a688ee4be68..00000000000
--- a/gas/testsuite/gas/arm/fpa-monadic.d
+++ /dev/null
@@ -1,202 +0,0 @@
-#objdump: -dr --prefix-addresses --show-raw-insn
-#name: FPA Monadic instructions
-#as: -mfpu=3Dfpa -mcpu=3Darm7m
-
-# Test FPA Monadic instructions
-# This test should work for both big and little-endian assembly.
-
-.*: *file format .*arm.*
-
-Disassembly of section .text:
-0+000 <[^>]*> ee008100 ?	mvfs	f0, f0
-0+004 <[^>]*> ee008120 ?	mvfsp	f0, f0
-0+008 <[^>]*> ee008140 ?	mvfsm	f0, f0
-0+00c <[^>]*> ee008160 ?	mvfsz	f0, f0
-0+010 <[^>]*> ee008180 ?	mvfd	f0, f0
-0+014 <[^>]*> ee0081a0 ?	mvfdp	f0, f0
-0+018 <[^>]*> ee0081c0 ?	mvfdm	f0, f0
-0+01c <[^>]*> ee0081e0 ?	mvfdz	f0, f0
-0+020 <[^>]*> ee088100 ?	mvfe	f0, f0
-0+024 <[^>]*> ee088120 ?	mvfep	f0, f0
-0+028 <[^>]*> ee088140 ?	mvfem	f0, f0
-0+02c <[^>]*> ee088160 ?	mvfez	f0, f0
-0+030 <[^>]*> ee108100 ?	mnfs	f0, f0
-0+034 <[^>]*> ee108120 ?	mnfsp	f0, f0
-0+038 <[^>]*> ee108140 ?	mnfsm	f0, f0
-0+03c <[^>]*> ee108160 ?	mnfsz	f0, f0
-0+040 <[^>]*> ee108180 ?	mnfd	f0, f0
-0+044 <[^>]*> ee1081a0 ?	mnfdp	f0, f0
-0+048 <[^>]*> ee1081c0 ?	mnfdm	f0, f0
-0+04c <[^>]*> ee1081e0 ?	mnfdz	f0, f0
-0+050 <[^>]*> ee188100 ?	mnfe	f0, f0
-0+054 <[^>]*> ee188120 ?	mnfep	f0, f0
-0+058 <[^>]*> ee188140 ?	mnfem	f0, f0
-0+05c <[^>]*> ee188160 ?	mnfez	f0, f0
-0+060 <[^>]*> ee208100 ?	abss	f0, f0
-0+064 <[^>]*> ee208120 ?	abssp	f0, f0
-0+068 <[^>]*> ee208140 ?	abssm	f0, f0
-0+06c <[^>]*> ee208160 ?	abssz	f0, f0
-0+070 <[^>]*> ee208180 ?	absd	f0, f0
-0+074 <[^>]*> ee2081a0 ?	absdp	f0, f0
-0+078 <[^>]*> ee2081c0 ?	absdm	f0, f0
-0+07c <[^>]*> ee2081e0 ?	absdz	f0, f0
-0+080 <[^>]*> ee288100 ?	abse	f0, f0
-0+084 <[^>]*> ee288120 ?	absep	f0, f0
-0+088 <[^>]*> ee288140 ?	absem	f0, f0
-0+08c <[^>]*> ee288160 ?	absez	f0, f0
-0+090 <[^>]*> ee308100 ?	rnds	f0, f0
-0+094 <[^>]*> ee308120 ?	rndsp	f0, f0
-0+098 <[^>]*> ee308140 ?	rndsm	f0, f0
-0+09c <[^>]*> ee308160 ?	rndsz	f0, f0
-0+0a0 <[^>]*> ee308180 ?	rndd	f0, f0
-0+0a4 <[^>]*> ee3081a0 ?	rnddp	f0, f0
-0+0a8 <[^>]*> ee3081c0 ?	rnddm	f0, f0
-0+0ac <[^>]*> ee3081e0 ?	rnddz	f0, f0
-0+0b0 <[^>]*> ee388100 ?	rnde	f0, f0
-0+0b4 <[^>]*> ee388120 ?	rndep	f0, f0
-0+0b8 <[^>]*> ee388140 ?	rndem	f0, f0
-0+0bc <[^>]*> ee388160 ?	rndez	f0, f0
-0+0c0 <[^>]*> ee408100 ?	sqts	f0, f0
-0+0c4 <[^>]*> ee408120 ?	sqtsp	f0, f0
-0+0c8 <[^>]*> ee408140 ?	sqtsm	f0, f0
-0+0cc <[^>]*> ee408160 ?	sqtsz	f0, f0
-0+0d0 <[^>]*> ee408180 ?	sqtd	f0, f0
-0+0d4 <[^>]*> ee4081a0 ?	sqtdp	f0, f0
-0+0d8 <[^>]*> ee4081c0 ?	sqtdm	f0, f0
-0+0dc <[^>]*> ee4081e0 ?	sqtdz	f0, f0
-0+0e0 <[^>]*> ee488100 ?	sqte	f0, f0
-0+0e4 <[^>]*> ee488120 ?	sqtep	f0, f0
-0+0e8 <[^>]*> ee488140 ?	sqtem	f0, f0
-0+0ec <[^>]*> ee488160 ?	sqtez	f0, f0
-0+0f0 <[^>]*> ee508100 ?	logs	f0, f0
-0+0f4 <[^>]*> ee508120 ?	logsp	f0, f0
-0+0f8 <[^>]*> ee508140 ?	logsm	f0, f0
-0+0fc <[^>]*> ee508160 ?	logsz	f0, f0
-0+100 <[^>]*> ee508180 ?	logd	f0, f0
-0+104 <[^>]*> ee5081a0 ?	logdp	f0, f0
-0+108 <[^>]*> ee5081c0 ?	logdm	f0, f0
-0+10c <[^>]*> ee5081e0 ?	logdz	f0, f0
-0+110 <[^>]*> ee588100 ?	loge	f0, f0
-0+114 <[^>]*> ee588120 ?	logep	f0, f0
-0+118 <[^>]*> ee588140 ?	logem	f0, f0
-0+11c <[^>]*> ee588160 ?	logez	f0, f0
-0+120 <[^>]*> ee608100 ?	lgns	f0, f0
-0+124 <[^>]*> ee608120 ?	lgnsp	f0, f0
-0+128 <[^>]*> ee608140 ?	lgnsm	f0, f0
-0+12c <[^>]*> ee608160 ?	lgnsz	f0, f0
-0+130 <[^>]*> ee608180 ?	lgnd	f0, f0
-0+134 <[^>]*> ee6081a0 ?	lgndp	f0, f0
-0+138 <[^>]*> ee6081c0 ?	lgndm	f0, f0
-0+13c <[^>]*> ee6081e0 ?	lgndz	f0, f0
-0+140 <[^>]*> ee688100 ?	lgne	f0, f0
-0+144 <[^>]*> ee688120 ?	lgnep	f0, f0
-0+148 <[^>]*> ee688140 ?	lgnem	f0, f0
-0+14c <[^>]*> ee688160 ?	lgnez	f0, f0
-0+150 <[^>]*> ee708100 ?	exps	f0, f0
-0+154 <[^>]*> ee708120 ?	expsp	f0, f0
-0+158 <[^>]*> ee708140 ?	expsm	f0, f0
-0+15c <[^>]*> ee708160 ?	expsz	f0, f0
-0+160 <[^>]*> ee708180 ?	expd	f0, f0
-0+164 <[^>]*> ee7081a0 ?	expdp	f0, f0
-0+168 <[^>]*> ee7081c0 ?	expdm	f0, f0
-0+16c <[^>]*> ee7081e0 ?	expdz	f0, f0
-0+170 <[^>]*> ee788100 ?	expe	f0, f0
-0+174 <[^>]*> ee788120 ?	expep	f0, f0
-0+178 <[^>]*> ee788140 ?	expem	f0, f0
-0+17c <[^>]*> ee7081e0 ?	expdz	f0, f0
-0+180 <[^>]*> ee808100 ?	sins	f0, f0
-0+184 <[^>]*> ee808120 ?	sinsp	f0, f0
-0+188 <[^>]*> ee808140 ?	sinsm	f0, f0
-0+18c <[^>]*> ee808160 ?	sinsz	f0, f0
-0+190 <[^>]*> ee808180 ?	sind	f0, f0
-0+194 <[^>]*> ee8081a0 ?	sindp	f0, f0
-0+198 <[^>]*> ee8081c0 ?	sindm	f0, f0
-0+19c <[^>]*> ee8081e0 ?	sindz	f0, f0
-0+1a0 <[^>]*> ee888100 ?	sine	f0, f0
-0+1a4 <[^>]*> ee888120 ?	sinep	f0, f0
-0+1a8 <[^>]*> ee888140 ?	sinem	f0, f0
-0+1ac <[^>]*> ee888160 ?	sinez	f0, f0
-0+1b0 <[^>]*> ee908100 ?	coss	f0, f0
-0+1b4 <[^>]*> ee908120 ?	cossp	f0, f0
-0+1b8 <[^>]*> ee908140 ?	cossm	f0, f0
-0+1bc <[^>]*> ee908160 ?	cossz	f0, f0
-0+1c0 <[^>]*> ee908180 ?	cosd	f0, f0
-0+1c4 <[^>]*> ee9081a0 ?	cosdp	f0, f0
-0+1c8 <[^>]*> ee9081c0 ?	cosdm	f0, f0
-0+1cc <[^>]*> ee9081e0 ?	cosdz	f0, f0
-0+1d0 <[^>]*> ee988100 ?	cose	f0, f0
-0+1d4 <[^>]*> ee988120 ?	cosep	f0, f0
-0+1d8 <[^>]*> ee988140 ?	cosem	f0, f0
-0+1dc <[^>]*> ee988160 ?	cosez	f0, f0
-0+1e0 <[^>]*> eea08100 ?	tans	f0, f0
-0+1e4 <[^>]*> eea08120 ?	tansp	f0, f0
-0+1e8 <[^>]*> eea08140 ?	tansm	f0, f0
-0+1ec <[^>]*> eea08160 ?	tansz	f0, f0
-0+1f0 <[^>]*> eea08180 ?	tand	f0, f0
-0+1f4 <[^>]*> eea081a0 ?	tandp	f0, f0
-0+1f8 <[^>]*> eea081c0 ?	tandm	f0, f0
-0+1fc <[^>]*> eea081e0 ?	tandz	f0, f0
-0+200 <[^>]*> eea88100 ?	tane	f0, f0
-0+204 <[^>]*> eea88120 ?	tanep	f0, f0
-0+208 <[^>]*> eea88140 ?	tanem	f0, f0
-0+20c <[^>]*> eea88160 ?	tanez	f0, f0
-0+210 <[^>]*> eeb08100 ?	asns	f0, f0
-0+214 <[^>]*> eeb08120 ?	asnsp	f0, f0
-0+218 <[^>]*> eeb08140 ?	asnsm	f0, f0
-0+21c <[^>]*> eeb08160 ?	asnsz	f0, f0
-0+220 <[^>]*> eeb08180 ?	asnd	f0, f0
-0+224 <[^>]*> eeb081a0 ?	asndp	f0, f0
-0+228 <[^>]*> eeb081c0 ?	asndm	f0, f0
-0+22c <[^>]*> eeb081e0 ?	asndz	f0, f0
-0+230 <[^>]*> eeb88100 ?	asne	f0, f0
-0+234 <[^>]*> eeb88120 ?	asnep	f0, f0
-0+238 <[^>]*> eeb88140 ?	asnem	f0, f0
-0+23c <[^>]*> eeb88160 ?	asnez	f0, f0
-0+240 <[^>]*> eec08100 ?	acss	f0, f0
-0+244 <[^>]*> eec08120 ?	acssp	f0, f0
-0+248 <[^>]*> eec08140 ?	acssm	f0, f0
-0+24c <[^>]*> eec08160 ?	acssz	f0, f0
-0+250 <[^>]*> eec08180 ?	acsd	f0, f0
-0+254 <[^>]*> eec081a0 ?	acsdp	f0, f0
-0+258 <[^>]*> eec081c0 ?	acsdm	f0, f0
-0+25c <[^>]*> eec081e0 ?	acsdz	f0, f0
-0+260 <[^>]*> eec88100 ?	acse	f0, f0
-0+264 <[^>]*> eec88120 ?	acsep	f0, f0
-0+268 <[^>]*> eec88140 ?	acsem	f0, f0
-0+26c <[^>]*> eec88160 ?	acsez	f0, f0
-0+270 <[^>]*> eed08100 ?	atns	f0, f0
-0+274 <[^>]*> eed08120 ?	atnsp	f0, f0
-0+278 <[^>]*> eed08140 ?	atnsm	f0, f0
-0+27c <[^>]*> eed08160 ?	atnsz	f0, f0
-0+280 <[^>]*> eed08180 ?	atnd	f0, f0
-0+284 <[^>]*> eed081a0 ?	atndp	f0, f0
-0+288 <[^>]*> eed081c0 ?	atndm	f0, f0
-0+28c <[^>]*> eed081e0 ?	atndz	f0, f0
-0+290 <[^>]*> eed88100 ?	atne	f0, f0
-0+294 <[^>]*> eed88120 ?	atnep	f0, f0
-0+298 <[^>]*> eed88140 ?	atnem	f0, f0
-0+29c <[^>]*> eed88160 ?	atnez	f0, f0
-0+2a0 <[^>]*> eee08100 ?	urds	f0, f0
-0+2a4 <[^>]*> eee08120 ?	urdsp	f0, f0
-0+2a8 <[^>]*> eee08140 ?	urdsm	f0, f0
-0+2ac <[^>]*> eee08160 ?	urdsz	f0, f0
-0+2b0 <[^>]*> eee08180 ?	urdd	f0, f0
-0+2b4 <[^>]*> eee081a0 ?	urddp	f0, f0
-0+2b8 <[^>]*> eee081c0 ?	urddm	f0, f0
-0+2bc <[^>]*> eee081e0 ?	urddz	f0, f0
-0+2c0 <[^>]*> eee88100 ?	urde	f0, f0
-0+2c4 <[^>]*> eee88120 ?	urdep	f0, f0
-0+2c8 <[^>]*> eee88140 ?	urdem	f0, f0
-0+2cc <[^>]*> eee88160 ?	urdez	f0, f0
-0+2d0 <[^>]*> eef08100 ?	nrms	f0, f0
-0+2d4 <[^>]*> eef08120 ?	nrmsp	f0, f0
-0+2d8 <[^>]*> eef08140 ?	nrmsm	f0, f0
-0+2dc <[^>]*> eef08160 ?	nrmsz	f0, f0
-0+2e0 <[^>]*> eef08180 ?	nrmd	f0, f0
-0+2e4 <[^>]*> eef081a0 ?	nrmdp	f0, f0
-0+2e8 <[^>]*> eef081c0 ?	nrmdm	f0, f0
-0+2ec <[^>]*> eef081e0 ?	nrmdz	f0, f0
-0+2f0 <[^>]*> eef88100 ?	nrme	f0, f0
-0+2f4 <[^>]*> eef88120 ?	nrmep	f0, f0
-0+2f8 <[^>]*> eef88140 ?	nrmem	f0, f0
-0+2fc <[^>]*> eef88160 ?	nrmez	f0, f0
diff --git a/gas/testsuite/gas/arm/fpa-monadic.s b/gas/testsuite/gas/arm/fp=
a-monadic.s
deleted file mode 100644
index 2af03f4ea03..00000000000
--- a/gas/testsuite/gas/arm/fpa-monadic.s
+++ /dev/null
@@ -1,210 +0,0 @@
-	.text
-	.globl F
-F:
-	mvfs	f0, f0
-	mvfsp	f0, f0
-	mvfsm	f0, f0
-	mvfsz	f0, f0
-	mvfd	f0, f0
-	mvfdp	f0, f0
-	mvfdm	f0, f0
-	mvfdz	f0, f0
-	mvfe	f0, f0
-	mvfep	f0, f0
-	mvfem	f0, f0
-	mvfez	f0, f0
-
-	mnfs	f0, f0
-	mnfsp	f0, f0
-	mnfsm	f0, f0
-	mnfsz	f0, f0
-	mnfd	f0, f0
-	mnfdp	f0, f0
-	mnfdm	f0, f0
-	mnfdz	f0, f0
-	mnfe	f0, f0
-	mnfep	f0, f0
-	mnfem	f0, f0
-	mnfez	f0, f0
-
-	abss	f0, f0
-	abssp	f0, f0
-	abssm	f0, f0
-	abssz	f0, f0
-	absd	f0, f0
-	absdp	f0, f0
-	absdm	f0, f0
-	absdz	f0, f0
-	abse	f0, f0
-	absep	f0, f0
-	absem	f0, f0
-	absez	f0, f0
-
-	rnds	f0, f0
-	rndsp	f0, f0
-	rndsm	f0, f0
-	rndsz	f0, f0
-	rndd	f0, f0
-	rnddp	f0, f0
-	rnddm	f0, f0
-	rnddz	f0, f0
-	rnde	f0, f0
-	rndep	f0, f0
-	rndem	f0, f0
-	rndez	f0, f0
-
-	sqts	f0, f0
-	sqtsp	f0, f0
-	sqtsm	f0, f0
-	sqtsz	f0, f0
-	sqtd	f0, f0
-	sqtdp	f0, f0
-	sqtdm	f0, f0
-	sqtdz	f0, f0
-	sqte	f0, f0
-	sqtep	f0, f0
-	sqtem	f0, f0
-	sqtez	f0, f0
-
-	logs	f0, f0
-	logsp	f0, f0
-	logsm	f0, f0
-	logsz	f0, f0
-	logd	f0, f0
-	logdp	f0, f0
-	logdm	f0, f0
-	logdz	f0, f0
-	loge	f0, f0
-	logep	f0, f0
-	logem	f0, f0
-	logez	f0, f0
-
-	lgns	f0, f0
-	lgnsp	f0, f0
-	lgnsm	f0, f0
-	lgnsz	f0, f0
-	lgnd	f0, f0
-	lgndp	f0, f0
-	lgndm	f0, f0
-	lgndz	f0, f0
-	lgne	f0, f0
-	lgnep	f0, f0
-	lgnem	f0, f0
-	lgnez	f0, f0
-
-	exps	f0, f0
-	expsp	f0, f0
-	expsm	f0, f0
-	expsz	f0, f0
-	expd	f0, f0
-	expdp	f0, f0
-	expdm	f0, f0
-	expdz	f0, f0
-	expe	f0, f0
-	expep	f0, f0
-	expem	f0, f0
-	expdz	f0, f0
-
-	sins	f0, f0
-	sinsp	f0, f0
-	sinsm	f0, f0
-	sinsz	f0, f0
-	sind	f0, f0
-	sindp	f0, f0
-	sindm	f0, f0
-	sindz	f0, f0
-	sine	f0, f0
-	sinep	f0, f0
-	sinem	f0, f0
-	sinez	f0, f0
-
-	coss	f0, f0
-	cossp	f0, f0
-	cossm	f0, f0
-	cossz	f0, f0
-	cosd	f0, f0
-	cosdp	f0, f0
-	cosdm	f0, f0
-	cosdz	f0, f0
-	cose	f0, f0
-	cosep	f0, f0
-	cosem	f0, f0
-	cosez	f0, f0
-
-	tans	f0, f0
-	tansp	f0, f0
-	tansm	f0, f0
-	tansz	f0, f0
-	tand	f0, f0
-	tandp	f0, f0
-	tandm	f0, f0
-	tandz	f0, f0
-	tane	f0, f0
-	tanep	f0, f0
-	tanem	f0, f0
-	tanez	f0, f0
-
-	asns	f0, f0
-	asnsp	f0, f0
-	asnsm	f0, f0
-	asnsz	f0, f0
-	asnd	f0, f0
-	asndp	f0, f0
-	asndm	f0, f0
-	asndz	f0, f0
-	asne	f0, f0
-	asnep	f0, f0
-	asnem	f0, f0
-	asnez	f0, f0
-
-	acss	f0, f0
-	acssp	f0, f0
-	acssm	f0, f0
-	acssz	f0, f0
-	acsd	f0, f0
-	acsdp	f0, f0
-	acsdm	f0, f0
-	acsdz	f0, f0
-	acse	f0, f0
-	acsep	f0, f0
-	acsem	f0, f0
-	acsez	f0, f0
-
-	atns	f0, f0
-	atnsp	f0, f0
-	atnsm	f0, f0
-	atnsz	f0, f0
-	atnd	f0, f0
-	atndp	f0, f0
-	atndm	f0, f0
-	atndz	f0, f0
-	atne	f0, f0
-	atnep	f0, f0
-	atnem	f0, f0
-	atnez	f0, f0
-
-	urds	f0, f0
-	urdsp	f0, f0
-	urdsm	f0, f0
-	urdsz	f0, f0
-	urdd	f0, f0
-	urddp	f0, f0
-	urddm	f0, f0
-	urddz	f0, f0
-	urde	f0, f0
-	urdep	f0, f0
-	urdem	f0, f0
-	urdez	f0, f0
-
-	nrms	f0, f0
-	nrmsp	f0, f0
-	nrmsm	f0, f0
-	nrmsz	f0, f0
-	nrmd	f0, f0
-	nrmdp	f0, f0
-	nrmdm	f0, f0
-	nrmdz	f0, f0
-	nrme	f0, f0
-	nrmep	f0, f0
-	nrmem	f0, f0
-	nrmez	f0, f0
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l b/gas/tes=
tsuite/gas/arm/group-reloc-ldc-encoding-bad.l
index 191c5c659ea..3cf8638e617 100644
--- a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l
+++ b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l
@@ -191,198 +191,6 @@
 [^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
 [^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
 [^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
-[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words=
\)
 [^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
 [^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
 [^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s b/gas/tes=
tsuite/gas/arm/group-reloc-ldc-encoding-bad.s
index 1d402f9eee3..8608125058f 100644
--- a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s
+++ b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s
@@ -50,55 +50,55 @@
 	ldctest ldc2 stc2 0x808
 	ldctest ldc2l stc2l 0x808
=20
-@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP
=20
-	.fpu	fpa
=20
-	.macro	fpa_test load store cst
=20
-	\load	f0, [r0, #:pc_g0:(f + \cst)]
-	\load	f0, [r0, #:pc_g1:(f + \cst)]
-	\load	f0, [r0, #:pc_g2:(f + \cst)]
=20
-	\load	f0, [r0, #:sb_g0:(f + \cst)]
-	\load	f0, [r0, #:sb_g1:(f + \cst)]
-	\load	f0, [r0, #:sb_g2:(f + \cst)]
=20
-	\store	f0, [r0, #:pc_g0:(f + \cst)]
-	\store	f0, [r0, #:pc_g1:(f + \cst)]
-	\store	f0, [r0, #:pc_g2:(f + \cst)]
=20
-	\store	f0, [r0, #:sb_g0:(f + \cst)]
-	\store	f0, [r0, #:sb_g1:(f + \cst)]
-	\store	f0, [r0, #:sb_g2:(f + \cst)]
=20
-	\load	f0, [r0, #:pc_g0:(f - \cst)]
-	\load	f0, [r0, #:pc_g1:(f - \cst)]
-	\load	f0, [r0, #:pc_g2:(f - \cst)]
=20
-	\load	f0, [r0, #:sb_g0:(f - \cst)]
-	\load	f0, [r0, #:sb_g1:(f - \cst)]
-	\load	f0, [r0, #:sb_g2:(f - \cst)]
=20
-	\store	f0, [r0, #:pc_g0:(f - \cst)]
-	\store	f0, [r0, #:pc_g1:(f - \cst)]
-	\store	f0, [r0, #:pc_g2:(f - \cst)]
=20
-	\store	f0, [r0, #:sb_g0:(f - \cst)]
-	\store	f0, [r0, #:sb_g1:(f - \cst)]
-	\store	f0, [r0, #:sb_g2:(f - \cst)]
=20
-	.endm
=20
-	fpa_test ldfs stfs 0x1
-	fpa_test ldfd stfd 0x1
-	fpa_test ldfe stfe 0x1
-	fpa_test ldfp stfp 0x1
=20
-	fpa_test ldfs stfs 0x808
-	fpa_test ldfd stfd 0x808
-	fpa_test ldfe stfe 0x808
-	fpa_test ldfp stfp 0x808
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
=20
 @ FLDS/FSTS
=20
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l b/gas/test=
suite/gas/arm/group-reloc-ldc-parsing-bad.l
index 69526865312..94b9efb8313 100644
--- a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l
+++ b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l
@@ -79,86 +79,6 @@
 [^:]*:33: *Info: macro .*
 [^:]*:10: Error: unknown group relocation -- `stc2l 0,c0,\[r0,#:foo:\(sym\=
)\]'
 [^:]*:33: *Info: macro .*
-[^:]*:16: Error: this group relocation is not allowed on this instruction =
-- `ldfs f0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:37: *Info: macro .*
-[^:]*:17: Error: this group relocation is not allowed on this instruction =
-- `ldfs f0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:37: *Info: macro .*
-[^:]*:18: Error: this group relocation is not allowed on this instruction =
-- `ldfs f0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:37: *Info: macro .*
-[^:]*:19: Error: this group relocation is not allowed on this instruction =
-- `ldfs f0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:37: *Info: macro .*
-[^:]*:21: Error: unknown group relocation -- `ldfs f0,\[r0,#:foo:\(sym\)\]'
-[^:]*:37: *Info: macro .*
-[^:]*:16: Error: this group relocation is not allowed on this instruction =
-- `stfs f0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:38: *Info: macro .*
-[^:]*:17: Error: this group relocation is not allowed on this instruction =
-- `stfs f0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:38: *Info: macro .*
-[^:]*:18: Error: this group relocation is not allowed on this instruction =
-- `stfs f0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:38: *Info: macro .*
-[^:]*:19: Error: this group relocation is not allowed on this instruction =
-- `stfs f0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:38: *Info: macro .*
-[^:]*:21: Error: unknown group relocation -- `stfs f0,\[r0,#:foo:\(sym\)\]'
-[^:]*:38: *Info: macro .*
-[^:]*:16: Error: this group relocation is not allowed on this instruction =
-- `ldfd f0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:39: *Info: macro .*
-[^:]*:17: Error: this group relocation is not allowed on this instruction =
-- `ldfd f0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:39: *Info: macro .*
-[^:]*:18: Error: this group relocation is not allowed on this instruction =
-- `ldfd f0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:39: *Info: macro .*
-[^:]*:19: Error: this group relocation is not allowed on this instruction =
-- `ldfd f0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:39: *Info: macro .*
-[^:]*:21: Error: unknown group relocation -- `ldfd f0,\[r0,#:foo:\(sym\)\]'
-[^:]*:39: *Info: macro .*
-[^:]*:16: Error: this group relocation is not allowed on this instruction =
-- `stfd f0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:40: *Info: macro .*
-[^:]*:17: Error: this group relocation is not allowed on this instruction =
-- `stfd f0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:40: *Info: macro .*
-[^:]*:18: Error: this group relocation is not allowed on this instruction =
-- `stfd f0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:40: *Info: macro .*
-[^:]*:19: Error: this group relocation is not allowed on this instruction =
-- `stfd f0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:40: *Info: macro .*
-[^:]*:21: Error: unknown group relocation -- `stfd f0,\[r0,#:foo:\(sym\)\]'
-[^:]*:40: *Info: macro .*
-[^:]*:16: Error: this group relocation is not allowed on this instruction =
-- `ldfe f0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:41: *Info: macro .*
-[^:]*:17: Error: this group relocation is not allowed on this instruction =
-- `ldfe f0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:41: *Info: macro .*
-[^:]*:18: Error: this group relocation is not allowed on this instruction =
-- `ldfe f0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:41: *Info: macro .*
-[^:]*:19: Error: this group relocation is not allowed on this instruction =
-- `ldfe f0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:41: *Info: macro .*
-[^:]*:21: Error: unknown group relocation -- `ldfe f0,\[r0,#:foo:\(sym\)\]'
-[^:]*:41: *Info: macro .*
-[^:]*:16: Error: this group relocation is not allowed on this instruction =
-- `stfe f0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:42: *Info: macro .*
-[^:]*:17: Error: this group relocation is not allowed on this instruction =
-- `stfe f0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:42: *Info: macro .*
-[^:]*:18: Error: this group relocation is not allowed on this instruction =
-- `stfe f0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:42: *Info: macro .*
-[^:]*:19: Error: this group relocation is not allowed on this instruction =
-- `stfe f0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:42: *Info: macro .*
-[^:]*:21: Error: unknown group relocation -- `stfe f0,\[r0,#:foo:\(sym\)\]'
-[^:]*:42: *Info: macro .*
-[^:]*:16: Error: this group relocation is not allowed on this instruction =
-- `ldfp f0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:43: *Info: macro .*
-[^:]*:17: Error: this group relocation is not allowed on this instruction =
-- `ldfp f0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:43: *Info: macro .*
-[^:]*:18: Error: this group relocation is not allowed on this instruction =
-- `ldfp f0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:43: *Info: macro .*
-[^:]*:19: Error: this group relocation is not allowed on this instruction =
-- `ldfp f0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:43: *Info: macro .*
-[^:]*:21: Error: unknown group relocation -- `ldfp f0,\[r0,#:foo:\(sym\)\]'
-[^:]*:43: *Info: macro .*
-[^:]*:16: Error: this group relocation is not allowed on this instruction =
-- `stfp f0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:44: *Info: macro .*
-[^:]*:17: Error: this group relocation is not allowed on this instruction =
-- `stfp f0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:44: *Info: macro .*
-[^:]*:18: Error: this group relocation is not allowed on this instruction =
-- `stfp f0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:44: *Info: macro .*
-[^:]*:19: Error: this group relocation is not allowed on this instruction =
-- `stfp f0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:44: *Info: macro .*
-[^:]*:21: Error: unknown group relocation -- `stfp f0,\[r0,#:foo:\(sym\)\]'
-[^:]*:44: *Info: macro .*
 [^:]*:16: Error: this group relocation is not allowed on this instruction =
-- `flds s0,\[r0,#:pc_g0_nc:\(sym\)\]'
 [^:]*:48: *Info: macro .*
 [^:]*:17: Error: this group relocation is not allowed on this instruction =
-- `flds s0,\[r0,#:pc_g1_nc:\(sym\)\]'
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s b/gas/test=
suite/gas/arm/group-reloc-ldc-parsing-bad.s
index d10e363a8ed..80a651b4d8f 100644
--- a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s
+++ b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s
@@ -32,16 +32,16 @@
 	ldctest stc2 c0
 	ldctest stc2l c0
=20
-	.fpu 	fpa
-
-	ldctest2 ldfs f0
-	ldctest2 stfs f0
-	ldctest2 ldfd f0
-	ldctest2 stfd f0
-	ldctest2 ldfe f0
-	ldctest2 stfe f0
-	ldctest2 ldfp f0
-	ldctest2 stfp f0
+
+
+
+
+
+
+
+
+
+
=20
 	.fpu	vfp
=20
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc.d b/gas/testsuite/gas/ar=
m/group-reloc-ldc.d
index 870703d6a44..7c51c720b5c 100644
--- a/gas/testsuite/gas/arm/group-reloc-ldc.d
+++ b/gas/testsuite/gas/arm/group-reloc-ldc.d
@@ -197,339 +197,147 @@ Disassembly of section .text:
 			178: R_ARM_LDC_SB_G1	f
 0[0-9a-f]+ <[^>]+> fd400085 	stc2l	0, cr0, \[r0, #-532\].*
 			17c: R_ARM_LDC_SB_G2	f
-0[0-9a-f]+ <[^>]+> ed900185 	ldfs	f0, \[r0, #532\].*
-			180: R_ARM_LDC_PC_G0	f
-0[0-9a-f]+ <[^>]+> ed900185 	ldfs	f0, \[r0, #532\].*
-			184: R_ARM_LDC_PC_G1	f
-0[0-9a-f]+ <[^>]+> ed900185 	ldfs	f0, \[r0, #532\].*
-			188: R_ARM_LDC_PC_G2	f
-0[0-9a-f]+ <[^>]+> ed900185 	ldfs	f0, \[r0, #532\].*
-			18c: R_ARM_LDC_SB_G0	f
-0[0-9a-f]+ <[^>]+> ed900185 	ldfs	f0, \[r0, #532\].*
-			190: R_ARM_LDC_SB_G1	f
-0[0-9a-f]+ <[^>]+> ed900185 	ldfs	f0, \[r0, #532\].*
-			194: R_ARM_LDC_SB_G2	f
-0[0-9a-f]+ <[^>]+> ed800185 	stfs	f0, \[r0, #532\].*
-			198: R_ARM_LDC_PC_G0	f
-0[0-9a-f]+ <[^>]+> ed800185 	stfs	f0, \[r0, #532\].*
-			19c: R_ARM_LDC_PC_G1	f
-0[0-9a-f]+ <[^>]+> ed800185 	stfs	f0, \[r0, #532\].*
-			1a0: R_ARM_LDC_PC_G2	f
-0[0-9a-f]+ <[^>]+> ed800185 	stfs	f0, \[r0, #532\].*
-			1a4: R_ARM_LDC_SB_G0	f
-0[0-9a-f]+ <[^>]+> ed800185 	stfs	f0, \[r0, #532\].*
-			1a8: R_ARM_LDC_SB_G1	f
-0[0-9a-f]+ <[^>]+> ed800185 	stfs	f0, \[r0, #532\].*
-			1ac: R_ARM_LDC_SB_G2	f
-0[0-9a-f]+ <[^>]+> ed100185 	ldfs	f0, \[r0, #-532\].*
-			1b0: R_ARM_LDC_PC_G0	f
-0[0-9a-f]+ <[^>]+> ed100185 	ldfs	f0, \[r0, #-532\].*
-			1b4: R_ARM_LDC_PC_G1	f
-0[0-9a-f]+ <[^>]+> ed100185 	ldfs	f0, \[r0, #-532\].*
-			1b8: R_ARM_LDC_PC_G2	f
-0[0-9a-f]+ <[^>]+> ed100185 	ldfs	f0, \[r0, #-532\].*
-			1bc: R_ARM_LDC_SB_G0	f
-0[0-9a-f]+ <[^>]+> ed100185 	ldfs	f0, \[r0, #-532\].*
-			1c0: R_ARM_LDC_SB_G1	f
-0[0-9a-f]+ <[^>]+> ed100185 	ldfs	f0, \[r0, #-532\].*
-			1c4: R_ARM_LDC_SB_G2	f
-0[0-9a-f]+ <[^>]+> ed000185 	stfs	f0, \[r0, #-532\].*
-			1c8: R_ARM_LDC_PC_G0	f
-0[0-9a-f]+ <[^>]+> ed000185 	stfs	f0, \[r0, #-532\].*
-			1cc: R_ARM_LDC_PC_G1	f
-0[0-9a-f]+ <[^>]+> ed000185 	stfs	f0, \[r0, #-532\].*
-			1d0: R_ARM_LDC_PC_G2	f
-0[0-9a-f]+ <[^>]+> ed000185 	stfs	f0, \[r0, #-532\].*
-			1d4: R_ARM_LDC_SB_G0	f
-0[0-9a-f]+ <[^>]+> ed000185 	stfs	f0, \[r0, #-532\].*
-			1d8: R_ARM_LDC_SB_G1	f
-0[0-9a-f]+ <[^>]+> ed000185 	stfs	f0, \[r0, #-532\].*
-			1dc: R_ARM_LDC_SB_G2	f
-0[0-9a-f]+ <[^>]+> ed908185 	ldfd	f0, \[r0, #532\].*
-			1e0: R_ARM_LDC_PC_G0	f
-0[0-9a-f]+ <[^>]+> ed908185 	ldfd	f0, \[r0, #532\].*
-			1e4: R_ARM_LDC_PC_G1	f
-0[0-9a-f]+ <[^>]+> ed908185 	ldfd	f0, \[r0, #532\].*
-			1e8: R_ARM_LDC_PC_G2	f
-0[0-9a-f]+ <[^>]+> ed908185 	ldfd	f0, \[r0, #532\].*
-			1ec: R_ARM_LDC_SB_G0	f
-0[0-9a-f]+ <[^>]+> ed908185 	ldfd	f0, \[r0, #532\].*
-			1f0: R_ARM_LDC_SB_G1	f
-0[0-9a-f]+ <[^>]+> ed908185 	ldfd	f0, \[r0, #532\].*
-			1f4: R_ARM_LDC_SB_G2	f
-0[0-9a-f]+ <[^>]+> ed808185 	stfd	f0, \[r0, #532\].*
-			1f8: R_ARM_LDC_PC_G0	f
-0[0-9a-f]+ <[^>]+> ed808185 	stfd	f0, \[r0, #532\].*
-			1fc: R_ARM_LDC_PC_G1	f
-0[0-9a-f]+ <[^>]+> ed808185 	stfd	f0, \[r0, #532\].*
-			200: R_ARM_LDC_PC_G2	f
-0[0-9a-f]+ <[^>]+> ed808185 	stfd	f0, \[r0, #532\].*
-			204: R_ARM_LDC_SB_G0	f
-0[0-9a-f]+ <[^>]+> ed808185 	stfd	f0, \[r0, #532\].*
-			208: R_ARM_LDC_SB_G1	f
-0[0-9a-f]+ <[^>]+> ed808185 	stfd	f0, \[r0, #532\].*
-			20c: R_ARM_LDC_SB_G2	f
-0[0-9a-f]+ <[^>]+> ed108185 	ldfd	f0, \[r0, #-532\].*
-			210: R_ARM_LDC_PC_G0	f
-0[0-9a-f]+ <[^>]+> ed108185 	ldfd	f0, \[r0, #-532\].*
-			214: R_ARM_LDC_PC_G1	f
-0[0-9a-f]+ <[^>]+> ed108185 	ldfd	f0, \[r0, #-532\].*
-			218: R_ARM_LDC_PC_G2	f
-0[0-9a-f]+ <[^>]+> ed108185 	ldfd	f0, \[r0, #-532\].*
-			21c: R_ARM_LDC_SB_G0	f
-0[0-9a-f]+ <[^>]+> ed108185 	ldfd	f0, \[r0, #-532\].*
-			220: R_ARM_LDC_SB_G1	f
-0[0-9a-f]+ <[^>]+> ed108185 	ldfd	f0, \[r0, #-532\].*
-			224: R_ARM_LDC_SB_G2	f
-0[0-9a-f]+ <[^>]+> ed008185 	stfd	f0, \[r0, #-532\].*
-			228: R_ARM_LDC_PC_G0	f
-0[0-9a-f]+ <[^>]+> ed008185 	stfd	f0, \[r0, #-532\].*
-			22c: R_ARM_LDC_PC_G1	f
-0[0-9a-f]+ <[^>]+> ed008185 	stfd	f0, \[r0, #-532\].*
-			230: R_ARM_LDC_PC_G2	f
-0[0-9a-f]+ <[^>]+> ed008185 	stfd	f0, \[r0, #-532\].*
-			234: R_ARM_LDC_SB_G0	f
-0[0-9a-f]+ <[^>]+> ed008185 	stfd	f0, \[r0, #-532\].*
-			238: R_ARM_LDC_SB_G1	f
-0[0-9a-f]+ <[^>]+> ed008185 	stfd	f0, \[r0, #-532\].*
-			23c: R_ARM_LDC_SB_G2	f
-0[0-9a-f]+ <[^>]+> edd00185 	ldfe	f0, \[r0, #532\].*
-			240: R_ARM_LDC_PC_G0	f
-0[0-9a-f]+ <[^>]+> edd00185 	ldfe	f0, \[r0, #532\].*
-			244: R_ARM_LDC_PC_G1	f
-0[0-9a-f]+ <[^>]+> edd00185 	ldfe	f0, \[r0, #532\].*
-			248: R_ARM_LDC_PC_G2	f
-0[0-9a-f]+ <[^>]+> edd00185 	ldfe	f0, \[r0, #532\].*
-			24c: R_ARM_LDC_SB_G0	f
-0[0-9a-f]+ <[^>]+> edd00185 	ldfe	f0, \[r0, #532\].*
-			250: R_ARM_LDC_SB_G1	f
-0[0-9a-f]+ <[^>]+> edd00185 	ldfe	f0, \[r0, #532\].*
-			254: R_ARM_LDC_SB_G2	f
-0[0-9a-f]+ <[^>]+> edc00185 	stfe	f0, \[r0, #532\].*
-			258: R_ARM_LDC_PC_G0	f
-0[0-9a-f]+ <[^>]+> edc00185 	stfe	f0, \[r0, #532\].*
-			25c: R_ARM_LDC_PC_G1	f
-0[0-9a-f]+ <[^>]+> edc00185 	stfe	f0, \[r0, #532\].*
-			260: R_ARM_LDC_PC_G2	f
-0[0-9a-f]+ <[^>]+> edc00185 	stfe	f0, \[r0, #532\].*
-			264: R_ARM_LDC_SB_G0	f
-0[0-9a-f]+ <[^>]+> edc00185 	stfe	f0, \[r0, #532\].*
-			268: R_ARM_LDC_SB_G1	f
-0[0-9a-f]+ <[^>]+> edc00185 	stfe	f0, \[r0, #532\].*
-			26c: R_ARM_LDC_SB_G2	f
-0[0-9a-f]+ <[^>]+> ed500185 	ldfe	f0, \[r0, #-532\].*
-			270: R_ARM_LDC_PC_G0	f
-0[0-9a-f]+ <[^>]+> ed500185 	ldfe	f0, \[r0, #-532\].*
-			274: R_ARM_LDC_PC_G1	f
-0[0-9a-f]+ <[^>]+> ed500185 	ldfe	f0, \[r0, #-532\].*
-			278: R_ARM_LDC_PC_G2	f
-0[0-9a-f]+ <[^>]+> ed500185 	ldfe	f0, \[r0, #-532\].*
-			27c: R_ARM_LDC_SB_G0	f
-0[0-9a-f]+ <[^>]+> ed500185 	ldfe	f0, \[r0, #-532\].*
-			280: R_ARM_LDC_SB_G1	f
-0[0-9a-f]+ <[^>]+> ed500185 	ldfe	f0, \[r0, #-532\].*
-			284: R_ARM_LDC_SB_G2	f
-0[0-9a-f]+ <[^>]+> ed400185 	stfe	f0, \[r0, #-532\].*
-			288: R_ARM_LDC_PC_G0	f
-0[0-9a-f]+ <[^>]+> ed400185 	stfe	f0, \[r0, #-532\].*
-			28c: R_ARM_LDC_PC_G1	f
-0[0-9a-f]+ <[^>]+> ed400185 	stfe	f0, \[r0, #-532\].*
-			290: R_ARM_LDC_PC_G2	f
-0[0-9a-f]+ <[^>]+> ed400185 	stfe	f0, \[r0, #-532\].*
-			294: R_ARM_LDC_SB_G0	f
-0[0-9a-f]+ <[^>]+> ed400185 	stfe	f0, \[r0, #-532\].*
-			298: R_ARM_LDC_SB_G1	f
-0[0-9a-f]+ <[^>]+> ed400185 	stfe	f0, \[r0, #-532\].*
-			29c: R_ARM_LDC_SB_G2	f
-0[0-9a-f]+ <[^>]+> edd08185 	ldfp	f0, \[r0, #532\].*
-			2a0: R_ARM_LDC_PC_G0	f
-0[0-9a-f]+ <[^>]+> edd08185 	ldfp	f0, \[r0, #532\].*
-			2a4: R_ARM_LDC_PC_G1	f
-0[0-9a-f]+ <[^>]+> edd08185 	ldfp	f0, \[r0, #532\].*
-			2a8: R_ARM_LDC_PC_G2	f
-0[0-9a-f]+ <[^>]+> edd08185 	ldfp	f0, \[r0, #532\].*
-			2ac: R_ARM_LDC_SB_G0	f
-0[0-9a-f]+ <[^>]+> edd08185 	ldfp	f0, \[r0, #532\].*
-			2b0: R_ARM_LDC_SB_G1	f
-0[0-9a-f]+ <[^>]+> edd08185 	ldfp	f0, \[r0, #532\].*
-			2b4: R_ARM_LDC_SB_G2	f
-0[0-9a-f]+ <[^>]+> edc08185 	stfp	f0, \[r0, #532\].*
-			2b8: R_ARM_LDC_PC_G0	f
-0[0-9a-f]+ <[^>]+> edc08185 	stfp	f0, \[r0, #532\].*
-			2bc: R_ARM_LDC_PC_G1	f
-0[0-9a-f]+ <[^>]+> edc08185 	stfp	f0, \[r0, #532\].*
-			2c0: R_ARM_LDC_PC_G2	f
-0[0-9a-f]+ <[^>]+> edc08185 	stfp	f0, \[r0, #532\].*
-			2c4: R_ARM_LDC_SB_G0	f
-0[0-9a-f]+ <[^>]+> edc08185 	stfp	f0, \[r0, #532\].*
-			2c8: R_ARM_LDC_SB_G1	f
-0[0-9a-f]+ <[^>]+> edc08185 	stfp	f0, \[r0, #532\].*
-			2cc: R_ARM_LDC_SB_G2	f
-0[0-9a-f]+ <[^>]+> ed508185 	ldfp	f0, \[r0, #-532\].*
-			2d0: R_ARM_LDC_PC_G0	f
-0[0-9a-f]+ <[^>]+> ed508185 	ldfp	f0, \[r0, #-532\].*
-			2d4: R_ARM_LDC_PC_G1	f
-0[0-9a-f]+ <[^>]+> ed508185 	ldfp	f0, \[r0, #-532\].*
-			2d8: R_ARM_LDC_PC_G2	f
-0[0-9a-f]+ <[^>]+> ed508185 	ldfp	f0, \[r0, #-532\].*
-			2dc: R_ARM_LDC_SB_G0	f
-0[0-9a-f]+ <[^>]+> ed508185 	ldfp	f0, \[r0, #-532\].*
-			2e0: R_ARM_LDC_SB_G1	f
-0[0-9a-f]+ <[^>]+> ed508185 	ldfp	f0, \[r0, #-532\].*
-			2e4: R_ARM_LDC_SB_G2	f
-0[0-9a-f]+ <[^>]+> ed408185 	stfp	f0, \[r0, #-532\].*
-			2e8: R_ARM_LDC_PC_G0	f
-0[0-9a-f]+ <[^>]+> ed408185 	stfp	f0, \[r0, #-532\].*
-			2ec: R_ARM_LDC_PC_G1	f
-0[0-9a-f]+ <[^>]+> ed408185 	stfp	f0, \[r0, #-532\].*
-			2f0: R_ARM_LDC_PC_G2	f
-0[0-9a-f]+ <[^>]+> ed408185 	stfp	f0, \[r0, #-532\].*
-			2f4: R_ARM_LDC_SB_G0	f
-0[0-9a-f]+ <[^>]+> ed408185 	stfp	f0, \[r0, #-532\].*
-			2f8: R_ARM_LDC_SB_G1	f
-0[0-9a-f]+ <[^>]+> ed408185 	stfp	f0, \[r0, #-532\].*
-			2fc: R_ARM_LDC_SB_G2	f
 0[0-9a-f]+ <[^>]+> ed900a85 	(vldr|flds)	s0, \[r0, #532\].*
-			300: R_ARM_LDC_PC_G0	f
+			180: R_ARM_LDC_PC_G0	f
 0[0-9a-f]+ <[^>]+> ed900a85 	(vldr|flds)	s0, \[r0, #532\].*
-			304: R_ARM_LDC_PC_G1	f
+			184: R_ARM_LDC_PC_G1	f
 0[0-9a-f]+ <[^>]+> ed900a85 	(vldr|flds)	s0, \[r0, #532\].*
-			308: R_ARM_LDC_PC_G2	f
+			188: R_ARM_LDC_PC_G2	f
 0[0-9a-f]+ <[^>]+> ed900a85 	(vldr|flds)	s0, \[r0, #532\].*
-			30c: R_ARM_LDC_SB_G0	f
+			18c: R_ARM_LDC_SB_G0	f
 0[0-9a-f]+ <[^>]+> ed900a85 	(vldr|flds)	s0, \[r0, #532\].*
-			310: R_ARM_LDC_SB_G1	f
+			190: R_ARM_LDC_SB_G1	f
 0[0-9a-f]+ <[^>]+> ed900a85 	(vldr|flds)	s0, \[r0, #532\].*
-			314: R_ARM_LDC_SB_G2	f
+			194: R_ARM_LDC_SB_G2	f
 0[0-9a-f]+ <[^>]+> ed800a85 	(vstr|fsts)	s0, \[r0, #532\].*
-			318: R_ARM_LDC_PC_G0	f
+			198: R_ARM_LDC_PC_G0	f
 0[0-9a-f]+ <[^>]+> ed800a85 	(vstr|fsts)	s0, \[r0, #532\].*
-			31c: R_ARM_LDC_PC_G1	f
+			19c: R_ARM_LDC_PC_G1	f
 0[0-9a-f]+ <[^>]+> ed800a85 	(vstr|fsts)	s0, \[r0, #532\].*
-			320: R_ARM_LDC_PC_G2	f
+			1a0: R_ARM_LDC_PC_G2	f
 0[0-9a-f]+ <[^>]+> ed800a85 	(vstr|fsts)	s0, \[r0, #532\].*
-			324: R_ARM_LDC_SB_G0	f
+			1a4: R_ARM_LDC_SB_G0	f
 0[0-9a-f]+ <[^>]+> ed800a85 	(vstr|fsts)	s0, \[r0, #532\].*
-			328: R_ARM_LDC_SB_G1	f
+			1a8: R_ARM_LDC_SB_G1	f
 0[0-9a-f]+ <[^>]+> ed800a85 	(vstr|fsts)	s0, \[r0, #532\].*
-			32c: R_ARM_LDC_SB_G2	f
+			1ac: R_ARM_LDC_SB_G2	f
 0[0-9a-f]+ <[^>]+> ed100a85 	(vldr|flds)	s0, \[r0, #-532\].*
-			330: R_ARM_LDC_PC_G0	f
+			1b0: R_ARM_LDC_PC_G0	f
 0[0-9a-f]+ <[^>]+> ed100a85 	(vldr|flds)	s0, \[r0, #-532\].*
-			334: R_ARM_LDC_PC_G1	f
+			1b4: R_ARM_LDC_PC_G1	f
 0[0-9a-f]+ <[^>]+> ed100a85 	(vldr|flds)	s0, \[r0, #-532\].*
-			338: R_ARM_LDC_PC_G2	f
+			1b8: R_ARM_LDC_PC_G2	f
 0[0-9a-f]+ <[^>]+> ed100a85 	(vldr|flds)	s0, \[r0, #-532\].*
-			33c: R_ARM_LDC_SB_G0	f
+			1bc: R_ARM_LDC_SB_G0	f
 0[0-9a-f]+ <[^>]+> ed100a85 	(vldr|flds)	s0, \[r0, #-532\].*
-			340: R_ARM_LDC_SB_G1	f
+			1c0: R_ARM_LDC_SB_G1	f
 0[0-9a-f]+ <[^>]+> ed100a85 	(vldr|flds)	s0, \[r0, #-532\].*
-			344: R_ARM_LDC_SB_G2	f
+			1c4: R_ARM_LDC_SB_G2	f
 0[0-9a-f]+ <[^>]+> ed000a85 	(vstr|fsts)	s0, \[r0, #-532\].*
-			348: R_ARM_LDC_PC_G0	f
+			1c8: R_ARM_LDC_PC_G0	f
 0[0-9a-f]+ <[^>]+> ed000a85 	(vstr|fsts)	s0, \[r0, #-532\].*
-			34c: R_ARM_LDC_PC_G1	f
+			1cc: R_ARM_LDC_PC_G1	f
 0[0-9a-f]+ <[^>]+> ed000a85 	(vstr|fsts)	s0, \[r0, #-532\].*
-			350: R_ARM_LDC_PC_G2	f
+			1d0: R_ARM_LDC_PC_G2	f
 0[0-9a-f]+ <[^>]+> ed000a85 	(vstr|fsts)	s0, \[r0, #-532\].*
-			354: R_ARM_LDC_SB_G0	f
+			1d4: R_ARM_LDC_SB_G0	f
 0[0-9a-f]+ <[^>]+> ed000a85 	(vstr|fsts)	s0, \[r0, #-532\].*
-			358: R_ARM_LDC_SB_G1	f
+			1d8: R_ARM_LDC_SB_G1	f
 0[0-9a-f]+ <[^>]+> ed000a85 	(vstr|fsts)	s0, \[r0, #-532\].*
-			35c: R_ARM_LDC_SB_G2	f
+			1dc: R_ARM_LDC_SB_G2	f
 0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\].*
-			360: R_ARM_LDC_PC_G0	f
+			1e0: R_ARM_LDC_PC_G0	f
 0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\].*
-			364: R_ARM_LDC_PC_G1	f
+			1e4: R_ARM_LDC_PC_G1	f
 0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\].*
-			368: R_ARM_LDC_PC_G2	f
+			1e8: R_ARM_LDC_PC_G2	f
 0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\].*
-			36c: R_ARM_LDC_SB_G0	f
+			1ec: R_ARM_LDC_SB_G0	f
 0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\].*
-			370: R_ARM_LDC_SB_G1	f
+			1f0: R_ARM_LDC_SB_G1	f
 0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\].*
-			374: R_ARM_LDC_SB_G2	f
+			1f4: R_ARM_LDC_SB_G2	f
 0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\].*
-			378: R_ARM_LDC_PC_G0	f
+			1f8: R_ARM_LDC_PC_G0	f
 0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\].*
-			37c: R_ARM_LDC_PC_G1	f
+			1fc: R_ARM_LDC_PC_G1	f
 0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\].*
-			380: R_ARM_LDC_PC_G2	f
+			200: R_ARM_LDC_PC_G2	f
 0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\].*
-			384: R_ARM_LDC_SB_G0	f
+			204: R_ARM_LDC_SB_G0	f
 0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\].*
-			388: R_ARM_LDC_SB_G1	f
+			208: R_ARM_LDC_SB_G1	f
 0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\].*
-			38c: R_ARM_LDC_SB_G2	f
+			20c: R_ARM_LDC_SB_G2	f
 0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\].*
-			390: R_ARM_LDC_PC_G0	f
+			210: R_ARM_LDC_PC_G0	f
 0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\].*
-			394: R_ARM_LDC_PC_G1	f
+			214: R_ARM_LDC_PC_G1	f
 0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\].*
-			398: R_ARM_LDC_PC_G2	f
+			218: R_ARM_LDC_PC_G2	f
 0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\].*
-			39c: R_ARM_LDC_SB_G0	f
+			21c: R_ARM_LDC_SB_G0	f
 0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\].*
-			3a0: R_ARM_LDC_SB_G1	f
+			220: R_ARM_LDC_SB_G1	f
 0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\].*
-			3a4: R_ARM_LDC_SB_G2	f
+			224: R_ARM_LDC_SB_G2	f
 0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\].*
-			3a8: R_ARM_LDC_PC_G0	f
+			228: R_ARM_LDC_PC_G0	f
 0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\].*
-			3ac: R_ARM_LDC_PC_G1	f
+			22c: R_ARM_LDC_PC_G1	f
 0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\].*
-			3b0: R_ARM_LDC_PC_G2	f
+			230: R_ARM_LDC_PC_G2	f
 0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\].*
-			3b4: R_ARM_LDC_SB_G0	f
+			234: R_ARM_LDC_SB_G0	f
 0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\].*
-			3b8: R_ARM_LDC_SB_G1	f
+			238: R_ARM_LDC_SB_G1	f
 0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\].*
-			3bc: R_ARM_LDC_SB_G2	f
+			23c: R_ARM_LDC_SB_G2	f
 0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\].*
-			3c0: R_ARM_LDC_PC_G0	f
+			240: R_ARM_LDC_PC_G0	f
 0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\].*
-			3c4: R_ARM_LDC_PC_G1	f
+			244: R_ARM_LDC_PC_G1	f
 0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\].*
-			3c8: R_ARM_LDC_PC_G2	f
+			248: R_ARM_LDC_PC_G2	f
 0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\].*
-			3cc: R_ARM_LDC_SB_G0	f
+			24c: R_ARM_LDC_SB_G0	f
 0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\].*
-			3d0: R_ARM_LDC_SB_G1	f
+			250: R_ARM_LDC_SB_G1	f
 0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\].*
-			3d4: R_ARM_LDC_SB_G2	f
+			254: R_ARM_LDC_SB_G2	f
 0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\].*
-			3d8: R_ARM_LDC_PC_G0	f
+			258: R_ARM_LDC_PC_G0	f
 0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\].*
-			3dc: R_ARM_LDC_PC_G1	f
+			25c: R_ARM_LDC_PC_G1	f
 0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\].*
-			3e0: R_ARM_LDC_PC_G2	f
+			260: R_ARM_LDC_PC_G2	f
 0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\].*
-			3e4: R_ARM_LDC_SB_G0	f
+			264: R_ARM_LDC_SB_G0	f
 0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\].*
-			3e8: R_ARM_LDC_SB_G1	f
+			268: R_ARM_LDC_SB_G1	f
 0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\].*
-			3ec: R_ARM_LDC_SB_G2	f
+			26c: R_ARM_LDC_SB_G2	f
 0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\].*
-			3f0: R_ARM_LDC_PC_G0	f
+			270: R_ARM_LDC_PC_G0	f
 0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\].*
-			3f4: R_ARM_LDC_PC_G1	f
+			274: R_ARM_LDC_PC_G1	f
 0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\].*
-			3f8: R_ARM_LDC_PC_G2	f
+			278: R_ARM_LDC_PC_G2	f
 0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\].*
-			3fc: R_ARM_LDC_SB_G0	f
+			27c: R_ARM_LDC_SB_G0	f
 0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\].*
-			400: R_ARM_LDC_SB_G1	f
+			280: R_ARM_LDC_SB_G1	f
 0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\].*
-			404: R_ARM_LDC_SB_G2	f
+			284: R_ARM_LDC_SB_G2	f
 0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\].*
-			408: R_ARM_LDC_PC_G0	f
+			288: R_ARM_LDC_PC_G0	f
 0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\].*
-			40c: R_ARM_LDC_PC_G1	f
+			28c: R_ARM_LDC_PC_G1	f
 0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\].*
-			410: R_ARM_LDC_PC_G2	f
+			290: R_ARM_LDC_PC_G2	f
 0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\].*
-			414: R_ARM_LDC_SB_G0	f
+			294: R_ARM_LDC_SB_G0	f
 0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\].*
-			418: R_ARM_LDC_SB_G1	f
+			298: R_ARM_LDC_SB_G1	f
 0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\].*
-			41c: R_ARM_LDC_SB_G2	f
+			29c: R_ARM_LDC_SB_G2	f
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc.s b/gas/testsuite/gas/ar=
m/group-reloc-ldc.s
index f17fa89551b..fdf26f16395 100644
--- a/gas/testsuite/gas/arm/group-reloc-ldc.s
+++ b/gas/testsuite/gas/arm/group-reloc-ldc.s
@@ -45,51 +45,6 @@
 	ldctest ldc2 stc2
 	ldctest ldc2l stc2l
=20
-@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP
-
-	.fpu	fpa
-
-	.macro	fpa_test load store
-
-	\load	f0, [r0, #:pc_g0:(f + 0x214)]
-	\load	f0, [r0, #:pc_g1:(f + 0x214)]
-	\load	f0, [r0, #:pc_g2:(f + 0x214)]
-
-	\load	f0, [r0, #:sb_g0:(f + 0x214)]
-	\load	f0, [r0, #:sb_g1:(f + 0x214)]
-	\load	f0, [r0, #:sb_g2:(f + 0x214)]
-
-	\store	f0, [r0, #:pc_g0:(f + 0x214)]
-	\store	f0, [r0, #:pc_g1:(f + 0x214)]
-	\store	f0, [r0, #:pc_g2:(f + 0x214)]
-
-	\store	f0, [r0, #:sb_g0:(f + 0x214)]
-	\store	f0, [r0, #:sb_g1:(f + 0x214)]
-	\store	f0, [r0, #:sb_g2:(f + 0x214)]
-
-	\load	f0, [r0, #:pc_g0:(f - 0x214)]
-	\load	f0, [r0, #:pc_g1:(f - 0x214)]
-	\load	f0, [r0, #:pc_g2:(f - 0x214)]
-
-	\load	f0, [r0, #:sb_g0:(f - 0x214)]
-	\load	f0, [r0, #:sb_g1:(f - 0x214)]
-	\load	f0, [r0, #:sb_g2:(f - 0x214)]
-
-	\store	f0, [r0, #:pc_g0:(f - 0x214)]
-	\store	f0, [r0, #:pc_g1:(f - 0x214)]
-	\store	f0, [r0, #:pc_g2:(f - 0x214)]
-
-	\store	f0, [r0, #:sb_g0:(f - 0x214)]
-	\store	f0, [r0, #:sb_g1:(f - 0x214)]
-	\store	f0, [r0, #:sb_g2:(f - 0x214)]
-
-	.endm
-
-	fpa_test ldfs stfs
-	fpa_test ldfd stfd
-	fpa_test ldfe stfe
-	fpa_test ldfp stfp
-
 @ FLDS/FSTS
=20
 	.fpu	vfp
diff --git a/gas/testsuite/gas/arm/le-fpconst.d b/gas/testsuite/gas/arm/le-=
fpconst.d
deleted file mode 100644
index 846da89f029..00000000000
--- a/gas/testsuite/gas/arm/le-fpconst.d
+++ /dev/null
@@ -1,11 +0,0 @@
-#objdump: -s --section=3D.text
-#as: -EL
-#name: arm little-endian fpconst
-# Not all arm targets are bi-endian, so only run this test on ones
-# we know that are.  FIXME We should probably also key off armeb/armel.
-#target: *-*-pe
-
-.*: +file format .*arm.*
-
-Contents of section .text:
- 0000 cdcc8c3f 00000000 9999f13f 9a999999 .*
diff --git a/gas/testsuite/gas/arm/le-fpconst.s b/gas/testsuite/gas/arm/le-=
fpconst.s
deleted file mode 100644
index 8a3c3d70145..00000000000
--- a/gas/testsuite/gas/arm/le-fpconst.s
+++ /dev/null
@@ -1,8 +0,0 @@
-# Test fp constants.
-# These need ARM specific support because 8 byte fp constants in little
-# endian mode are represented abnormally.
-=09
-	.text
-	.float 1.1
-	.float 0
-	.double 1.1

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 02/11] arm: rename FPU_ARCH_VFP to FPU_ARCH_SOFTVFP
  2024-06-03 11:49 [PATCH 00/11] arm: Remove FPA support from gas/binutils Richard Earnshaw
  2024-06-03 11:49 ` [PATCH 01/11] arm: remove FPA related tests Richard Earnshaw
@ 2024-06-03 11:49 ` Richard Earnshaw
  2024-06-03 11:49 ` [PATCH 03/11] arm: default to softvfp on armv6 or later cores Richard Earnshaw
                   ` (8 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Richard Earnshaw @ 2024-06-03 11:49 UTC (permalink / raw)
  To: binutils; +Cc: nickc, Richard Earnshaw

[-- Attachment #1: Type: text/plain, Size: 555 bytes --]


FPU_ARCH_VFP has always meant VFP floating-point format (natural FP
word order) but without any VFP instructions.  But the name
FPU_ARCH_VFP is potentially confusing.  This patch just changes the
name to make the meaning clearer.
---
 gas/config/tc-arm.c          | 146 ++++++++++++++++++++++-------------
 gas/config/te-armeabi.h      |   2 +-
 gas/config/te-armfbsdvfp.h   |   2 +-
 gas/config/te-armlinuxeabi.h |   2 +-
 gas/config/te-nacl.h         |   2 +-
 include/opcode/arm.h         |   2 +-
 6 files changed, 97 insertions(+), 59 deletions(-)


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0002-arm-rename-FPU_ARCH_VFP-to-FPU_ARCH_SOFTVFP.patch --]
[-- Type: text/x-patch; name="0002-arm-rename-FPU_ARCH_VFP-to-FPU_ARCH_SOFTVFP.patch", Size: 11331 bytes --]

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 41bcfb8dee2..12e8f7cfc84 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -121,13 +121,13 @@ static bool out_of_range_p (offsetT value, offsetT bits)
 #  define FPU_DEFAULT FPU_ARCH_FPA
 # elif defined (TE_NetBSD)
 #  ifdef OBJ_ELF
-#   define FPU_DEFAULT FPU_ARCH_VFP	/* Soft-float, but VFP order.  */
+#   define FPU_DEFAULT FPU_ARCH_SOFTVFP	/* Soft-float, but VFP order.  */
 #  else
     /* Legacy a.out format.  */
 #   define FPU_DEFAULT FPU_ARCH_FPA	/* Soft-float, but FPA order.  */
 #  endif
 # elif defined (TE_VXWORKS)
-#  define FPU_DEFAULT FPU_ARCH_VFP	/* Soft-float, VFP order.  */
+#  define FPU_DEFAULT FPU_ARCH_SOFTVFP	/* Soft-float, VFP order.  */
 # else
    /* For backwards compatibility, default to FPA.  */
 #  define FPU_DEFAULT FPU_ARCH_FPA
@@ -31966,65 +31966,103 @@ static const struct arm_arch_option_table arm_archs[] =
   ARM_ARCH_OPT ("armv4xm",	  ARM_ARCH_V4xM,	FPU_ARCH_FPA),
   ARM_ARCH_OPT ("armv4t",	  ARM_ARCH_V4T,		FPU_ARCH_FPA),
   ARM_ARCH_OPT ("armv4txm",	  ARM_ARCH_V4TxM,	FPU_ARCH_FPA),
-  ARM_ARCH_OPT ("armv5",	  ARM_ARCH_V5,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv5t",	  ARM_ARCH_V5T,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv5txm",	  ARM_ARCH_V5TxM,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT2 ("armv5te",	  ARM_ARCH_V5TE,	FPU_ARCH_VFP,	armv5te),
-  ARM_ARCH_OPT2 ("armv5texp",	  ARM_ARCH_V5TExP,	FPU_ARCH_VFP, armv5te),
-  ARM_ARCH_OPT2 ("armv5tej",	  ARM_ARCH_V5TEJ,	FPU_ARCH_VFP,	armv5te),
-  ARM_ARCH_OPT2 ("armv6",	  ARM_ARCH_V6,		FPU_ARCH_VFP,	armv5te),
-  ARM_ARCH_OPT2 ("armv6j",	  ARM_ARCH_V6,		FPU_ARCH_VFP,	armv5te),
-  ARM_ARCH_OPT2 ("armv6k",	  ARM_ARCH_V6K,		FPU_ARCH_VFP,	armv5te),
-  ARM_ARCH_OPT2 ("armv6z",	  ARM_ARCH_V6Z,		FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT ("armv5",	  ARM_ARCH_V5,		FPU_ARCH_SOFTVFP),
+  ARM_ARCH_OPT ("armv5t",	  ARM_ARCH_V5T,		FPU_ARCH_SOFTVFP),
+  ARM_ARCH_OPT ("armv5txm",	  ARM_ARCH_V5TxM,	FPU_ARCH_SOFTVFP),
+  ARM_ARCH_OPT2 ("armv5te",	  ARM_ARCH_V5TE,	FPU_ARCH_SOFTVFP,
+		 armv5te),
+  ARM_ARCH_OPT2 ("armv5texp",	  ARM_ARCH_V5TExP,	FPU_ARCH_SOFTVFP,
+		 armv5te),
+  ARM_ARCH_OPT2 ("armv5tej",	  ARM_ARCH_V5TEJ,	FPU_ARCH_SOFTVFP,
+		 armv5te),
+  ARM_ARCH_OPT2 ("armv6",	  ARM_ARCH_V6,		FPU_ARCH_SOFTVFP,
+		 armv5te),
+  ARM_ARCH_OPT2 ("armv6j",	  ARM_ARCH_V6,		FPU_ARCH_SOFTVFP,
+		 armv5te),
+  ARM_ARCH_OPT2 ("armv6k",	  ARM_ARCH_V6K,		FPU_ARCH_SOFTVFP,
+		 armv5te),
+  ARM_ARCH_OPT2 ("armv6z",	  ARM_ARCH_V6Z,		FPU_ARCH_SOFTVFP,
+		 armv5te),
   /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
      kept to preserve existing behaviour.  */
-  ARM_ARCH_OPT2 ("armv6kz",	  ARM_ARCH_V6KZ,	FPU_ARCH_VFP,	armv5te),
-  ARM_ARCH_OPT2 ("armv6zk",	  ARM_ARCH_V6KZ,	FPU_ARCH_VFP,	armv5te),
-  ARM_ARCH_OPT2 ("armv6t2",	  ARM_ARCH_V6T2,	FPU_ARCH_VFP,	armv5te),
-  ARM_ARCH_OPT2 ("armv6kt2",	  ARM_ARCH_V6KT2,	FPU_ARCH_VFP,	armv5te),
-  ARM_ARCH_OPT2 ("armv6zt2",	  ARM_ARCH_V6ZT2,	FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6kz",	  ARM_ARCH_V6KZ,	FPU_ARCH_SOFTVFP,
+		 armv5te),
+  ARM_ARCH_OPT2 ("armv6zk",	  ARM_ARCH_V6KZ,	FPU_ARCH_SOFTVFP,
+		 armv5te),
+  ARM_ARCH_OPT2 ("armv6t2",	  ARM_ARCH_V6T2,	FPU_ARCH_SOFTVFP,
+		 armv5te),
+  ARM_ARCH_OPT2 ("armv6kt2",	  ARM_ARCH_V6KT2,	FPU_ARCH_SOFTVFP,
+		 armv5te),
+  ARM_ARCH_OPT2 ("armv6zt2",	  ARM_ARCH_V6ZT2,	FPU_ARCH_SOFTVFP,
+		 armv5te),
   /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
      kept to preserve existing behaviour.  */
-  ARM_ARCH_OPT2 ("armv6kzt2",	  ARM_ARCH_V6KZT2,	FPU_ARCH_VFP,	armv5te),
-  ARM_ARCH_OPT2 ("armv6zkt2",	  ARM_ARCH_V6KZT2,	FPU_ARCH_VFP,	armv5te),
-  ARM_ARCH_OPT ("armv6-m",	  ARM_ARCH_V6M,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6s-m",	  ARM_ARCH_V6SM,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT2 ("armv7",	  ARM_ARCH_V7,		FPU_ARCH_VFP, armv7),
+  ARM_ARCH_OPT2 ("armv6kzt2",	  ARM_ARCH_V6KZT2,	FPU_ARCH_SOFTVFP,
+		 armv5te),
+  ARM_ARCH_OPT2 ("armv6zkt2",	  ARM_ARCH_V6KZT2,	FPU_ARCH_SOFTVFP,
+		 armv5te),
+  ARM_ARCH_OPT ("armv6-m",	  ARM_ARCH_V6M,		FPU_ARCH_SOFTVFP),
+  ARM_ARCH_OPT ("armv6s-m",	  ARM_ARCH_V6SM,	FPU_ARCH_SOFTVFP),
+  ARM_ARCH_OPT2 ("armv7",	  ARM_ARCH_V7,		FPU_ARCH_SOFTVFP,
+		 armv7),
   /* The official spelling of the ARMv7 profile variants is the dashed form.
      Accept the non-dashed form for compatibility with old toolchains.  */
-  ARM_ARCH_OPT2 ("armv7a",	  ARM_ARCH_V7A,		FPU_ARCH_VFP, armv7a),
-  ARM_ARCH_OPT2 ("armv7ve",	  ARM_ARCH_V7VE,	FPU_ARCH_VFP, armv7ve),
-  ARM_ARCH_OPT2 ("armv7r",	  ARM_ARCH_V7R,		FPU_ARCH_VFP, armv7r),
-  ARM_ARCH_OPT ("armv7m",	  ARM_ARCH_V7M,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT2 ("armv7-a",	  ARM_ARCH_V7A,		FPU_ARCH_VFP, armv7a),
-  ARM_ARCH_OPT2 ("armv7-r",	  ARM_ARCH_V7R,		FPU_ARCH_VFP, armv7r),
-  ARM_ARCH_OPT ("armv7-m",	  ARM_ARCH_V7M,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT2 ("armv7e-m",	  ARM_ARCH_V7EM,	FPU_ARCH_VFP, armv7em),
-  ARM_ARCH_OPT ("armv8-m.base",	  ARM_ARCH_V8M_BASE,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT2 ("armv8-m.main",  ARM_ARCH_V8M_MAIN,	FPU_ARCH_VFP,
+  ARM_ARCH_OPT2 ("armv7a",	  ARM_ARCH_V7A,		FPU_ARCH_SOFTVFP,
+		 armv7a),
+  ARM_ARCH_OPT2 ("armv7ve",	  ARM_ARCH_V7VE,	FPU_ARCH_SOFTVFP,
+		 armv7ve),
+  ARM_ARCH_OPT2 ("armv7r",	  ARM_ARCH_V7R,		FPU_ARCH_SOFTVFP,
+		 armv7r),
+  ARM_ARCH_OPT ("armv7m",	  ARM_ARCH_V7M,		FPU_ARCH_SOFTVFP),
+  ARM_ARCH_OPT2 ("armv7-a",	  ARM_ARCH_V7A,		FPU_ARCH_SOFTVFP,
+		 armv7a),
+  ARM_ARCH_OPT2 ("armv7-r",	  ARM_ARCH_V7R,		FPU_ARCH_SOFTVFP,
+		 armv7r),
+  ARM_ARCH_OPT ("armv7-m",	  ARM_ARCH_V7M,		FPU_ARCH_SOFTVFP),
+  ARM_ARCH_OPT2 ("armv7e-m",	  ARM_ARCH_V7EM,	FPU_ARCH_SOFTVFP,
+		 armv7em),
+  ARM_ARCH_OPT ("armv8-m.base",	  ARM_ARCH_V8M_BASE,	FPU_ARCH_SOFTVFP),
+  ARM_ARCH_OPT2 ("armv8-m.main",  ARM_ARCH_V8M_MAIN,	FPU_ARCH_SOFTVFP,
 		 armv8m_main),
-  ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN,	FPU_ARCH_VFP,
+  ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN,	FPU_ARCH_SOFTVFP,
 		 armv8_1m_main),
-  ARM_ARCH_OPT2 ("armv8-a",	  ARM_ARCH_V8A,		FPU_ARCH_VFP, armv8a),
-  ARM_ARCH_OPT2 ("armv8.1-a",	  ARM_ARCH_V8_1A,	FPU_ARCH_VFP, armv81a),
-  ARM_ARCH_OPT2 ("armv8.2-a",	  ARM_ARCH_V8_2A,	FPU_ARCH_VFP, armv82a),
-  ARM_ARCH_OPT2 ("armv8.3-a",	  ARM_ARCH_V8_3A,	FPU_ARCH_VFP, armv82a),
-  ARM_ARCH_OPT2 ("armv8-r",	  ARM_ARCH_V8R,		FPU_ARCH_VFP, armv8r),
-  ARM_ARCH_OPT2 ("armv8.4-a",	  ARM_ARCH_V8_4A,	FPU_ARCH_VFP, armv84a),
-  ARM_ARCH_OPT2 ("armv8.5-a",	  ARM_ARCH_V8_5A,	FPU_ARCH_VFP, armv85a),
-  ARM_ARCH_OPT2 ("armv8.6-a",	  ARM_ARCH_V8_6A,	FPU_ARCH_VFP, armv86a),
-  ARM_ARCH_OPT2 ("armv8.7-a",	  ARM_ARCH_V8_7A,	FPU_ARCH_VFP, armv87a),
-  ARM_ARCH_OPT2 ("armv8.8-a",	  ARM_ARCH_V8_8A,	FPU_ARCH_VFP, armv88a),
-  ARM_ARCH_OPT2 ("armv8.9-a",	  ARM_ARCH_V8_9A,	FPU_ARCH_VFP, armv89a),
-  ARM_ARCH_OPT2 ("armv9-a",	  ARM_ARCH_V9A,		FPU_ARCH_VFP, armv9a),
-  ARM_ARCH_OPT2 ("armv9.1-a",	  ARM_ARCH_V9_1A,	FPU_ARCH_VFP, armv91a),
-  ARM_ARCH_OPT2 ("armv9.2-a",	  ARM_ARCH_V9_2A,	FPU_ARCH_VFP, armv92a),
-  ARM_ARCH_OPT2 ("armv9.3-a",	  ARM_ARCH_V9_2A,	FPU_ARCH_VFP, armv93a),
-  ARM_ARCH_OPT2 ("armv9.4-a",	  ARM_ARCH_V9_4A,	FPU_ARCH_VFP, armv94a),
-  ARM_ARCH_OPT2 ("armv9.5-a",	  ARM_ARCH_V9_5A,	FPU_ARCH_VFP, armv95a),
-  ARM_ARCH_OPT ("xscale",	  ARM_ARCH_XSCALE,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("iwmmxt",	  ARM_ARCH_IWMMXT,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("iwmmxt2",	  ARM_ARCH_IWMMXT2,	FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv8-a",	  ARM_ARCH_V8A,		FPU_ARCH_SOFTVFP,
+		 armv8a),
+  ARM_ARCH_OPT2 ("armv8.1-a",	  ARM_ARCH_V8_1A,	FPU_ARCH_SOFTVFP,
+		 armv81a),
+  ARM_ARCH_OPT2 ("armv8.2-a",	  ARM_ARCH_V8_2A,	FPU_ARCH_SOFTVFP,
+		 armv82a),
+  ARM_ARCH_OPT2 ("armv8.3-a",	  ARM_ARCH_V8_3A,	FPU_ARCH_SOFTVFP,
+		 armv82a),
+  ARM_ARCH_OPT2 ("armv8-r",	  ARM_ARCH_V8R,		FPU_ARCH_SOFTVFP,
+		 armv8r),
+  ARM_ARCH_OPT2 ("armv8.4-a",	  ARM_ARCH_V8_4A,	FPU_ARCH_SOFTVFP,
+		 armv84a),
+  ARM_ARCH_OPT2 ("armv8.5-a",	  ARM_ARCH_V8_5A,	FPU_ARCH_SOFTVFP,
+		 armv85a),
+  ARM_ARCH_OPT2 ("armv8.6-a",	  ARM_ARCH_V8_6A,	FPU_ARCH_SOFTVFP,
+		 armv86a),
+  ARM_ARCH_OPT2 ("armv8.7-a",	  ARM_ARCH_V8_7A,	FPU_ARCH_SOFTVFP,
+		 armv87a),
+  ARM_ARCH_OPT2 ("armv8.8-a",	  ARM_ARCH_V8_8A,	FPU_ARCH_SOFTVFP,
+		 armv88a),
+  ARM_ARCH_OPT2 ("armv8.9-a",	  ARM_ARCH_V8_9A,	FPU_ARCH_SOFTVFP,
+		 armv89a),
+  ARM_ARCH_OPT2 ("armv9-a",	  ARM_ARCH_V9A,		FPU_ARCH_SOFTVFP,
+		 armv9a),
+  ARM_ARCH_OPT2 ("armv9.1-a",	  ARM_ARCH_V9_1A,	FPU_ARCH_SOFTVFP,
+		 armv91a),
+  ARM_ARCH_OPT2 ("armv9.2-a",	  ARM_ARCH_V9_2A,	FPU_ARCH_SOFTVFP,
+		 armv92a),
+  ARM_ARCH_OPT2 ("armv9.3-a",	  ARM_ARCH_V9_2A,	FPU_ARCH_SOFTVFP,
+		 armv93a),
+  ARM_ARCH_OPT2 ("armv9.4-a",	  ARM_ARCH_V9_4A,	FPU_ARCH_SOFTVFP,
+		 armv94a),
+  ARM_ARCH_OPT2 ("armv9.5-a",	  ARM_ARCH_V9_5A,	FPU_ARCH_SOFTVFP,
+		 armv95a),
+  ARM_ARCH_OPT ("xscale",	  ARM_ARCH_XSCALE,	FPU_ARCH_SOFTVFP),
+  ARM_ARCH_OPT ("iwmmxt",	  ARM_ARCH_IWMMXT,	FPU_ARCH_SOFTVFP),
+  ARM_ARCH_OPT ("iwmmxt2",	  ARM_ARCH_IWMMXT2,	FPU_ARCH_SOFTVFP),
   { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
 };
 #undef ARM_ARCH_OPT
@@ -32147,7 +32185,7 @@ static const struct arm_option_fpu_value_table arm_fpus[] =
   {"fpa10",		FPU_ARCH_FPA},
   {"fpa11",		FPU_ARCH_FPA},
   {"arm7500fe",		FPU_ARCH_FPA},
-  {"softvfp",		FPU_ARCH_VFP},
+  {"softvfp",		FPU_ARCH_SOFTVFP},
   {"softvfp+vfp",	FPU_ARCH_VFP_V2},
   {"vfp",		FPU_ARCH_VFP_V2},
   {"vfp9",		FPU_ARCH_VFP_V2},
diff --git a/gas/config/te-armeabi.h b/gas/config/te-armeabi.h
index 546e72ed188..f23509798c6 100644
--- a/gas/config/te-armeabi.h
+++ b/gas/config/te-armeabi.h
@@ -18,7 +18,7 @@
    02110-1301, USA.  */
 
 /* The EABI requires the use of VFP.  */
-#define FPU_DEFAULT FPU_ARCH_VFP
+#define FPU_DEFAULT FPU_ARCH_SOFTVFP
 #define EABI_DEFAULT EF_ARM_EABI_VER5
 
 #define LOCAL_LABELS_DOLLAR 1
diff --git a/gas/config/te-armfbsdvfp.h b/gas/config/te-armfbsdvfp.h
index a3b15f1d7d5..c13d46dc059 100644
--- a/gas/config/te-armfbsdvfp.h
+++ b/gas/config/te-armfbsdvfp.h
@@ -19,4 +19,4 @@
 
 #include "te-armfbsdeabi.h"
 
-#define FPU_DEFAULT FPU_ARCH_VFP
+#define FPU_DEFAULT FPU_ARCH_SOFTVFP
diff --git a/gas/config/te-armlinuxeabi.h b/gas/config/te-armlinuxeabi.h
index 617c9414419..e7647c67d23 100644
--- a/gas/config/te-armlinuxeabi.h
+++ b/gas/config/te-armlinuxeabi.h
@@ -20,5 +20,5 @@
 #include "te-linux.h"
 
 /* The EABI requires the use of VFP.  */
-#define FPU_DEFAULT FPU_ARCH_VFP
+#define FPU_DEFAULT FPU_ARCH_SOFTVFP
 #define EABI_DEFAULT EF_ARM_EABI_VER5
diff --git a/gas/config/te-nacl.h b/gas/config/te-nacl.h
index ebcbd4da760..7678d4b3241 100644
--- a/gas/config/te-nacl.h
+++ b/gas/config/te-nacl.h
@@ -24,7 +24,7 @@
 
 /* These are for ARM but don't hurt other CPU targets.
    They match the settings from te-armeabi.h; NaCl/ARM is based on EABI.  */
-#define FPU_DEFAULT FPU_ARCH_VFP
+#define FPU_DEFAULT FPU_ARCH_SOFTVFP
 #define EABI_DEFAULT EF_ARM_EABI_VER5
 
 #include "obj-format.h"
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index faa793c447e..c921f76ec7d 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -247,7 +247,7 @@
 #define FPU_FPA		  (FPU_FPA_EXT_V1    | FPU_FPA_EXT_V2)
 
 /* Deprecated.  */
-#define FPU_ARCH_VFP		ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
+#define FPU_ARCH_SOFTVFP	ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
 
 #define FPU_ARCH_FPE		ARM_FEATURE_COPROC (FPU_FPA_EXT_V1)
 #define FPU_ARCH_FPA		ARM_FEATURE_COPROC (FPU_FPA)

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 03/11] arm: default to softvfp on armv6 or later cores
  2024-06-03 11:49 [PATCH 00/11] arm: Remove FPA support from gas/binutils Richard Earnshaw
  2024-06-03 11:49 ` [PATCH 01/11] arm: remove FPA related tests Richard Earnshaw
  2024-06-03 11:49 ` [PATCH 02/11] arm: rename FPU_ARCH_VFP to FPU_ARCH_SOFTVFP Richard Earnshaw
@ 2024-06-03 11:49 ` Richard Earnshaw
  2024-06-03 11:49 ` [PATCH 04/11] arm: adjust FPU selection logic Richard Earnshaw
                   ` (7 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Richard Earnshaw @ 2024-06-03 11:49 UTC (permalink / raw)
  To: binutils; +Cc: nickc, Richard Earnshaw

[-- Attachment #1: Type: text/plain, Size: 678 bytes --]


From armv6 onwards a lot of cores started to come with a physical VFP
implementation; but many still did not and in some cases there are
both variants.  For the cores that lacked a physical VFP we would fall
back to FPU_NONE if the platform/ABI did not mandate something else.
To make matters worse, FPU_NONE is internal state used to imply
soft-fpa (ie a mixed-endian double format), so any use of .double in
hand-written assembly is almost certainly generating incorrect output.

That's undesirable, all these cores should really default to a softvfp
model.
---
 gas/config/tc-arm.c | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0003-arm-default-to-softvfp-on-armv6-or-later-cores.patch --]
[-- Type: text/x-patch; name="0003-arm-default-to-softvfp-on-armv6-or-later-cores.patch", Size: 3993 bytes --]

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 12e8f7cfc84..8452ea17a02 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -31458,10 +31458,10 @@ static const struct arm_cpu_option_table arm_cpus[] =
 	       FPU_ARCH_VFP_V2),
   ARM_CPU_OPT ("arm1136js",	  "ARM1136J-S",	       ARM_ARCH_V6,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("arm1136j-s",	  NULL,		       ARM_ARCH_V6,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("arm1136jfs",	  "ARM1136JF-S",       ARM_ARCH_V6,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_VFP_V2),
@@ -31473,22 +31473,22 @@ static const struct arm_cpu_option_table arm_cpus[] =
 	       FPU_ARCH_VFP_V2),
   ARM_CPU_OPT ("mpcorenovfp",	  "MPCore",	       ARM_ARCH_V6K,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("arm1156t2-s",	  NULL,		       ARM_ARCH_V6T2,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("arm1156t2f-s",	  NULL,		       ARM_ARCH_V6T2,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_VFP_V2),
   ARM_CPU_OPT ("arm1176jz-s",	  NULL,		       ARM_ARCH_V6KZ,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("arm1176jzf-s",	  NULL,		       ARM_ARCH_V6KZ,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_VFP_V2),
   ARM_CPU_OPT ("cortex-a5",	  "Cortex-A5",	       ARM_ARCH_V7A,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-a7",	  "Cortex-A7",	       ARM_ARCH_V7VE,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_NEON_VFP_V4),
@@ -31559,13 +31559,13 @@ static const struct arm_cpu_option_table arm_cpus[] =
 	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
   ARM_CPU_OPT ("cortex-r4",	  "Cortex-R4",	       ARM_ARCH_V7R,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-r4f",	  "Cortex-R4F",	       ARM_ARCH_V7R,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_VFP_V3D16),
   ARM_CPU_OPT ("cortex-r5",	  "Cortex-R5",	       ARM_ARCH_V7R,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-r7",	  "Cortex-R7",	       ARM_ARCH_V7R,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
 	       FPU_ARCH_VFP_V3D16),
@@ -31580,31 +31580,31 @@ static const struct arm_cpu_option_table arm_cpus[] =
 	      FPU_ARCH_NEON_VFP_ARMV8),
   ARM_CPU_OPT ("cortex-m35p",	  "Cortex-M35P",       ARM_ARCH_V8M_MAIN,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m33",	  "Cortex-M33",	       ARM_ARCH_V8M_MAIN,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m23",	  "Cortex-M23",	       ARM_ARCH_V8M_BASE,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m7",	  "Cortex-M7",	       ARM_ARCH_V7EM,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m4",	  "Cortex-M4",	       ARM_ARCH_V7EM,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m3",	  "Cortex-M3",	       ARM_ARCH_V7M,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m1",	  "Cortex-M1",	       ARM_ARCH_V6SM,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m0",	  "Cortex-M0",	       ARM_ARCH_V6SM,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m0plus",	  "Cortex-M0+",	       ARM_ARCH_V6SM,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-x1",   "Cortex-X1",	       ARM_ARCH_V8_2A,
 	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
 	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 04/11] arm: adjust FPU selection logic
  2024-06-03 11:49 [PATCH 00/11] arm: Remove FPA support from gas/binutils Richard Earnshaw
                   ` (2 preceding siblings ...)
  2024-06-03 11:49 ` [PATCH 03/11] arm: default to softvfp on armv6 or later cores Richard Earnshaw
@ 2024-06-03 11:49 ` Richard Earnshaw
  2024-06-03 11:49 ` [PATCH 05/11] arm: redirect fp constant data directives through a wrapper Richard Earnshaw
                   ` (6 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Richard Earnshaw @ 2024-06-03 11:49 UTC (permalink / raw)
  To: binutils; +Cc: nickc, Richard Earnshaw

[-- Attachment #1: Type: text/plain, Size: 703 bytes --]


The logic here seems to be overly complex, so simplify it a bit.  One
particular problem was that using the legacy -mno-fpu option was not
working properly, as this has all the feature bits set to zero causing
the code to then pick a different FPU as the default.  Fix this by
only selecting an FPU as a fallback if the code has not otherwise
selected one: there was only one route by which this could happen.

This patch is really a pre-cursor to the following one where we want
to make no-fpu internally a fall-back position for some legacy
processors where previously we would have dropped back to the FPA.
---
 gas/config/tc-arm.c | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0004-arm-adjust-FPU-selection-logic.patch --]
[-- Type: text/x-patch; name="0004-arm-adjust-FPU-selection-logic.patch", Size: 1135 bytes --]

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 8452ea17a02..9294619e1a4 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -187,7 +187,6 @@ static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V1;
 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3;
 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1;
-static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
 
@@ -30817,19 +30816,13 @@ md_begin (void)
 	selected_fpu = *mcpu_fpu_opt;
       else if (march_fpu_opt)
 	selected_fpu = *march_fpu_opt;
+      else
+	selected_fpu = fpu_default;
 #else
       selected_fpu = fpu_default;
 #endif
     }
 
-  if (ARM_FEATURE_ZERO (selected_fpu))
-    {
-      if (!no_cpu_selected ())
-	selected_fpu = fpu_default;
-      else
-	selected_fpu = fpu_arch_fpa;
-    }
-
 #ifdef CPU_DEFAULT
   if (ARM_FEATURE_ZERO (selected_arch))
     {

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 05/11] arm: redirect fp constant data directives through a wrapper
  2024-06-03 11:49 [PATCH 00/11] arm: Remove FPA support from gas/binutils Richard Earnshaw
                   ` (3 preceding siblings ...)
  2024-06-03 11:49 ` [PATCH 04/11] arm: adjust FPU selection logic Richard Earnshaw
@ 2024-06-03 11:49 ` Richard Earnshaw
  2024-06-03 11:49 ` [PATCH 06/11] arm: change default FPUs from FPA to none Richard Earnshaw
                   ` (5 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Richard Earnshaw @ 2024-06-03 11:49 UTC (permalink / raw)
  To: binutils; +Cc: nickc, Richard Earnshaw

[-- Attachment #1: Type: text/plain, Size: 1593 bytes --]


Assembler directives such as .float, or .double are handled by generic
code, but on Arm, their output can vary depeding on the type of FPU
begin targetted.  When we remove FPA support we don't want to silently
generate different code for processors that previously defaulted to
the FPA, so redirect these directives through a wrapper function that
checks the FPU is enabled; we use the legacy -mno-fpu in the test to
catch this.

Also fix a few tests so that they won't start to fail on targets (eg
arm-wince-pe) where there is no default format for the FPU and we pick
this from the default processor type.
---
 gas/config/tc-arm.c                           | 25 +++++++++++++++----
 gas/testsuite/gas/all/gas.exp                 |  2 ++
 gas/testsuite/gas/arm/bfloat16-directive-be.d |  2 +-
 gas/testsuite/gas/arm/bfloat16-directive-le.d |  2 +-
 gas/testsuite/gas/arm/float16-bad.d           |  1 +
 gas/testsuite/gas/arm/float16-be.d            |  2 +-
 .../gas/arm/float16-format-opt-bad.d          |  2 +-
 gas/testsuite/gas/arm/float16-le.d            |  2 +-
 gas/testsuite/gas/arm/fp-directive-bad.d      |  4 +++
 gas/testsuite/gas/arm/fp-directive-bad.l      |  7 ++++++
 gas/testsuite/gas/arm/fp-directive.d          |  9 +++++++
 gas/testsuite/gas/arm/fp-directive.s          |  7 ++++++
 12 files changed, 55 insertions(+), 10 deletions(-)
 create mode 100644 gas/testsuite/gas/arm/fp-directive-bad.d
 create mode 100644 gas/testsuite/gas/arm/fp-directive-bad.l
 create mode 100644 gas/testsuite/gas/arm/fp-directive.d
 create mode 100644 gas/testsuite/gas/arm/fp-directive.s


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0005-arm-redirect-fp-constant-data-directives-through-a-w.patch --]
[-- Type: text/x-patch; name="0005-arm-redirect-fp-constant-data-directives-through-a-w.patch", Size: 6777 bytes --]

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 9294619e1a4..1ba7bb31ac5 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -5148,6 +5148,14 @@ set_fp16_format (int dummy ATTRIBUTE_UNUSED)
   ignore_rest_of_line ();
 }
 
+static void s_arm_float_cons (int float_type)
+{
+  /* We still parse the directive on error, so that any syntactic issues
+     are picked up.  */
+  if (ARM_FEATURE_ZERO (selected_fpu))
+    as_bad (_("the floating-point format has not been set (or has been disabled)"));
+  float_cons (float_type);
+}
 /* This table describes all the machine specific pseudo-ops the assembler
    has to support.  The fields are:
      pseudo-op name without dot
@@ -5212,10 +5220,17 @@ const pseudo_typeS md_pseudo_table[] =
   { "loc",  dwarf2_directive_loc,  0 },
   { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
 #endif
-  { "extend",	   float_cons, 'x' },
-  { "ldouble",	   float_cons, 'x' },
-  { "packed",	   float_cons, 'p' },
-  { "bfloat16",	   float_cons, 'b' },
+  /* Override the default float_cons handling so that we can validate
+     the FPU setting.  */
+  { "float",	   s_arm_float_cons, 'f' },
+  { "single",	   s_arm_float_cons, 'f' },
+  { "double",	   s_arm_float_cons, 'd' },
+  { "dc.s",	   s_arm_float_cons, 'f' },
+  { "dc.d",	   s_arm_float_cons, 'd' },
+  { "extend",	   s_arm_float_cons, 'x' },
+  { "ldouble",	   s_arm_float_cons, 'x' },
+  { "packed",	   s_arm_float_cons, 'p' },
+  { "bfloat16",	   s_arm_float_cons, 'b' },
 #ifdef TE_PE
   {"secrel32", pe_directive_secrel, 0},
 #endif
@@ -5226,7 +5241,7 @@ const pseudo_typeS md_pseudo_table[] =
   {"asmfunc",      s_ccs_asmfunc,    0},
   {"endasmfunc",   s_ccs_endasmfunc, 0},
 
-  {"float16", float_cons, 'h' },
+  {"float16", s_arm_float_cons, 'h' },
   {"float16_format", set_fp16_format, 0 },
 
   { 0, 0, 0 }
diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp
index b9ff43997cb..af461b1988d 100644
--- a/gas/testsuite/gas/all/gas.exp
+++ b/gas/testsuite/gas/all/gas.exp
@@ -47,6 +47,8 @@ if { ![istarget cris-*-*] && ![istarget crisv32-*-*]
      && ![istarget z80-*-*] } then {
     if { [istarget tic4x-*-*] } then {
 	set as_opt ""
+    } elseif { [istarget arm*-*-pe ] } then {
+	set as_opt "--defsym hasnan=1 -mfpu=softvfp"
     } else {
 	set as_opt "--defsym hasnan=1"
     }
diff --git a/gas/testsuite/gas/arm/bfloat16-directive-be.d b/gas/testsuite/gas/arm/bfloat16-directive-be.d
index 8862f8302f7..44eadb33194 100644
--- a/gas/testsuite/gas/arm/bfloat16-directive-be.d
+++ b/gas/testsuite/gas/arm/bfloat16-directive-be.d
@@ -1,7 +1,7 @@
 # name: Big endian bfloat16 literal directives
 # source: bfloat16-directive.s
 # objdump: -s --section=.data
-# as: -mbig-endian
+# as: -mbig-endian -mfpu=softvfp
 
 .*: +file format .*
 
diff --git a/gas/testsuite/gas/arm/bfloat16-directive-le.d b/gas/testsuite/gas/arm/bfloat16-directive-le.d
index da94b6b254c..c595d8b065a 100644
--- a/gas/testsuite/gas/arm/bfloat16-directive-le.d
+++ b/gas/testsuite/gas/arm/bfloat16-directive-le.d
@@ -1,7 +1,7 @@
 # name: Little endian bfloat16 literal directives
 # source: bfloat16-directive.s
 # objdump: -s --section=.data
-# as: -mlittle-endian
+# as: -mlittle-endian -mfpu=softvfp
 
 .*: +file format .*
 
diff --git a/gas/testsuite/gas/arm/float16-bad.d b/gas/testsuite/gas/arm/float16-bad.d
index 8eac0af5cbb..604bb20adaf 100644
--- a/gas/testsuite/gas/arm/float16-bad.d
+++ b/gas/testsuite/gas/arm/float16-bad.d
@@ -1,3 +1,4 @@
 # name: Invalid float16 literals (IEEE 754 & Alternative)
 # source: float16-bad.s
 # error_output: float16-bad.l
+# as: -mfpu=softvfp
diff --git a/gas/testsuite/gas/arm/float16-be.d b/gas/testsuite/gas/arm/float16-be.d
index e31d9fbf432..b63d6cd49d5 100644
--- a/gas/testsuite/gas/arm/float16-be.d
+++ b/gas/testsuite/gas/arm/float16-be.d
@@ -1,7 +1,7 @@
 # name: Big endian float16 literals (IEEE 754 & Alternative)
 # source: float16.s
 # objdump: -s --section=.data
-# as: -mbig-endian
+# as: -mbig-endian -mfpu=softvfp
 
 .*: +file format .*arm.*
 
diff --git a/gas/testsuite/gas/arm/float16-format-opt-bad.d b/gas/testsuite/gas/arm/float16-format-opt-bad.d
index 861125800da..af8cca48956 100644
--- a/gas/testsuite/gas/arm/float16-format-opt-bad.d
+++ b/gas/testsuite/gas/arm/float16-format-opt-bad.d
@@ -1,4 +1,4 @@
 # name: Invalid combination of command line arguments and directives
 # source: float16.s
 # error_output: float16-format-opt-bad.l
-# as: -mfp16-format=ieee
+# as: -mfpu=softvfp -mfp16-format=ieee
diff --git a/gas/testsuite/gas/arm/float16-le.d b/gas/testsuite/gas/arm/float16-le.d
index c1fe7c20dc6..abbf09202be 100644
--- a/gas/testsuite/gas/arm/float16-le.d
+++ b/gas/testsuite/gas/arm/float16-le.d
@@ -1,7 +1,7 @@
 # name: Little endian float16 literals (IEEE 754 & Alternative)
 # source: float16.s
 # objdump: -s --section=.data
-# as: -mlittle-endian
+# as: -mlittle-endian -mfpu=softvfp
 
 .*: +file format .*arm.*
 
diff --git a/gas/testsuite/gas/arm/fp-directive-bad.d b/gas/testsuite/gas/arm/fp-directive-bad.d
new file mode 100644
index 00000000000..dfa01e6829c
--- /dev/null
+++ b/gas/testsuite/gas/arm/fp-directive-bad.d
@@ -0,0 +1,4 @@
+#name: floating-point directives disabled
+#source: fp-directive.s
+#as: -mno-warn-deprecated -mno-fpu
+#error_output: fp-directive-bad.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/arm/fp-directive-bad.l b/gas/testsuite/gas/arm/fp-directive-bad.l
new file mode 100644
index 00000000000..263cc9e6de4
--- /dev/null
+++ b/gas/testsuite/gas/arm/fp-directive-bad.l
@@ -0,0 +1,7 @@
+[^:]*: Assembler messages:
+[^:]*:2: Error: the floating-point format has not been set \(or has been disabled\)
+[^:]*:3: Error: the floating-point format has not been set \(or has been disabled\)
+[^:]*:4: Error: the floating-point format has not been set \(or has been disabled\)
+[^:]*:5: Error: the floating-point format has not been set \(or has been disabled\)
+[^:]*:6: Error: the floating-point format has not been set \(or has been disabled\)
+[^:]*:7: Error: the floating-point format has not been set \(or has been disabled\)
diff --git a/gas/testsuite/gas/arm/fp-directive.d b/gas/testsuite/gas/arm/fp-directive.d
new file mode 100644
index 00000000000..46ff9e9c571
--- /dev/null
+++ b/gas/testsuite/gas/arm/fp-directive.d
@@ -0,0 +1,9 @@
+#name: floating-point directives
+#objdump: -s --section=.data
+#as: -mfpu=softvfp
+
+.*: +file format .*arm.*
+
+Contents of section \.data:
+ 0000 .*
+ 0010 .*
diff --git a/gas/testsuite/gas/arm/fp-directive.s b/gas/testsuite/gas/arm/fp-directive.s
new file mode 100644
index 00000000000..c6fc22760f7
--- /dev/null
+++ b/gas/testsuite/gas/arm/fp-directive.s
@@ -0,0 +1,7 @@
+	.data
+	.float 1.0
+	.double 2.0
+	.single 3.0
+	.dc.s 5.3
+	.dc.d 6
+	.float16 4.0

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 06/11] arm: change default FPUs from FPA to none
  2024-06-03 11:49 [PATCH 00/11] arm: Remove FPA support from gas/binutils Richard Earnshaw
                   ` (4 preceding siblings ...)
  2024-06-03 11:49 ` [PATCH 05/11] arm: redirect fp constant data directives through a wrapper Richard Earnshaw
@ 2024-06-03 11:49 ` Richard Earnshaw
  2024-06-03 11:49 ` [PATCH 07/11] arm: remove options to select the FPA Richard Earnshaw
                   ` (4 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Richard Earnshaw @ 2024-06-03 11:49 UTC (permalink / raw)
  To: binutils; +Cc: nickc, Richard Earnshaw

[-- Attachment #1: Type: text/plain, Size: 381 bytes --]


Change the cases where the default FPU was FPA to none.  This should
ensure that any code that used settings to pick the floating-point
order will not silently produce a different output.  The options that
explicitly set the FPA remain for the moment.
---
 gas/config/tc-arm.c | 125 ++++++++++++++++++++++----------------------
 1 file changed, 63 insertions(+), 62 deletions(-)


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0006-arm-change-default-FPUs-from-FPA-to-none.patch --]
[-- Type: text/x-patch; name="0006-arm-change-default-FPUs-from-FPA-to-none.patch", Size: 8965 bytes --]

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 1ba7bb31ac5..12610fd8766 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -118,19 +118,20 @@ static bool out_of_range_p (offsetT value, offsetT bits)
 
 #ifndef FPU_DEFAULT
 # ifdef TE_LINUX
-#  define FPU_DEFAULT FPU_ARCH_FPA
+#  define FPU_DEFAULT FPU_NONE
 # elif defined (TE_NetBSD)
 #  ifdef OBJ_ELF
 #   define FPU_DEFAULT FPU_ARCH_SOFTVFP	/* Soft-float, but VFP order.  */
 #  else
     /* Legacy a.out format.  */
-#   define FPU_DEFAULT FPU_ARCH_FPA	/* Soft-float, but FPA order.  */
+#   define FPU_DEFAULT FPU_NONE	/* Soft-float, no FPU.  */
 #  endif
 # elif defined (TE_VXWORKS)
 #  define FPU_DEFAULT FPU_ARCH_SOFTVFP	/* Soft-float, VFP order.  */
 # else
-   /* For backwards compatibility, default to FPA.  */
-#  define FPU_DEFAULT FPU_ARCH_FPA
+   /* For backwards compatibility, default to no-fpu so that we don't
+      get silent code changes of FP literal data.  */
+#  define FPU_DEFAULT FPU_NONE
 # endif
 #endif /* ifndef FPU_DEFAULT */
 
@@ -31247,142 +31248,142 @@ static const struct arm_cpu_option_table arm_cpus[] =
 {
   ARM_CPU_OPT ("all",		  NULL,		       ARM_ANY,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm1",		  NULL,		       ARM_ARCH_V1,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm2",		  NULL,		       ARM_ARCH_V2,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm250",	  NULL,		       ARM_ARCH_V2S,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm3",		  NULL,		       ARM_ARCH_V2S,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm6",		  NULL,		       ARM_ARCH_V3,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm60",		  NULL,		       ARM_ARCH_V3,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm600",	  NULL,		       ARM_ARCH_V3,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm610",	  NULL,		       ARM_ARCH_V3,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm620",	  NULL,		       ARM_ARCH_V3,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm7",		  NULL,		       ARM_ARCH_V3,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm7m",		  NULL,		       ARM_ARCH_V3M,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm7d",		  NULL,		       ARM_ARCH_V3,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm7dm",	  NULL,		       ARM_ARCH_V3M,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm7di",	  NULL,		       ARM_ARCH_V3,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm7dmi",	  NULL,		       ARM_ARCH_V3M,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm70",		  NULL,		       ARM_ARCH_V3,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm700",	  NULL,		       ARM_ARCH_V3,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm700i",	  NULL,		       ARM_ARCH_V3,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm710",	  NULL,		       ARM_ARCH_V3,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm710t",	  NULL,		       ARM_ARCH_V4T,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm720",	  NULL,		       ARM_ARCH_V3,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm720t",	  NULL,		       ARM_ARCH_V4T,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm740t",	  NULL,		       ARM_ARCH_V4T,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm710c",	  NULL,		       ARM_ARCH_V3,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm7100",	  NULL,		       ARM_ARCH_V3,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm7500",	  NULL,		       ARM_ARCH_V3,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm7500fe",	  NULL,		       ARM_ARCH_V3,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm7t",		  NULL,		       ARM_ARCH_V4T,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm7tdmi",	  NULL,		       ARM_ARCH_V4T,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm7tdmi-s",	  NULL,		       ARM_ARCH_V4T,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm8",		  NULL,		       ARM_ARCH_V4,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm810",	  NULL,		       ARM_ARCH_V4,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("strongarm",	  NULL,		       ARM_ARCH_V4,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("strongarm1",	  NULL,		       ARM_ARCH_V4,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("strongarm110",	  NULL,		       ARM_ARCH_V4,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("strongarm1100",	  NULL,		       ARM_ARCH_V4,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("strongarm1110",	  NULL,		       ARM_ARCH_V4,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm9",		  NULL,		       ARM_ARCH_V4T,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm920",	  "ARM920T",	       ARM_ARCH_V4T,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm920t",	  NULL,		       ARM_ARCH_V4T,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm922t",	  NULL,		       ARM_ARCH_V4T,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm940t",	  NULL,		       ARM_ARCH_V4T,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("arm9tdmi",	  NULL,		       ARM_ARCH_V4T,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("fa526",		  NULL,		       ARM_ARCH_V4,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
   ARM_CPU_OPT ("fa626",		  NULL,		       ARM_ARCH_V4,
 	       ARM_ARCH_NONE,
-	       FPU_ARCH_FPA),
+	       FPU_NONE),
 
   /* For V5 or later processors we default to using VFP; but the user
      should really set the FPU type explicitly.	 */
@@ -31654,7 +31655,7 @@ static const struct arm_cpu_option_table arm_cpus[] =
   /* Maverick extensions are no-longer supported, but we can still
      recognize the CPU name and treat it like an Arm920T.  */
   ARM_CPU_OPT ("ep9312",	  "ARM920T",	       ARM_ARCH_V4T,
-	       ARM_ARCH_NONE, FPU_ARCH_FPA),
+	       ARM_ARCH_NONE, FPU_NONE),
 
   /* Marvell processors.  */
   ARM_CPU_OPT ("marvell-pj4",	  NULL,		       ARM_ARCH_V7A,
@@ -31963,17 +31964,17 @@ static const struct arm_ext_table armv8r_ext_table[] =
 
 static const struct arm_arch_option_table arm_archs[] =
 {
-  ARM_ARCH_OPT ("all",		  ARM_ANY,		FPU_ARCH_FPA),
-  ARM_ARCH_OPT ("armv1",	  ARM_ARCH_V1,		FPU_ARCH_FPA),
-  ARM_ARCH_OPT ("armv2",	  ARM_ARCH_V2,		FPU_ARCH_FPA),
-  ARM_ARCH_OPT ("armv2a",	  ARM_ARCH_V2S,		FPU_ARCH_FPA),
-  ARM_ARCH_OPT ("armv2s",	  ARM_ARCH_V2S,		FPU_ARCH_FPA),
-  ARM_ARCH_OPT ("armv3",	  ARM_ARCH_V3,		FPU_ARCH_FPA),
-  ARM_ARCH_OPT ("armv3m",	  ARM_ARCH_V3M,		FPU_ARCH_FPA),
-  ARM_ARCH_OPT ("armv4",	  ARM_ARCH_V4,		FPU_ARCH_FPA),
-  ARM_ARCH_OPT ("armv4xm",	  ARM_ARCH_V4xM,	FPU_ARCH_FPA),
-  ARM_ARCH_OPT ("armv4t",	  ARM_ARCH_V4T,		FPU_ARCH_FPA),
-  ARM_ARCH_OPT ("armv4txm",	  ARM_ARCH_V4TxM,	FPU_ARCH_FPA),
+  ARM_ARCH_OPT ("all",		  ARM_ANY,		FPU_NONE),
+  ARM_ARCH_OPT ("armv1",	  ARM_ARCH_V1,		FPU_NONE),
+  ARM_ARCH_OPT ("armv2",	  ARM_ARCH_V2,		FPU_NONE),
+  ARM_ARCH_OPT ("armv2a",	  ARM_ARCH_V2S,		FPU_NONE),
+  ARM_ARCH_OPT ("armv2s",	  ARM_ARCH_V2S,		FPU_NONE),
+  ARM_ARCH_OPT ("armv3",	  ARM_ARCH_V3,		FPU_NONE),
+  ARM_ARCH_OPT ("armv3m",	  ARM_ARCH_V3M,		FPU_NONE),
+  ARM_ARCH_OPT ("armv4",	  ARM_ARCH_V4,		FPU_NONE),
+  ARM_ARCH_OPT ("armv4xm",	  ARM_ARCH_V4xM,	FPU_NONE),
+  ARM_ARCH_OPT ("armv4t",	  ARM_ARCH_V4T,		FPU_NONE),
+  ARM_ARCH_OPT ("armv4txm",	  ARM_ARCH_V4TxM,	FPU_NONE),
   ARM_ARCH_OPT ("armv5",	  ARM_ARCH_V5,		FPU_ARCH_SOFTVFP),
   ARM_ARCH_OPT ("armv5t",	  ARM_ARCH_V5T,		FPU_ARCH_SOFTVFP),
   ARM_ARCH_OPT ("armv5txm",	  ARM_ARCH_V5TxM,	FPU_ARCH_SOFTVFP),

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 07/11] arm: remove options to select the FPA
  2024-06-03 11:49 [PATCH 00/11] arm: Remove FPA support from gas/binutils Richard Earnshaw
                   ` (5 preceding siblings ...)
  2024-06-03 11:49 ` [PATCH 06/11] arm: change default FPUs from FPA to none Richard Earnshaw
@ 2024-06-03 11:49 ` Richard Earnshaw
  2024-06-03 11:49 ` [PATCH 08/11] arm: remove FPA instructions from assembler Richard Earnshaw
                   ` (3 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Richard Earnshaw @ 2024-06-03 11:49 UTC (permalink / raw)
  To: binutils; +Cc: nickc, Richard Earnshaw

[-- Attachment #1: Type: text/plain, Size: 329 bytes --]


Remove the command-line options to choose the FPA (or FPE - an
emulated FPA).  From this point on it should be impossible to assemble
the old FPA instructions.
---
 gas/config/tc-arm.c  | 16 +---------------
 gas/doc/c-arm.texi   |  9 +--------
 include/opcode/arm.h |  3 ---
 3 files changed, 2 insertions(+), 26 deletions(-)


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0007-arm-remove-options-to-select-the-FPA.patch --]
[-- Type: text/x-patch; name="0007-arm-remove-options-to-select-the-FPA.patch", Size: 2974 bytes --]

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 12610fd8766..73d9f8e1bc6 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -31215,14 +31215,7 @@ const struct arm_legacy_option_table arm_legacy_opts[] =
   {"marmv5t",	 &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
   {"mv5e",	 &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
   {"marmv5e",	 &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
-
-  /* Floating point variants -- don't add any more to this list either.	 */
-  {"mfpe-old",   &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
-  {"mfpa10",     &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
-  {"mfpa11",     &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
-  {"mno-fpu",    &legacy_fpu, ARM_ARCH_NONE,
-   N_("use either -mfpu=softfpa or -mfpu=softvfp")},
-
+  {"mno-fpu",    &legacy_fpu, ARM_ARCH_NONE, N_("use -mfpu=softvfp")},
   {NULL, NULL, ARM_ARCH_NONE, NULL}
 };
 
@@ -32187,13 +32180,6 @@ struct arm_option_fpu_value_table
 static const struct arm_option_fpu_value_table arm_fpus[] =
 {
   {"softfpa",		FPU_NONE},
-  {"fpe",		FPU_ARCH_FPE},
-  {"fpe2",		FPU_ARCH_FPE},
-  {"fpe3",		FPU_ARCH_FPA},	/* Third release supports LFM/SFM.  */
-  {"fpa",		FPU_ARCH_FPA},
-  {"fpa10",		FPU_ARCH_FPA},
-  {"fpa11",		FPU_ARCH_FPA},
-  {"arm7500fe",		FPU_ARCH_FPA},
   {"softvfp",		FPU_ARCH_SOFTVFP},
   {"softvfp+vfp",	FPU_ARCH_VFP_V2},
   {"vfp",		FPU_ARCH_VFP_V2},
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 067ed4d70e4..6d98c62949c 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -492,13 +492,6 @@ This option specifies the floating point format to assemble for.  The
 assembler will issue an error message if an attempt is made to assemble
 an instruction which will not execute on the target floating point unit.
 The following format options are recognized:
-@code{softfpa},
-@code{fpe},
-@code{fpe2},
-@code{fpe3},
-@code{fpa},
-@code{fpa10},
-@code{fpa11},
 @code{arm7500fe},
 @code{softvfp},
 @code{softvfp+vfp},
@@ -539,7 +532,7 @@ when assembling little-endian code.
 
 The default is dependent on the processor selected.  For Architecture 5 or
 later, the default is to assemble for VFP instructions; for earlier
-architectures the default is to assemble for FPA instructions.
+architectures the default is to assemble for no floating point.
 
 @cindex @code{-mfp16-format=} command-line option
 @item -mfp16-format=@var{format}
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index c921f76ec7d..ddc199ecbb8 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -249,9 +249,6 @@
 /* Deprecated.  */
 #define FPU_ARCH_SOFTVFP	ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
 
-#define FPU_ARCH_FPE		ARM_FEATURE_COPROC (FPU_FPA_EXT_V1)
-#define FPU_ARCH_FPA		ARM_FEATURE_COPROC (FPU_FPA)
-
 #define FPU_ARCH_VFP_V1xD	ARM_FEATURE_COPROC (FPU_VFP_V1xD)
 #define FPU_ARCH_VFP_V1		ARM_FEATURE_COPROC (FPU_VFP_V1)
 #define FPU_ARCH_VFP_V2		ARM_FEATURE_COPROC (FPU_VFP_V2)

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 08/11] arm: remove FPA instructions from assembler
  2024-06-03 11:49 [PATCH 00/11] arm: Remove FPA support from gas/binutils Richard Earnshaw
                   ` (6 preceding siblings ...)
  2024-06-03 11:49 ` [PATCH 07/11] arm: remove options to select the FPA Richard Earnshaw
@ 2024-06-03 11:49 ` Richard Earnshaw
  2024-06-03 11:49 ` [PATCH 09/11] arm: remove disassembly support for the FPA co-processor Richard Earnshaw
                   ` (2 subsequent siblings)
  10 siblings, 0 replies; 14+ messages in thread
From: Richard Earnshaw @ 2024-06-03 11:49 UTC (permalink / raw)
  To: binutils; +Cc: nickc, Richard Earnshaw

[-- Attachment #1: Type: text/plain, Size: 242 bytes --]


These can no-longer be generated as the options to reach them have now
gone.  So remove the parsing support for FPA instructions.
---
 gas/config/tc-arm.c | 699 --------------------------------------------
 1 file changed, 699 deletions(-)


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0008-arm-remove-FPA-instructions-from-assembler.patch --]
[-- Type: text/x-patch; name="0008-arm-remove-FPA-instructions-from-assembler.patch", Size: 33201 bytes --]

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 73d9f8e1bc6..becaecd717f 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -311,10 +311,6 @@ static const arm_feature_set arm_cext_iwmmxt =
   ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT);
 static const arm_feature_set arm_cext_xscale =
   ARM_FEATURE_COPROC (ARM_CEXT_XSCALE);
-static const arm_feature_set fpu_fpa_ext_v1 =
-  ARM_FEATURE_COPROC (FPU_FPA_EXT_V1);
-static const arm_feature_set fpu_fpa_ext_v2 =
-  ARM_FEATURE_COPROC (FPU_FPA_EXT_V2);
 static const arm_feature_set fpu_vfp_ext_v1xd =
   ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD);
 static const arm_feature_set fpu_vfp_ext_v1 =
@@ -706,7 +702,6 @@ const char * const reg_expected_msgs[] =
   [REG_TYPE_RN]	    = N_("ARM register expected"),
   [REG_TYPE_CP]	    = N_("bad or missing co-processor number"),
   [REG_TYPE_CN]	    = N_("co-processor register expected"),
-  [REG_TYPE_FN]	    = N_("FPA register expected"),
   [REG_TYPE_VFS]    = N_("VFP single precision register expected"),
   [REG_TYPE_VFD]    = N_("VFP/Neon double precision register expected"),
   [REG_TYPE_NQ]	    = N_("Neon quad precision register expected"),
@@ -4412,55 +4407,6 @@ parse_dot_save (char **str_p, int prev_reg)
     as_bad (BAD_SYNTAX);
 }
 
-/* Parse a directive saving FPA registers.  */
-
-static void
-s_arm_unwind_save_fpa (int reg)
-{
-  expressionS exp;
-  int num_regs;
-  valueT op;
-
-  /* Get Number of registers to transfer.  */
-  if (skip_past_comma (&input_line_pointer) != FAIL)
-    expression (&exp);
-  else
-    exp.X_op = O_illegal;
-
-  if (exp.X_op != O_constant)
-    {
-      as_bad (_("expected , <constant>"));
-      ignore_rest_of_line ();
-      return;
-    }
-
-  num_regs = exp.X_add_number;
-
-  if (num_regs < 1 || num_regs > 4)
-    {
-      as_bad (_("number of registers must be in the range [1:4]"));
-      ignore_rest_of_line ();
-      return;
-    }
-
-  demand_empty_rest_of_line ();
-
-  if (reg == 4)
-    {
-      /* Short form.  */
-      op = 0xb4 | (num_regs - 1);
-      add_unwind_opcode (op, 1);
-    }
-  else
-    {
-      /* Long form.  */
-      op = 0xc800 | (reg << 4) | (num_regs - 1);
-      add_unwind_opcode (op, 2);
-    }
-  unwind.frame_size += num_regs * 12;
-}
-
-
 /* Parse a directive saving VFP registers for ARMv6 and above.  */
 
 static void
@@ -4785,17 +4731,6 @@ s_arm_unwind_save (int arch_v6)
 
   switch (reg->type)
     {
-    case REG_TYPE_FN:
-      if (had_brace)
-	{
-	  as_bad (_("FPA .unwind_save does not take a register list"));
-	  ignore_rest_of_line ();
-	  return;
-	}
-      input_line_pointer = peek;
-      s_arm_unwind_save_fpa (reg->number);
-      return;
-
     case REG_TYPE_PSEUDO:
     case REG_TYPE_RN:
       {
@@ -5352,99 +5287,6 @@ parse_big_immediate (char **str, int i, expressionS *in_exp,
   return SUCCESS;
 }
 
-/* Returns the pseudo-register number of an FPA immediate constant,
-   or FAIL if there isn't a valid constant here.  */
-
-static int
-parse_fpa_immediate (char ** str)
-{
-  LITTLENUM_TYPE words[MAX_LITTLENUMS];
-  char *	 save_in;
-  expressionS	 exp;
-  int		 i;
-  int		 j;
-
-  /* First try and match exact strings, this is to guarantee
-     that some formats will work even for cross assembly.  */
-
-  for (i = 0; fp_const[i]; i++)
-    {
-      if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
-	{
-	  char *start = *str;
-
-	  *str += strlen (fp_const[i]);
-	  if (is_end_of_line[(unsigned char) **str])
-	    return i + 8;
-	  *str = start;
-	}
-    }
-
-  /* Just because we didn't get a match doesn't mean that the constant
-     isn't valid, just that it is in a format that we don't
-     automatically recognize.  Try parsing it with the standard
-     expression routines.  */
-
-  memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
-
-  /* Look for a raw floating point number.  */
-  if ((save_in = atof_ieee (*str, 'x', words)) != NULL
-      && is_end_of_line[(unsigned char) *save_in])
-    {
-      for (i = 0; i < NUM_FLOAT_VALS; i++)
-	{
-	  for (j = 0; j < MAX_LITTLENUMS; j++)
-	    {
-	      if (words[j] != fp_values[i][j])
-		break;
-	    }
-
-	  if (j == MAX_LITTLENUMS)
-	    {
-	      *str = save_in;
-	      return i + 8;
-	    }
-	}
-    }
-
-  /* Try and parse a more complex expression, this will probably fail
-     unless the code uses a floating point prefix (eg "0f").  */
-  save_in = input_line_pointer;
-  input_line_pointer = *str;
-  if (expression (&exp) == absolute_section
-      && exp.X_op == O_big
-      && exp.X_add_number < 0)
-    {
-      /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
-	 Ditto for 15.	*/
-#define X_PRECISION 5
-#define E_PRECISION 15L
-      if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0)
-	{
-	  for (i = 0; i < NUM_FLOAT_VALS; i++)
-	    {
-	      for (j = 0; j < MAX_LITTLENUMS; j++)
-		{
-		  if (words[j] != fp_values[i][j])
-		    break;
-		}
-
-	      if (j == MAX_LITTLENUMS)
-		{
-		  *str = input_line_pointer;
-		  input_line_pointer = save_in;
-		  return i + 8;
-		}
-	    }
-	}
-    }
-
-  *str = input_line_pointer;
-  input_line_pointer = save_in;
-  inst.error = _("invalid FPA immediate expression");
-  return FAIL;
-}
-
 /* Returns 1 if a number has "quarter-precision" float format
    0baBbbbbbc defgh000 00000000 00000000.  */
 
@@ -7150,7 +6992,6 @@ enum operand_parse_code
   OP_RRw,	/* ARM register, not r15, optional trailing ! */
   OP_RCP,	/* Coprocessor number */
   OP_RCN,	/* Coprocessor register */
-  OP_RF,	/* FPA register */
   OP_RVS,	/* VFP single precision register */
   OP_RVD,	/* VFP double precision register (0..15) */
   OP_RND,       /* Neon double precision register (0..31) */
@@ -7284,7 +7125,6 @@ enum operand_parse_code
   OP_RRnpc_I0,	/* ARM register or literal 0 */
   OP_RR_EXr,	/* ARM register or expression with opt. reloc stuff. */
   OP_RR_EXi,	/* ARM register or expression with imm prefix */
-  OP_RF_IF,	/* FPA register or immediate */
   OP_RIWR_RIWC, /* iWMMXt R or C reg */
   OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
 
@@ -7504,7 +7344,6 @@ parse_operands (char *str, const unsigned int *pattern, bool thumb)
 	case OP_RR:    po_reg_or_fail (REG_TYPE_RN);	  break;
 	case OP_RCP:   po_reg_or_fail (REG_TYPE_CP);	  break;
 	case OP_RCN:   po_reg_or_fail (REG_TYPE_CN);	  break;
-	case OP_RF:    po_reg_or_fail (REG_TYPE_FN);	  break;
 	case OP_RVS:   po_reg_or_fail (REG_TYPE_VFS);	  break;
 	case OP_RVD:   po_reg_or_fail (REG_TYPE_VFD);	  break;
 	case OP_oRND:
@@ -7874,20 +7713,6 @@ parse_operands (char *str, const unsigned int *pattern, bool thumb)
 	case OP_RRnpcsp_I32: po_reg_or_goto (REG_TYPE_RN, I32);	break;
 	I32:		     po_imm_or_fail (1, 32, false);	break;
 
-	case OP_RF_IF:    po_reg_or_goto (REG_TYPE_FN, IF);   break;
-	IF:
-	  if (!is_immediate_prefix (*str))
-	    goto bad_args;
-	  str++;
-	  val = parse_fpa_immediate (&str);
-	  if (val == FAIL)
-	    goto failure;
-	  /* FPA immediates are encoded as registers 8-15.
-	     parse_fpa_immediate has already applied the offset.  */
-	  inst.operands[i].reg = val;
-	  inst.operands[i].isreg = 1;
-	  break;
-
 	case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
 	I32z:		  po_imm_or_fail (0, 32, false);	  break;
 
@@ -9350,13 +9175,6 @@ do_imm0 (void)
   inst.instruction |= inst.operands[0].imm;
 }
 
-static void
-do_rd_cpaddr (void)
-{
-  inst.instruction |= inst.operands[0].reg << 12;
-  encode_arm_cp_address (1, true, true, 0);
-}
-
 /* ARM instructions, in alphabetical order by function name (except
    that wrapper functions appear immediately after the function they
    wrap).  */
@@ -11063,54 +10881,6 @@ do_vfp_dp_conv_32 (void)
   vfp_conv (32);
 }
 \f
-/* FPA instructions.  Also in a logical order.	*/
-
-static void
-do_fpa_cmp (void)
-{
-  inst.instruction |= inst.operands[0].reg << 16;
-  inst.instruction |= inst.operands[1].reg;
-}
-
-static void
-do_fpa_ldmstm (void)
-{
-  inst.instruction |= inst.operands[0].reg << 12;
-  switch (inst.operands[1].imm)
-    {
-    case 1: inst.instruction |= CP_T_X;		 break;
-    case 2: inst.instruction |= CP_T_Y;		 break;
-    case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
-    case 4:					 break;
-    default: abort ();
-    }
-
-  if (inst.instruction & (PRE_INDEX | INDEX_UP))
-    {
-      /* The instruction specified "ea" or "fd", so we can only accept
-	 [Rn]{!}.  The instruction does not really support stacking or
-	 unstacking, so we have to emulate these by setting appropriate
-	 bits and offsets.  */
-      constraint (inst.relocs[0].exp.X_op != O_constant
-		  || inst.relocs[0].exp.X_add_number != 0,
-		  _("this instruction does not support indexing"));
-
-      if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
-	inst.relocs[0].exp.X_add_number = 12 * inst.operands[1].imm;
-
-      if (!(inst.instruction & INDEX_UP))
-	inst.relocs[0].exp.X_add_number = -inst.relocs[0].exp.X_add_number;
-
-      if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
-	{
-	  inst.operands[2].preind = 0;
-	  inst.operands[2].postind = 1;
-	}
-    }
-
-  encode_arm_cp_address (2, true, true, 0);
-}
-\f
 /* iWMMXt instructions: strictly in alphabetical order.	 */
 
 static void
@@ -23925,13 +23695,6 @@ static const struct reg_entry reg_names[] =
   REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
   REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
 
-  /* FPA registers.  */
-  REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
-  REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
-
-  REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
-  REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
-
   /* VFP SP registers.	*/
   REGSET(s,VFS),  REGSET(S,VFS),
   REGSETH(s,VFS), REGSETH(S,VFS),
@@ -24308,19 +24071,6 @@ static struct asm_barrier_opt barrier_opt_names[] =
 #define mcCE(mnem,  op, nops, ops, ae)	\
   { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
 
-/* Legacy coprocessor instructions where conditional infix and conditional
-   suffix are ambiguous.  For consistency this includes all FPA instructions,
-   not just the potentially ambiguous ones.  */
-#define cCL(mnem, op, nops, ops, ae)	\
-  { mnem, OPS##nops ops, OT_cinfix3_legacy, \
-    0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
-
-/* Coprocessor, takes either a suffix or a position-3 infix
-   (for an FPA corner case). */
-#define C3E(mnem, op, nops, ops, ae) \
-  { mnem, OPS##nops ops, OT_csuf_or_in3, \
-    0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
-
 #define xCM_(m1, m2, m3, op, nops, ops, ae)	\
   { m1 #m2 m3, OPS##nops ops, \
     sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
@@ -25136,451 +24886,6 @@ static const struct asm_opcode insns[] =
  NUF (vsdot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_s),
  NUF (vudot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_u),
 
-#undef  ARM_VARIANT
-#define ARM_VARIANT  & fpu_fpa_ext_v1  /* Core FPA instruction set (V1).  */
-#undef  THUMB_VARIANT
-#define THUMB_VARIANT NULL
-
- cCE("wfs",	e200110, 1, (RR),	     rd),
- cCE("rfs",	e300110, 1, (RR),	     rd),
- cCE("wfc",	e400110, 1, (RR),	     rd),
- cCE("rfc",	e500110, 1, (RR),	     rd),
-
- cCL("ldfs",	c100100, 2, (RF, ADDRGLDC),  rd_cpaddr),
- cCL("ldfd",	c108100, 2, (RF, ADDRGLDC),  rd_cpaddr),
- cCL("ldfe",	c500100, 2, (RF, ADDRGLDC),  rd_cpaddr),
- cCL("ldfp",	c508100, 2, (RF, ADDRGLDC),  rd_cpaddr),
-
- cCL("stfs",	c000100, 2, (RF, ADDRGLDC),  rd_cpaddr),
- cCL("stfd",	c008100, 2, (RF, ADDRGLDC),  rd_cpaddr),
- cCL("stfe",	c400100, 2, (RF, ADDRGLDC),  rd_cpaddr),
- cCL("stfp",	c408100, 2, (RF, ADDRGLDC),  rd_cpaddr),
-
- cCL("mvfs",	e008100, 2, (RF, RF_IF),     rd_rm),
- cCL("mvfsp",	e008120, 2, (RF, RF_IF),     rd_rm),
- cCL("mvfsm",	e008140, 2, (RF, RF_IF),     rd_rm),
- cCL("mvfsz",	e008160, 2, (RF, RF_IF),     rd_rm),
- cCL("mvfd",	e008180, 2, (RF, RF_IF),     rd_rm),
- cCL("mvfdp",	e0081a0, 2, (RF, RF_IF),     rd_rm),
- cCL("mvfdm",	e0081c0, 2, (RF, RF_IF),     rd_rm),
- cCL("mvfdz",	e0081e0, 2, (RF, RF_IF),     rd_rm),
- cCL("mvfe",	e088100, 2, (RF, RF_IF),     rd_rm),
- cCL("mvfep",	e088120, 2, (RF, RF_IF),     rd_rm),
- cCL("mvfem",	e088140, 2, (RF, RF_IF),     rd_rm),
- cCL("mvfez",	e088160, 2, (RF, RF_IF),     rd_rm),
-
- cCL("mnfs",	e108100, 2, (RF, RF_IF),     rd_rm),
- cCL("mnfsp",	e108120, 2, (RF, RF_IF),     rd_rm),
- cCL("mnfsm",	e108140, 2, (RF, RF_IF),     rd_rm),
- cCL("mnfsz",	e108160, 2, (RF, RF_IF),     rd_rm),
- cCL("mnfd",	e108180, 2, (RF, RF_IF),     rd_rm),
- cCL("mnfdp",	e1081a0, 2, (RF, RF_IF),     rd_rm),
- cCL("mnfdm",	e1081c0, 2, (RF, RF_IF),     rd_rm),
- cCL("mnfdz",	e1081e0, 2, (RF, RF_IF),     rd_rm),
- cCL("mnfe",	e188100, 2, (RF, RF_IF),     rd_rm),
- cCL("mnfep",	e188120, 2, (RF, RF_IF),     rd_rm),
- cCL("mnfem",	e188140, 2, (RF, RF_IF),     rd_rm),
- cCL("mnfez",	e188160, 2, (RF, RF_IF),     rd_rm),
-
- cCL("abss",	e208100, 2, (RF, RF_IF),     rd_rm),
- cCL("abssp",	e208120, 2, (RF, RF_IF),     rd_rm),
- cCL("abssm",	e208140, 2, (RF, RF_IF),     rd_rm),
- cCL("abssz",	e208160, 2, (RF, RF_IF),     rd_rm),
- cCL("absd",	e208180, 2, (RF, RF_IF),     rd_rm),
- cCL("absdp",	e2081a0, 2, (RF, RF_IF),     rd_rm),
- cCL("absdm",	e2081c0, 2, (RF, RF_IF),     rd_rm),
- cCL("absdz",	e2081e0, 2, (RF, RF_IF),     rd_rm),
- cCL("abse",	e288100, 2, (RF, RF_IF),     rd_rm),
- cCL("absep",	e288120, 2, (RF, RF_IF),     rd_rm),
- cCL("absem",	e288140, 2, (RF, RF_IF),     rd_rm),
- cCL("absez",	e288160, 2, (RF, RF_IF),     rd_rm),
-
- cCL("rnds",	e308100, 2, (RF, RF_IF),     rd_rm),
- cCL("rndsp",	e308120, 2, (RF, RF_IF),     rd_rm),
- cCL("rndsm",	e308140, 2, (RF, RF_IF),     rd_rm),
- cCL("rndsz",	e308160, 2, (RF, RF_IF),     rd_rm),
- cCL("rndd",	e308180, 2, (RF, RF_IF),     rd_rm),
- cCL("rnddp",	e3081a0, 2, (RF, RF_IF),     rd_rm),
- cCL("rnddm",	e3081c0, 2, (RF, RF_IF),     rd_rm),
- cCL("rnddz",	e3081e0, 2, (RF, RF_IF),     rd_rm),
- cCL("rnde",	e388100, 2, (RF, RF_IF),     rd_rm),
- cCL("rndep",	e388120, 2, (RF, RF_IF),     rd_rm),
- cCL("rndem",	e388140, 2, (RF, RF_IF),     rd_rm),
- cCL("rndez",	e388160, 2, (RF, RF_IF),     rd_rm),
-
- cCL("sqts",	e408100, 2, (RF, RF_IF),     rd_rm),
- cCL("sqtsp",	e408120, 2, (RF, RF_IF),     rd_rm),
- cCL("sqtsm",	e408140, 2, (RF, RF_IF),     rd_rm),
- cCL("sqtsz",	e408160, 2, (RF, RF_IF),     rd_rm),
- cCL("sqtd",	e408180, 2, (RF, RF_IF),     rd_rm),
- cCL("sqtdp",	e4081a0, 2, (RF, RF_IF),     rd_rm),
- cCL("sqtdm",	e4081c0, 2, (RF, RF_IF),     rd_rm),
- cCL("sqtdz",	e4081e0, 2, (RF, RF_IF),     rd_rm),
- cCL("sqte",	e488100, 2, (RF, RF_IF),     rd_rm),
- cCL("sqtep",	e488120, 2, (RF, RF_IF),     rd_rm),
- cCL("sqtem",	e488140, 2, (RF, RF_IF),     rd_rm),
- cCL("sqtez",	e488160, 2, (RF, RF_IF),     rd_rm),
-
- cCL("logs",	e508100, 2, (RF, RF_IF),     rd_rm),
- cCL("logsp",	e508120, 2, (RF, RF_IF),     rd_rm),
- cCL("logsm",	e508140, 2, (RF, RF_IF),     rd_rm),
- cCL("logsz",	e508160, 2, (RF, RF_IF),     rd_rm),
- cCL("logd",	e508180, 2, (RF, RF_IF),     rd_rm),
- cCL("logdp",	e5081a0, 2, (RF, RF_IF),     rd_rm),
- cCL("logdm",	e5081c0, 2, (RF, RF_IF),     rd_rm),
- cCL("logdz",	e5081e0, 2, (RF, RF_IF),     rd_rm),
- cCL("loge",	e588100, 2, (RF, RF_IF),     rd_rm),
- cCL("logep",	e588120, 2, (RF, RF_IF),     rd_rm),
- cCL("logem",	e588140, 2, (RF, RF_IF),     rd_rm),
- cCL("logez",	e588160, 2, (RF, RF_IF),     rd_rm),
-
- cCL("lgns",	e608100, 2, (RF, RF_IF),     rd_rm),
- cCL("lgnsp",	e608120, 2, (RF, RF_IF),     rd_rm),
- cCL("lgnsm",	e608140, 2, (RF, RF_IF),     rd_rm),
- cCL("lgnsz",	e608160, 2, (RF, RF_IF),     rd_rm),
- cCL("lgnd",	e608180, 2, (RF, RF_IF),     rd_rm),
- cCL("lgndp",	e6081a0, 2, (RF, RF_IF),     rd_rm),
- cCL("lgndm",	e6081c0, 2, (RF, RF_IF),     rd_rm),
- cCL("lgndz",	e6081e0, 2, (RF, RF_IF),     rd_rm),
- cCL("lgne",	e688100, 2, (RF, RF_IF),     rd_rm),
- cCL("lgnep",	e688120, 2, (RF, RF_IF),     rd_rm),
- cCL("lgnem",	e688140, 2, (RF, RF_IF),     rd_rm),
- cCL("lgnez",	e688160, 2, (RF, RF_IF),     rd_rm),
-
- cCL("exps",	e708100, 2, (RF, RF_IF),     rd_rm),
- cCL("expsp",	e708120, 2, (RF, RF_IF),     rd_rm),
- cCL("expsm",	e708140, 2, (RF, RF_IF),     rd_rm),
- cCL("expsz",	e708160, 2, (RF, RF_IF),     rd_rm),
- cCL("expd",	e708180, 2, (RF, RF_IF),     rd_rm),
- cCL("expdp",	e7081a0, 2, (RF, RF_IF),     rd_rm),
- cCL("expdm",	e7081c0, 2, (RF, RF_IF),     rd_rm),
- cCL("expdz",	e7081e0, 2, (RF, RF_IF),     rd_rm),
- cCL("expe",	e788100, 2, (RF, RF_IF),     rd_rm),
- cCL("expep",	e788120, 2, (RF, RF_IF),     rd_rm),
- cCL("expem",	e788140, 2, (RF, RF_IF),     rd_rm),
- cCL("expdz",	e788160, 2, (RF, RF_IF),     rd_rm),
-
- cCL("sins",	e808100, 2, (RF, RF_IF),     rd_rm),
- cCL("sinsp",	e808120, 2, (RF, RF_IF),     rd_rm),
- cCL("sinsm",	e808140, 2, (RF, RF_IF),     rd_rm),
- cCL("sinsz",	e808160, 2, (RF, RF_IF),     rd_rm),
- cCL("sind",	e808180, 2, (RF, RF_IF),     rd_rm),
- cCL("sindp",	e8081a0, 2, (RF, RF_IF),     rd_rm),
- cCL("sindm",	e8081c0, 2, (RF, RF_IF),     rd_rm),
- cCL("sindz",	e8081e0, 2, (RF, RF_IF),     rd_rm),
- cCL("sine",	e888100, 2, (RF, RF_IF),     rd_rm),
- cCL("sinep",	e888120, 2, (RF, RF_IF),     rd_rm),
- cCL("sinem",	e888140, 2, (RF, RF_IF),     rd_rm),
- cCL("sinez",	e888160, 2, (RF, RF_IF),     rd_rm),
-
- cCL("coss",	e908100, 2, (RF, RF_IF),     rd_rm),
- cCL("cossp",	e908120, 2, (RF, RF_IF),     rd_rm),
- cCL("cossm",	e908140, 2, (RF, RF_IF),     rd_rm),
- cCL("cossz",	e908160, 2, (RF, RF_IF),     rd_rm),
- cCL("cosd",	e908180, 2, (RF, RF_IF),     rd_rm),
- cCL("cosdp",	e9081a0, 2, (RF, RF_IF),     rd_rm),
- cCL("cosdm",	e9081c0, 2, (RF, RF_IF),     rd_rm),
- cCL("cosdz",	e9081e0, 2, (RF, RF_IF),     rd_rm),
- cCL("cose",	e988100, 2, (RF, RF_IF),     rd_rm),
- cCL("cosep",	e988120, 2, (RF, RF_IF),     rd_rm),
- cCL("cosem",	e988140, 2, (RF, RF_IF),     rd_rm),
- cCL("cosez",	e988160, 2, (RF, RF_IF),     rd_rm),
-
- cCL("tans",	ea08100, 2, (RF, RF_IF),     rd_rm),
- cCL("tansp",	ea08120, 2, (RF, RF_IF),     rd_rm),
- cCL("tansm",	ea08140, 2, (RF, RF_IF),     rd_rm),
- cCL("tansz",	ea08160, 2, (RF, RF_IF),     rd_rm),
- cCL("tand",	ea08180, 2, (RF, RF_IF),     rd_rm),
- cCL("tandp",	ea081a0, 2, (RF, RF_IF),     rd_rm),
- cCL("tandm",	ea081c0, 2, (RF, RF_IF),     rd_rm),
- cCL("tandz",	ea081e0, 2, (RF, RF_IF),     rd_rm),
- cCL("tane",	ea88100, 2, (RF, RF_IF),     rd_rm),
- cCL("tanep",	ea88120, 2, (RF, RF_IF),     rd_rm),
- cCL("tanem",	ea88140, 2, (RF, RF_IF),     rd_rm),
- cCL("tanez",	ea88160, 2, (RF, RF_IF),     rd_rm),
-
- cCL("asns",	eb08100, 2, (RF, RF_IF),     rd_rm),
- cCL("asnsp",	eb08120, 2, (RF, RF_IF),     rd_rm),
- cCL("asnsm",	eb08140, 2, (RF, RF_IF),     rd_rm),
- cCL("asnsz",	eb08160, 2, (RF, RF_IF),     rd_rm),
- cCL("asnd",	eb08180, 2, (RF, RF_IF),     rd_rm),
- cCL("asndp",	eb081a0, 2, (RF, RF_IF),     rd_rm),
- cCL("asndm",	eb081c0, 2, (RF, RF_IF),     rd_rm),
- cCL("asndz",	eb081e0, 2, (RF, RF_IF),     rd_rm),
- cCL("asne",	eb88100, 2, (RF, RF_IF),     rd_rm),
- cCL("asnep",	eb88120, 2, (RF, RF_IF),     rd_rm),
- cCL("asnem",	eb88140, 2, (RF, RF_IF),     rd_rm),
- cCL("asnez",	eb88160, 2, (RF, RF_IF),     rd_rm),
-
- cCL("acss",	ec08100, 2, (RF, RF_IF),     rd_rm),
- cCL("acssp",	ec08120, 2, (RF, RF_IF),     rd_rm),
- cCL("acssm",	ec08140, 2, (RF, RF_IF),     rd_rm),
- cCL("acssz",	ec08160, 2, (RF, RF_IF),     rd_rm),
- cCL("acsd",	ec08180, 2, (RF, RF_IF),     rd_rm),
- cCL("acsdp",	ec081a0, 2, (RF, RF_IF),     rd_rm),
- cCL("acsdm",	ec081c0, 2, (RF, RF_IF),     rd_rm),
- cCL("acsdz",	ec081e0, 2, (RF, RF_IF),     rd_rm),
- cCL("acse",	ec88100, 2, (RF, RF_IF),     rd_rm),
- cCL("acsep",	ec88120, 2, (RF, RF_IF),     rd_rm),
- cCL("acsem",	ec88140, 2, (RF, RF_IF),     rd_rm),
- cCL("acsez",	ec88160, 2, (RF, RF_IF),     rd_rm),
-
- cCL("atns",	ed08100, 2, (RF, RF_IF),     rd_rm),
- cCL("atnsp",	ed08120, 2, (RF, RF_IF),     rd_rm),
- cCL("atnsm",	ed08140, 2, (RF, RF_IF),     rd_rm),
- cCL("atnsz",	ed08160, 2, (RF, RF_IF),     rd_rm),
- cCL("atnd",	ed08180, 2, (RF, RF_IF),     rd_rm),
- cCL("atndp",	ed081a0, 2, (RF, RF_IF),     rd_rm),
- cCL("atndm",	ed081c0, 2, (RF, RF_IF),     rd_rm),
- cCL("atndz",	ed081e0, 2, (RF, RF_IF),     rd_rm),
- cCL("atne",	ed88100, 2, (RF, RF_IF),     rd_rm),
- cCL("atnep",	ed88120, 2, (RF, RF_IF),     rd_rm),
- cCL("atnem",	ed88140, 2, (RF, RF_IF),     rd_rm),
- cCL("atnez",	ed88160, 2, (RF, RF_IF),     rd_rm),
-
- cCL("urds",	ee08100, 2, (RF, RF_IF),     rd_rm),
- cCL("urdsp",	ee08120, 2, (RF, RF_IF),     rd_rm),
- cCL("urdsm",	ee08140, 2, (RF, RF_IF),     rd_rm),
- cCL("urdsz",	ee08160, 2, (RF, RF_IF),     rd_rm),
- cCL("urdd",	ee08180, 2, (RF, RF_IF),     rd_rm),
- cCL("urddp",	ee081a0, 2, (RF, RF_IF),     rd_rm),
- cCL("urddm",	ee081c0, 2, (RF, RF_IF),     rd_rm),
- cCL("urddz",	ee081e0, 2, (RF, RF_IF),     rd_rm),
- cCL("urde",	ee88100, 2, (RF, RF_IF),     rd_rm),
- cCL("urdep",	ee88120, 2, (RF, RF_IF),     rd_rm),
- cCL("urdem",	ee88140, 2, (RF, RF_IF),     rd_rm),
- cCL("urdez",	ee88160, 2, (RF, RF_IF),     rd_rm),
-
- cCL("nrms",	ef08100, 2, (RF, RF_IF),     rd_rm),
- cCL("nrmsp",	ef08120, 2, (RF, RF_IF),     rd_rm),
- cCL("nrmsm",	ef08140, 2, (RF, RF_IF),     rd_rm),
- cCL("nrmsz",	ef08160, 2, (RF, RF_IF),     rd_rm),
- cCL("nrmd",	ef08180, 2, (RF, RF_IF),     rd_rm),
- cCL("nrmdp",	ef081a0, 2, (RF, RF_IF),     rd_rm),
- cCL("nrmdm",	ef081c0, 2, (RF, RF_IF),     rd_rm),
- cCL("nrmdz",	ef081e0, 2, (RF, RF_IF),     rd_rm),
- cCL("nrme",	ef88100, 2, (RF, RF_IF),     rd_rm),
- cCL("nrmep",	ef88120, 2, (RF, RF_IF),     rd_rm),
- cCL("nrmem",	ef88140, 2, (RF, RF_IF),     rd_rm),
- cCL("nrmez",	ef88160, 2, (RF, RF_IF),     rd_rm),
-
- cCL("adfs",	e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("adfsp",	e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("adfsm",	e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("adfsz",	e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("adfd",	e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("adfdp",	e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("adfdm",	e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("adfdz",	e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("adfe",	e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("adfep",	e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("adfem",	e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("adfez",	e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- cCL("sufs",	e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("sufsp",	e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("sufsm",	e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("sufsz",	e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("sufd",	e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("sufdp",	e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("sufdm",	e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("sufdz",	e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("sufe",	e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("sufep",	e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("sufem",	e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("sufez",	e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- cCL("rsfs",	e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rsfsp",	e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rsfsm",	e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rsfsz",	e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rsfd",	e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rsfdp",	e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rsfdm",	e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rsfdz",	e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rsfe",	e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rsfep",	e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rsfem",	e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rsfez",	e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- cCL("mufs",	e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("mufsp",	e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("mufsm",	e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("mufsz",	e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("mufd",	e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("mufdp",	e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("mufdm",	e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("mufdz",	e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("mufe",	e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("mufep",	e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("mufem",	e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("mufez",	e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- cCL("dvfs",	e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("dvfsp",	e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("dvfsm",	e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("dvfsz",	e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("dvfd",	e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("dvfdp",	e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("dvfdm",	e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("dvfdz",	e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("dvfe",	e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("dvfep",	e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("dvfem",	e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("dvfez",	e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- cCL("rdfs",	e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rdfsp",	e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rdfsm",	e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rdfsz",	e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rdfd",	e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rdfdp",	e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rdfdm",	e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rdfdz",	e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rdfe",	e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rdfep",	e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rdfem",	e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rdfez",	e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- cCL("pows",	e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("powsp",	e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("powsm",	e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("powsz",	e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("powd",	e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("powdp",	e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("powdm",	e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("powdz",	e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("powe",	e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("powep",	e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("powem",	e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("powez",	e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- cCL("rpws",	e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rpwsp",	e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rpwsm",	e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rpwsz",	e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rpwd",	e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rpwdp",	e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rpwdm",	e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rpwdz",	e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rpwe",	e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rpwep",	e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rpwem",	e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rpwez",	e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- cCL("rmfs",	e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rmfsp",	e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rmfsm",	e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rmfsz",	e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rmfd",	e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rmfdp",	e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rmfdm",	e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rmfdz",	e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rmfe",	e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rmfep",	e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rmfem",	e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("rmfez",	e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- cCL("fmls",	e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fmlsp",	e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fmlsm",	e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fmlsz",	e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fmld",	e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fmldp",	e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fmldm",	e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fmldz",	e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fmle",	e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fmlep",	e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fmlem",	e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fmlez",	e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- cCL("fdvs",	ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fdvsp",	ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fdvsm",	ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fdvsz",	ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fdvd",	ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fdvdp",	ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fdvdm",	ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fdvdz",	ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fdve",	ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fdvep",	ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fdvem",	ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("fdvez",	ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- cCL("frds",	eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("frdsp",	eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("frdsm",	eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("frdsz",	eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("frdd",	eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("frddp",	eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("frddm",	eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("frddz",	eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("frde",	eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("frdep",	eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("frdem",	eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("frdez",	eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- cCL("pols",	ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("polsp",	ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("polsm",	ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("polsz",	ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("pold",	ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("poldp",	ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("poldm",	ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("poldz",	ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("pole",	ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("polep",	ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("polem",	ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
- cCL("polez",	ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- cCE("cmf",	e90f110, 2, (RF, RF_IF),     fpa_cmp),
- C3E("cmfe",	ed0f110, 2, (RF, RF_IF),     fpa_cmp),
- cCE("cnf",	eb0f110, 2, (RF, RF_IF),     fpa_cmp),
- C3E("cnfe",	ef0f110, 2, (RF, RF_IF),     fpa_cmp),
-
- cCL("flts",	e000110, 2, (RF, RR),	     rn_rd),
- cCL("fltsp",	e000130, 2, (RF, RR),	     rn_rd),
- cCL("fltsm",	e000150, 2, (RF, RR),	     rn_rd),
- cCL("fltsz",	e000170, 2, (RF, RR),	     rn_rd),
- cCL("fltd",	e000190, 2, (RF, RR),	     rn_rd),
- cCL("fltdp",	e0001b0, 2, (RF, RR),	     rn_rd),
- cCL("fltdm",	e0001d0, 2, (RF, RR),	     rn_rd),
- cCL("fltdz",	e0001f0, 2, (RF, RR),	     rn_rd),
- cCL("flte",	e080110, 2, (RF, RR),	     rn_rd),
- cCL("fltep",	e080130, 2, (RF, RR),	     rn_rd),
- cCL("fltem",	e080150, 2, (RF, RR),	     rn_rd),
- cCL("fltez",	e080170, 2, (RF, RR),	     rn_rd),
-
-  /* The implementation of the FIX instruction is broken on some
-     assemblers, in that it accepts a precision specifier as well as a
-     rounding specifier, despite the fact that this is meaningless.
-     To be more compatible, we accept it as well, though of course it
-     does not set any bits.  */
- cCE("fix",	e100110, 2, (RR, RF),	     rd_rm),
- cCL("fixp",	e100130, 2, (RR, RF),	     rd_rm),
- cCL("fixm",	e100150, 2, (RR, RF),	     rd_rm),
- cCL("fixz",	e100170, 2, (RR, RF),	     rd_rm),
- cCL("fixsp",	e100130, 2, (RR, RF),	     rd_rm),
- cCL("fixsm",	e100150, 2, (RR, RF),	     rd_rm),
- cCL("fixsz",	e100170, 2, (RR, RF),	     rd_rm),
- cCL("fixdp",	e100130, 2, (RR, RF),	     rd_rm),
- cCL("fixdm",	e100150, 2, (RR, RF),	     rd_rm),
- cCL("fixdz",	e100170, 2, (RR, RF),	     rd_rm),
- cCL("fixep",	e100130, 2, (RR, RF),	     rd_rm),
- cCL("fixem",	e100150, 2, (RR, RF),	     rd_rm),
- cCL("fixez",	e100170, 2, (RR, RF),	     rd_rm),
-
-  /* Instructions that were new with the real FPA, call them V2.  */
-#undef  ARM_VARIANT
-#define ARM_VARIANT  & fpu_fpa_ext_v2
-
- cCE("lfm",	c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
- cCL("lfmfd",	c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
- cCL("lfmea",	d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
- cCE("sfm",	c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
- cCL("sfmfd",	d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
- cCL("sfmea",	c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
-
 #undef  ARM_VARIANT
 #define ARM_VARIANT  & fpu_vfp_ext_v1xd  /* VFP V1xD (single precision).  */
 #undef THUMB_VARIANT
@@ -26664,8 +25969,6 @@ static const struct asm_opcode insns[] =
 #undef TUF
 #undef TCC
 #undef cCE
-#undef cCL
-#undef C3E
 #undef C3
 #undef CE
 #undef CM
@@ -31014,8 +30317,6 @@ md_begin (void)
 	      -m[arm]v[2345[t[e]]]    Arm architectures
 	      -mall		      All (except the ARM1)
       FP variants:
-	      -mfpa10, -mfpa11	      FPA10 and 11 co-processor instructions
-	      -mfpe-old		      (No float load/store multiples)
 	      -mvfpxd		      VFP Single precision
 	      -mvfp		      All VFP
 	      -mno-fpu		      Disable all floating point instructions

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 09/11] arm: remove disassembly support for the FPA co-processor
  2024-06-03 11:49 [PATCH 00/11] arm: Remove FPA support from gas/binutils Richard Earnshaw
                   ` (7 preceding siblings ...)
  2024-06-03 11:49 ` [PATCH 08/11] arm: remove FPA instructions from assembler Richard Earnshaw
@ 2024-06-03 11:49 ` Richard Earnshaw
  2024-06-03 11:49 ` [PATCH 10/11] arm: minor documentation cleanup given removal of FPA Richard Earnshaw
  2024-06-03 11:49 ` [PATCH 11/11] NEWS: arm: note that FPA support has been removed Richard Earnshaw
  10 siblings, 0 replies; 14+ messages in thread
From: Richard Earnshaw @ 2024-06-03 11:49 UTC (permalink / raw)
  To: binutils; +Cc: nickc, Richard Earnshaw

[-- Attachment #1: Type: text/plain, Size: 503 bytes --]


Remove the FPA support from the disassembler.  This entails a couple
of testsuite fixes where we were (probably incorrectly) disassembling
a generic co-processor instruction using the legacy FPA opcodes.
---
 .../gas/arm/copro-arm_v2plus-arm_v2.d         |   6 +-
 .../arm/copro-thumb_v6t2plus-thumb_v6t2-1.d   |   6 +-
 include/opcode/arm.h                          |   7 +-
 opcodes/arm-dis.c                             | 197 +-----------------
 4 files changed, 10 insertions(+), 206 deletions(-)


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0009-arm-remove-disassembly-support-for-the-FPA-co-proces.patch --]
[-- Type: text/x-patch; name="0009-arm-remove-disassembly-support-for-the-FPA-co-proces.patch", Size: 13771 bytes --]

diff --git a/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d b/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d
index 0d88359d325..9cc6a96c413 100644
--- a/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d
+++ b/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d
@@ -8,10 +8,10 @@
 .*: +file format .*arm.*
 
 Disassembly of section .text:
-0+000 <[^>]*> ee421103 	dvfs	f1, f2, f3
+0+000 <[^>]*> ee421103 	cdp	1, 4, cr1, cr2, cr3, \{0\}
 0+004 <[^>]*> 0e3414a5 	cdpeq	4, 3, cr1, cr4, cr5, \{5\}
 0+008 <[^>]*> ed939500 	ldc	5, cr9, \[r3\]
-0+00c <[^>]*> edd1e108 	ldfp	f6, \[r1, #32\]
+0+00c <[^>]*> edd1e108 	ldcl	1, cr14, \[r1, #32\]
 0+010 <[^>]*> 4db200ff 	ldcmi	0, cr0, \[r2, #1020\]!.*
 0+014 <[^>]*> 5cf31710 	ldclpl	7, cr1, \[r3\], #64.*
 0+018 <[^>]*> ed1f8001 	ldc	0, cr8, \[pc, #-4\]	@ .* <foo>
@@ -19,7 +19,7 @@ Disassembly of section .text:
 0+020 <[^>]*> edc0f302 	stcl	3, cr15, \[r0, #8\]
 0+024 <[^>]*> 0da2c419 	stceq	4, cr12, \[r2, #100\]!	@.*
 0+028 <[^>]*> 3ca4860c 	stccc	6, cr8, \[r4\], #48.*
-0+02c <[^>]*> ed0f7101 	stfs	f7, \[pc, #-4\]	@ .* <bar>
+0+02c <[^>]*> ed0f7101 	stc	1, cr7, \[pc, #-4\]	@ .* <bar>
 0+030 <[^>]*> ee715212 	mrc	2, 3, r5, cr1, cr2, \{0\}
 0+034 <[^>]*> aeb1f4f2 	mrcge	4, 5, APSR_nzcv, cr1, cr2, \{7\}
 0+038 <[^>]*> ee215711 	mcr	7, 1, r5, cr1, cr1, \{0\}
diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d
index 243610fbf95..6e556335773 100644
--- a/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d
+++ b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d
@@ -8,11 +8,11 @@
 .*: +file format .*arm.*
 
 Disassembly of section .text:
-0+000 <[^>]*> ee42 1103 	dvfs	f1, f2, f3
+0+000 <[^>]*> ee42 1103 	cdp	1, 4, cr1, cr2, cr3, \{0\}
 0+004 <[^>]*> [^ ]*      	it	eq
 0+006 <[^>]*> ee34 14a5 	cdpeq	4, 3, cr1, cr4, cr5, \{5\}
 0+00a <[^>]*> ed93 9500 	ldc	5, cr9, \[r3\]
-0+00e <[^>]*> edd1 e108 	ldfp	f6, \[r1, #32\]
+0+00e <[^>]*> edd1 e108 	ldcl	1, cr14, \[r1, #32\]
 0+012 <[^>]*> [^ ]*      	ite	mi
 0+014 <[^>]*> edb2 00ff 	ldcmi	0, cr0, \[r2, #1020\]!.*
 0+018 <[^>]*> ecf3 1710 	ldclpl	7, cr1, \[r3\], #64.*
@@ -23,7 +23,7 @@ Disassembly of section .text:
 0+02a <[^>]*> eda2 c419 	stceq	4, cr12, \[r2, #100\]!	@.*
 0+02e <[^>]*> [^ ]*      	it	cc
 0+030 <[^>]*> eca4 860c 	stccc	6, cr8, \[r4\], #48.*
-0+034 <[^>]*> ed8f 7100 	stfs	f7, \[pc\]	@ .* <bar>
+0+034 <[^>]*> ed8f 7100 	stc	1, cr7, \[pc\]	@ .* <bar>
 0+038 <[^>]*> ee71 5212 	mrc	2, 3, r5, cr1, cr2, \{0\}
 0+03c <[^>]*> [^ ]*      	it	ge
 0+03e <[^>]*> eeb1 f4f2 	mrcge	4, 5, APSR_nzcv, cr1, cr2, \{7\}
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index ddc199ecbb8..a89c215faff 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -105,8 +105,8 @@
 					   coprocessor version 2.	   */
 
 #define FPU_ENDIAN_PURE	     0x80000000	/* Pure-endian doubles.		   */
-#define FPU_FPA_EXT_V1	     0x40000000	/* Base FPA instruction set.	   */
-#define FPU_FPA_EXT_V2	     0x20000000	/* LFM/SFM.			   */
+/* unused		     0x40000000	*/
+/* unused		     0x20000000	*/
 /* unused		     0x10000000	*/
 #define FPU_VFP_EXT_V1xD     0x08000000	/* Base VFP instruction set.	   */
 #define FPU_VFP_EXT_V1	     0x04000000	/* Double-precision insns.	   */
@@ -244,7 +244,6 @@
 					     | FPU_VFP_EXT_V3	   \
 					     | FPU_NEON_EXT_V1	   \
 					     | FPU_VFP_EXT_D32)
-#define FPU_FPA		  (FPU_FPA_EXT_V1    | FPU_FPA_EXT_V2)
 
 /* Deprecated.  */
 #define FPU_ARCH_SOFTVFP	ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
@@ -404,7 +403,7 @@
 #define ARM_ARCH_UNKNOWN	ARM_FEATURE_ALL (-1, -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP), -1, -1)	/* Machine type is unknown.  */
 #define ARM_ANY		ARM_FEATURE_ALL (-1, -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP), -1, 0)	/* Any basic core.  */
 #define FPU_ANY		ARM_FEATURE_COPROC (-1 & ~(ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2)) /* Any FPU.  */
-#define FPU_ANY_HARD	ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD)
+#define FPU_ANY_HARD	ARM_FEATURE_COPROC (FPU_VFP_HARD)
 /* Extensions containing some Thumb-2 instructions.  If any is present, Thumb
    ISA is Thumb-2.  */
 #define ARM_ARCH_THUMB2 ARM_FEATURE_CORE (ARM_EXT_V6T2 | ARM_EXT_V7	\
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index b63faddf6f9..480e4c21655 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -405,16 +405,11 @@ struct opcode16
    %q			print shifter argument
    %u			print condition code (unconditional in ARM mode,
                           UNPREDICTABLE if not AL in Thumb)
-   %A			print address for ldc/stc/ldf/stf instruction
+   %A			print address for ldc/stc instruction
    %B			print vstm/vldm register list
    %C			print vscclrm register list
-   %I                   print cirrus signed shift immediate: bits 0..3|4..6
    %J			print register for VLDR instruction
    %K			print address for VLDR instruction
-   %F			print the COUNT field of a LFM/SFM instruction.
-   %P			print floating point precision in arithmetic insn
-   %Q			print floating point precision in ldf/stf insn
-   %R			print floating point rounding mode
 
    %<bitfield>c		print as a condition code (for vsel)
    %<bitfield>r		print as an ARM register
@@ -424,8 +419,6 @@ struct opcode16
    %<bitfield>k		print immediate for VFPv3 conversion instruction
    %<bitfield>x		print the bitfield in hex
    %<bitfield>X		print the bitfield as 1 hex digit without leading "0x"
-   %<bitfield>f		print a floating point constant if >7 else a
-			floating point register
    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
    %<bitfield>g         print as an iWMMXt 64-bit register
    %<bitfield>G         print as an iWMMXt general purpose or control register
@@ -707,94 +700,6 @@ static const struct sopcode32 coprocessor_opcodes[] =
   {ANY, ARM_FEATURE_CORE_LOW (0),
     SENTINEL_IWMMXT_END, 0, "" },
 
-  /* Floating point coprocessor (FPA) instructions.  */
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
-    0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
-    0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
-  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
-    0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
-
   /* Armv8.1-M Mainline instructions.  */
   {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
     0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
@@ -5011,9 +4916,6 @@ static const char *const arm_conditional[] =
 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
 
-static const char *const arm_fp_const[] =
-{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
-
 static const char *const arm_shift[] =
 {"lsl", "lsr", "asr", "ror"};
 
@@ -8299,25 +8201,6 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
 			arm_conditional[cond]);
 		  break;
 
-		case 'I':
-		  /* Print a Cirrus/DSP shift immediate.  */
-		  /* Immediates are 7bit signed ints with bits 0..3 in
-		     bits 0..3 of opcode and bits 4..6 in bits 5..7
-		     of opcode.  */
-		  {
-		    int imm;
-
-		    imm = (given & 0xf) | ((given & 0xe0) >> 1);
-
-		    /* Is ``imm'' a negative number?  */
-		    if (imm & 0x40)
-		      imm -= 0x80;
-
-		    func (stream, dis_style_immediate, "%d", imm);
-		  }
-
-		  break;
-
 		case 'J':
 		  {
 		    unsigned long regno
@@ -8351,76 +8234,6 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
 		  }
 		  break;
 
-		case 'F':
-		  switch (given & 0x00408000)
-		    {
-		    case 0:
-		      func (stream, dis_style_immediate, "4");
-		      break;
-		    case 0x8000:
-		      func (stream, dis_style_immediate, "1");
-		      break;
-		    case 0x00400000:
-		      func (stream, dis_style_immediate, "2");
-		      break;
-		    default:
-		      func (stream, dis_style_immediate, "3");
-		    }
-		  break;
-
-		case 'P':
-		  switch (given & 0x00080080)
-		    {
-		    case 0:
-		      func (stream, dis_style_mnemonic, "s");
-		      break;
-		    case 0x80:
-		      func (stream, dis_style_mnemonic, "d");
-		      break;
-		    case 0x00080000:
-		      func (stream, dis_style_mnemonic, "e");
-		      break;
-		    default:
-		      func (stream, dis_style_text, _("<illegal precision>"));
-		      break;
-		    }
-		  break;
-
-		case 'Q':
-		  switch (given & 0x00408000)
-		    {
-		    case 0:
-		      func (stream, dis_style_mnemonic, "s");
-		      break;
-		    case 0x8000:
-		      func (stream, dis_style_mnemonic, "d");
-		      break;
-		    case 0x00400000:
-		      func (stream, dis_style_mnemonic, "e");
-		      break;
-		    default:
-		      func (stream, dis_style_mnemonic, "p");
-		      break;
-		    }
-		  break;
-
-		case 'R':
-		  switch (given & 0x60)
-		    {
-		    case 0:
-		      break;
-		    case 0x20:
-		      func (stream, dis_style_mnemonic, "p");
-		      break;
-		    case 0x40:
-		      func (stream, dis_style_mnemonic, "m");
-		      break;
-		    default:
-		      func (stream, dis_style_mnemonic, "z");
-		      break;
-		    }
-		  break;
-
 		case '0': case '1': case '2': case '3': case '4':
 		case '5': case '6': case '7': case '8': case '9':
 		  {
@@ -8517,14 +8330,6 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
 			}
 			break;
 
-		      case 'f':
-			if (value > 7)
-			  func (stream, dis_style_immediate, "#%s",
-				arm_fp_const[value & 7]);
-			else
-			  func (stream, dis_style_register, "f%ld", value);
-			break;
-
 		      case 'w':
 			if (width == 2)
 			  func (stream, dis_style_mnemonic, "%s",

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 10/11] arm: minor documentation cleanup given removal of FPA
  2024-06-03 11:49 [PATCH 00/11] arm: Remove FPA support from gas/binutils Richard Earnshaw
                   ` (8 preceding siblings ...)
  2024-06-03 11:49 ` [PATCH 09/11] arm: remove disassembly support for the FPA co-processor Richard Earnshaw
@ 2024-06-03 11:49 ` Richard Earnshaw
  2024-06-03 11:49 ` [PATCH 11/11] NEWS: arm: note that FPA support has been removed Richard Earnshaw
  10 siblings, 0 replies; 14+ messages in thread
From: Richard Earnshaw @ 2024-06-03 11:49 UTC (permalink / raw)
  To: binutils; +Cc: nickc, Richard Earnshaw

[-- Attachment #1: Type: text/plain, Size: 164 bytes --]


The use in the documentation of .save for an FPA instruction is no-longer
relevant, so remove it.
---
 gas/doc/c-arm.texi | 3 ---
 1 file changed, 3 deletions(-)


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0010-arm-minor-documentation-cleanup-given-removal-of-FPA.patch --]
[-- Type: text/x-patch; name="0010-arm-minor-documentation-cleanup-given-removal-of-FPA.patch", Size: 421 bytes --]

diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 6d98c62949c..8135f011112 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -1147,9 +1147,6 @@ instruction.
 @exdent @emph{core registers}
   .save @{r4, r5, r6, lr@}
   stmfd sp!, @{r4, r5, r6, lr@}
-@exdent @emph{FPA registers}
-  .save f4, 2
-  sfmfd f4, 2, [sp]!
 @exdent @emph{VFP registers}
   .save @{d8, d9, d10@}
   fstmdx sp!, @{d8, d9, d10@}

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 11/11] NEWS: arm: note that FPA support has been removed
  2024-06-03 11:49 [PATCH 00/11] arm: Remove FPA support from gas/binutils Richard Earnshaw
                   ` (9 preceding siblings ...)
  2024-06-03 11:49 ` [PATCH 10/11] arm: minor documentation cleanup given removal of FPA Richard Earnshaw
@ 2024-06-03 11:49 ` Richard Earnshaw
  10 siblings, 0 replies; 14+ messages in thread
From: Richard Earnshaw @ 2024-06-03 11:49 UTC (permalink / raw)
  To: binutils; +Cc: nickc, Richard Earnshaw

[-- Attachment #1: Type: text/plain, Size: 62 bytes --]

---
 binutils/NEWS | 4 ++++
 1 file changed, 4 insertions(+)


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0011-NEWS-arm-note-that-FPA-support-has-been-removed.patch --]
[-- Type: text/x-patch; name="0011-NEWS-arm-note-that-FPA-support-has-been-removed.patch", Size: 572 bytes --]

diff --git a/binutils/NEWS b/binutils/NEWS
index 756a29d1292..c4739386cb2 100644
--- a/binutils/NEWS
+++ b/binutils/NEWS
@@ -16,6 +16,10 @@
   removed.  The CPU name ep9312 is still recognized, but treated as an alias
   for arm920t.
 
+* Support for the FPA co-procossor on Arm has been removed.  In cases where a
+  legacy CPU previously defaulted to using this instruction set extension, the
+  assembler now defaults to no-FPU to avoid quietly misassembling legacy code.
+
 Changes in 2.42:
 
 * The objdump program has a new command line option -Z/--decompress which

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 03/11] arm: default to softvfp on armv6 or later cores
  2024-06-04 11:56 [PATCH 00/11] [2nd resend] arm: Remove FPA support from gas/binutils Richard Earnshaw
@ 2024-06-04 11:56 ` Richard Earnshaw
  0 siblings, 0 replies; 14+ messages in thread
From: Richard Earnshaw @ 2024-06-04 11:56 UTC (permalink / raw)
  To: binutils; +Cc: Richard Earnshaw

From armv6 onwards a lot of cores started to come with a physical VFP
implementation; but many still did not and in some cases there are
both variants.  For the cores that lacked a physical VFP we would fall
back to FPU_NONE if the platform/ABI did not mandate something else.
To make matters worse, FPU_NONE is internal state used to imply
soft-fpa (ie a mixed-endian double format), so any use of .double in
hand-written assembly is almost certainly generating incorrect output.

That's undesirable, all these cores should really default to a softvfp
model.
---
 gas/config/tc-arm.c | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 12e8f7cfc84..8452ea17a02 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -31458,10 +31458,10 @@ static const struct arm_cpu_option_table arm_cpus[] =
 	       FPU_ARCH_VFP_V2),
   ARM_CPU_OPT ("arm1136js",	  "ARM1136J-S",	       ARM_ARCH_V6,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("arm1136j-s",	  NULL,		       ARM_ARCH_V6,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("arm1136jfs",	  "ARM1136JF-S",       ARM_ARCH_V6,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_VFP_V2),
@@ -31473,22 +31473,22 @@ static const struct arm_cpu_option_table arm_cpus[] =
 	       FPU_ARCH_VFP_V2),
   ARM_CPU_OPT ("mpcorenovfp",	  "MPCore",	       ARM_ARCH_V6K,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("arm1156t2-s",	  NULL,		       ARM_ARCH_V6T2,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("arm1156t2f-s",	  NULL,		       ARM_ARCH_V6T2,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_VFP_V2),
   ARM_CPU_OPT ("arm1176jz-s",	  NULL,		       ARM_ARCH_V6KZ,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("arm1176jzf-s",	  NULL,		       ARM_ARCH_V6KZ,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_VFP_V2),
   ARM_CPU_OPT ("cortex-a5",	  "Cortex-A5",	       ARM_ARCH_V7A,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-a7",	  "Cortex-A7",	       ARM_ARCH_V7VE,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_NEON_VFP_V4),
@@ -31559,13 +31559,13 @@ static const struct arm_cpu_option_table arm_cpus[] =
 	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
   ARM_CPU_OPT ("cortex-r4",	  "Cortex-R4",	       ARM_ARCH_V7R,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-r4f",	  "Cortex-R4F",	       ARM_ARCH_V7R,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_VFP_V3D16),
   ARM_CPU_OPT ("cortex-r5",	  "Cortex-R5",	       ARM_ARCH_V7R,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-r7",	  "Cortex-R7",	       ARM_ARCH_V7R,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
 	       FPU_ARCH_VFP_V3D16),
@@ -31580,31 +31580,31 @@ static const struct arm_cpu_option_table arm_cpus[] =
 	      FPU_ARCH_NEON_VFP_ARMV8),
   ARM_CPU_OPT ("cortex-m35p",	  "Cortex-M35P",       ARM_ARCH_V8M_MAIN,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m33",	  "Cortex-M33",	       ARM_ARCH_V8M_MAIN,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m23",	  "Cortex-M23",	       ARM_ARCH_V8M_BASE,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m7",	  "Cortex-M7",	       ARM_ARCH_V7EM,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m4",	  "Cortex-M4",	       ARM_ARCH_V7EM,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m3",	  "Cortex-M3",	       ARM_ARCH_V7M,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m1",	  "Cortex-M1",	       ARM_ARCH_V6SM,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m0",	  "Cortex-M0",	       ARM_ARCH_V6SM,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m0plus",	  "Cortex-M0+",	       ARM_ARCH_V6SM,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-x1",   "Cortex-X1",	       ARM_ARCH_V8_2A,
 	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
 	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-- 
2.34.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 03/11] arm: default to softvfp on armv6 or later cores
  2024-06-03 15:14 [PATCH 00/11] [resend] arm: Remove FPA support from gas/binutils Richard Earnshaw
@ 2024-06-03 15:14 ` Richard Earnshaw
  0 siblings, 0 replies; 14+ messages in thread
From: Richard Earnshaw @ 2024-06-03 15:14 UTC (permalink / raw)
  To: binutils; +Cc: nickc, Richard Earnshaw

[-- Attachment #1: Type: text/plain, Size: 678 bytes --]


From armv6 onwards a lot of cores started to come with a physical VFP
implementation; but many still did not and in some cases there are
both variants.  For the cores that lacked a physical VFP we would fall
back to FPU_NONE if the platform/ABI did not mandate something else.
To make matters worse, FPU_NONE is internal state used to imply
soft-fpa (ie a mixed-endian double format), so any use of .double in
hand-written assembly is almost certainly generating incorrect output.

That's undesirable, all these cores should really default to a softvfp
model.
---
 gas/config/tc-arm.c | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0003-arm-default-to-softvfp-on-armv6-or-later-cores.patch --]
[-- Type: text/x-patch; name="0003-arm-default-to-softvfp-on-armv6-or-later-cores.patch", Size: 3993 bytes --]

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 12e8f7cfc84..8452ea17a02 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -31458,10 +31458,10 @@ static const struct arm_cpu_option_table arm_cpus[] =
 	       FPU_ARCH_VFP_V2),
   ARM_CPU_OPT ("arm1136js",	  "ARM1136J-S",	       ARM_ARCH_V6,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("arm1136j-s",	  NULL,		       ARM_ARCH_V6,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("arm1136jfs",	  "ARM1136JF-S",       ARM_ARCH_V6,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_VFP_V2),
@@ -31473,22 +31473,22 @@ static const struct arm_cpu_option_table arm_cpus[] =
 	       FPU_ARCH_VFP_V2),
   ARM_CPU_OPT ("mpcorenovfp",	  "MPCore",	       ARM_ARCH_V6K,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("arm1156t2-s",	  NULL,		       ARM_ARCH_V6T2,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("arm1156t2f-s",	  NULL,		       ARM_ARCH_V6T2,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_VFP_V2),
   ARM_CPU_OPT ("arm1176jz-s",	  NULL,		       ARM_ARCH_V6KZ,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("arm1176jzf-s",	  NULL,		       ARM_ARCH_V6KZ,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_VFP_V2),
   ARM_CPU_OPT ("cortex-a5",	  "Cortex-A5",	       ARM_ARCH_V7A,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-a7",	  "Cortex-A7",	       ARM_ARCH_V7VE,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_NEON_VFP_V4),
@@ -31559,13 +31559,13 @@ static const struct arm_cpu_option_table arm_cpus[] =
 	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
   ARM_CPU_OPT ("cortex-r4",	  "Cortex-R4",	       ARM_ARCH_V7R,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-r4f",	  "Cortex-R4F",	       ARM_ARCH_V7R,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_VFP_V3D16),
   ARM_CPU_OPT ("cortex-r5",	  "Cortex-R5",	       ARM_ARCH_V7R,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-r7",	  "Cortex-R7",	       ARM_ARCH_V7R,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
 	       FPU_ARCH_VFP_V3D16),
@@ -31580,31 +31580,31 @@ static const struct arm_cpu_option_table arm_cpus[] =
 	      FPU_ARCH_NEON_VFP_ARMV8),
   ARM_CPU_OPT ("cortex-m35p",	  "Cortex-M35P",       ARM_ARCH_V8M_MAIN,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m33",	  "Cortex-M33",	       ARM_ARCH_V8M_MAIN,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m23",	  "Cortex-M23",	       ARM_ARCH_V8M_BASE,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m7",	  "Cortex-M7",	       ARM_ARCH_V7EM,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m4",	  "Cortex-M4",	       ARM_ARCH_V7EM,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m3",	  "Cortex-M3",	       ARM_ARCH_V7M,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m1",	  "Cortex-M1",	       ARM_ARCH_V6SM,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m0",	  "Cortex-M0",	       ARM_ARCH_V6SM,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-m0plus",	  "Cortex-M0+",	       ARM_ARCH_V6SM,
 	       ARM_ARCH_NONE,
-	       FPU_NONE),
+	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-x1",   "Cortex-X1",	       ARM_ARCH_V8_2A,
 	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
 	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),

^ permalink raw reply	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2024-06-04 11:57 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-06-03 11:49 [PATCH 00/11] arm: Remove FPA support from gas/binutils Richard Earnshaw
2024-06-03 11:49 ` [PATCH 01/11] arm: remove FPA related tests Richard Earnshaw
2024-06-03 11:49 ` [PATCH 02/11] arm: rename FPU_ARCH_VFP to FPU_ARCH_SOFTVFP Richard Earnshaw
2024-06-03 11:49 ` [PATCH 03/11] arm: default to softvfp on armv6 or later cores Richard Earnshaw
2024-06-03 11:49 ` [PATCH 04/11] arm: adjust FPU selection logic Richard Earnshaw
2024-06-03 11:49 ` [PATCH 05/11] arm: redirect fp constant data directives through a wrapper Richard Earnshaw
2024-06-03 11:49 ` [PATCH 06/11] arm: change default FPUs from FPA to none Richard Earnshaw
2024-06-03 11:49 ` [PATCH 07/11] arm: remove options to select the FPA Richard Earnshaw
2024-06-03 11:49 ` [PATCH 08/11] arm: remove FPA instructions from assembler Richard Earnshaw
2024-06-03 11:49 ` [PATCH 09/11] arm: remove disassembly support for the FPA co-processor Richard Earnshaw
2024-06-03 11:49 ` [PATCH 10/11] arm: minor documentation cleanup given removal of FPA Richard Earnshaw
2024-06-03 11:49 ` [PATCH 11/11] NEWS: arm: note that FPA support has been removed Richard Earnshaw
2024-06-03 15:14 [PATCH 00/11] [resend] arm: Remove FPA support from gas/binutils Richard Earnshaw
2024-06-03 15:14 ` [PATCH 03/11] arm: default to softvfp on armv6 or later cores Richard Earnshaw
2024-06-04 11:56 [PATCH 00/11] [2nd resend] arm: Remove FPA support from gas/binutils Richard Earnshaw
2024-06-04 11:56 ` [PATCH 03/11] arm: default to softvfp on armv6 or later cores Richard Earnshaw

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