From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from zg8tmja2lje4os4yms4ymjma.icoremail.net (zg8tmja2lje4os4yms4ymjma.icoremail.net [206.189.21.223]) by sourceware.org (Postfix) with ESMTP id E30CE38CEE9C for ; Thu, 6 Jun 2024 07:53:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E30CE38CEE9C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E30CE38CEE9C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=206.189.21.223 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1717660437; cv=none; b=UX6CqlViL2mipsW53L428836JBkHFa1yOZX8mppvvoL9RpT9P1dy/enqFpO5VkU0RrvcquuCmuYFCv6eHMnkMZW+iogXp4PE1FgQHWMqug5sbvvOjAWZOEP0D8sGM/V67j/iN4XJm75/6ukQQpFW23ANxO4LQj3vitjGlp1651I= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1717660437; c=relaxed/simple; bh=b3YjsuJ9j4Y676iSb5iWBWGurtVBDyYwVTPCQ030ZZE=; h=From:To:Subject:Date:Message-Id; b=INTehsZ47seFKTi2735+LTbsLdiTIR88fy9yTDAbQvjTJRnwK2DnCSoFXBHG7Hlb0efU+ck+mMEmVTJmbN1n4SxpUle58ZUrt+nIuCHn4GZofquqQf/G4D6qtLCg/6WCzL7bFZscO/Ig/rD5FhWbyxHmL35yVleOLvr9Jpowl20= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.38]) by app1 (Coremail) with SMTP id TAJkCgBX+OR4amFmH6MOAA--.40123S5; Thu, 06 Jun 2024 15:51:21 +0800 (CST) From: Xiao Zeng To: binutils@sourceware.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, nelson@rivosinc.com, zhengyu@eswincomputing.com, Xiao Zeng Subject: [PATCH 1/3] RISC-V: Add support for Zfbfmin extension Date: Thu, 6 Jun 2024 15:59:51 +0800 Message-Id: <20240606075953.28696-2-zengxiao@eswincomputing.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240606075953.28696-1-zengxiao@eswincomputing.com> References: <20240606075953.28696-1-zengxiao@eswincomputing.com> X-CM-TRANSID:TAJkCgBX+OR4amFmH6MOAA--.40123S5 X-Coremail-Antispam: 1UD129KBjvJXoW3AryrCFyktF1kKr1DCF47XFb_yoW3uw4rpF s5uFnY9r95X3Z7Jrn3GF1UKF47uanYgr1Ykr1S9w13AwsIqrWvqF4ktw15AF4kXF45Kr1S ga1agrW5Z3yUA3JanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUB214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE-syl42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfU5iSlUUUUU X-CM-SenderInfo: p2hqw5xldrqvxvzl0uprps33xlqjhudrp/ X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This implements the Zfbfmin extension, as of version 1.0. View detailed information in: 1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and FMV.H.X instructions as defined in the Zfh extension. 2 The Zfhmin extension includes the following instructions from the Zfh extension: FLH, FSH, FMV.X.H, FMV.H.X... View detailed information in: 3 Zfhmin extension depend on 'F'. 4 Simply put, just make Zfbfmin dependent on Zfhmin. Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and FMV.H.X instructions an independent extension to achieve precise dependency relationships for the Zfbfmin. 5 For relevant information in gcc, please refer to: bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zfbfmin. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zfbfmin.d: New test. * testsuite/gas/riscv/zfbfmin.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_FCVT_BF16_S): Define. (MASK_FCVT_BF16_S): Ditto. (MATCH_FCVT_S_BF16): Ditto. (MASK_FCVT_S_BF16): Ditto. (DECLARE_INSN): New declarations for Zfbfmin. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZFBFMIN. opcodes/ChangeLog: * riscv-opc.c: Add Zfbfmin instructions. --- bfd/elfxx-riscv.c | 6 ++++++ gas/NEWS | 2 ++ gas/testsuite/gas/riscv/march-help.l | 1 + gas/testsuite/gas/riscv/zfbfmin.d | 11 +++++++++++ gas/testsuite/gas/riscv/zfbfmin.s | 6 ++++++ include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 5 +++++ 8 files changed, 40 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zfbfmin.d create mode 100644 gas/testsuite/gas/riscv/zfbfmin.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 5cb063a68a9..1d70139725a 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1222,6 +1222,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zihpm", "zicsr", check_implicit_always}, {"zcd", "d", check_implicit_always}, {"zcf", "f", check_implicit_always}, + {"zfbfmin", "zfhmin", check_implicit_always}, {"zfa", "f", check_implicit_always}, {"d", "f", check_implicit_always}, {"zfh", "zfhmin", check_implicit_always}, @@ -1359,6 +1360,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2582,6 +2584,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, && riscv_subset_supports (rps, "q")) || (riscv_subset_supports (rps, "zhinxmin") && riscv_subset_supports (rps, "zqinx"))); + case INSN_CLASS_ZFBFMIN: + return riscv_subset_supports (rps, "zfbfmin"); case INSN_CLASS_ZFA: return riscv_subset_supports (rps, "zfa"); case INSN_CLASS_D_AND_ZFA: @@ -2836,6 +2840,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "zhinxmin"; else return _("zfhmin' and `q', or `zhinxmin' and `zqinx"); + case INSN_CLASS_ZFBFMIN: + return "zfbfmin"; case INSN_CLASS_ZFA: return "zfa"; case INSN_CLASS_D_AND_ZFA: diff --git a/gas/NEWS b/gas/NEWS index e51c3bbba6d..cdf30941894 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -21,6 +21,8 @@ * Add support for RISC-V Zcmp extension with version 1.0. +* Add support for RISC-V Zfbfmin extension with version 1.0. + * The base register operand in D(X,B) and D(L,B) may be explicitly omitted in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0) D(X,%r0), D(L,0), and D(L,%r0). diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index 5b5a36633e1..57c73b3074e 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -25,6 +25,7 @@ All available -march extensions for RISC-V: zabha 1.0 zalrsc 1.0 zawrs 1.0 + zfbfmin 1.0 zfa 1.0 zfh 1.0 zfhmin 1.0 diff --git a/gas/testsuite/gas/riscv/zfbfmin.d b/gas/testsuite/gas/riscv/zfbfmin.d new file mode 100644 index 00000000000..7cacc0bd684 --- /dev/null +++ b/gas/testsuite/gas/riscv/zfbfmin.d @@ -0,0 +1,11 @@ +#as: -march=rv64i_zfbfmin +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+4485f553[ ]+fcvt.bf16.s[ ]+fa0,fa1 +[ ]+[0-9a-f]+:[ ]+44858553[ ]+fcvt.bf16.s[ ]+fa0,fa1,rne +[ ]+[0-9a-f]+:[ ]+40658553[ ]+fcvt.s.bf16[ ]+fa0,fa1 diff --git a/gas/testsuite/gas/riscv/zfbfmin.s b/gas/testsuite/gas/riscv/zfbfmin.s new file mode 100644 index 00000000000..c9a9af3e394 --- /dev/null +++ b/gas/testsuite/gas/riscv/zfbfmin.s @@ -0,0 +1,6 @@ +target: + # fcvt.bf16.s + fcvt.bf16.s fa0, fa1 + fcvt.bf16.s fa0, fa1, rne + # fcvt.s.bf16 + fcvt.s.bf16 fa0, fa1 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index cd957ef9b6f..ef33aeb1b36 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2365,6 +2365,11 @@ #define MASK_WRS_NTO 0xffffffff #define MATCH_WRS_STO 0x01d00073 #define MASK_WRS_STO 0xffffffff +/* Zfbfmin intructions. */ +#define MATCH_FCVT_BF16_S 0x44800053 +#define MASK_FCVT_BF16_S 0xfff0007f +#define MATCH_FCVT_S_BF16 0x40600053 +#define MASK_FCVT_S_BF16 0xfff0007f /* Vendor-specific (CORE-V) Xcvmac instructions. */ #define MATCH_CV_MAC 0x9000302b #define MASK_CV_MAC 0xfe00707f @@ -3969,6 +3974,9 @@ DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL) /* Zawrs instructions. */ DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) +/* Zfbfmin instructions. */ +DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S) +DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16) /* Zvbb/Zvkb instructions. */ DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV) DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 0653ae57255..dfb86966b0a 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -449,6 +449,7 @@ enum riscv_insn_class INSN_CLASS_ZFHMIN_INX, INSN_CLASS_ZFHMIN_AND_D_INX, INSN_CLASS_ZFHMIN_AND_Q_INX, + INSN_CLASS_ZFBFMIN, INSN_CLASS_ZFA, INSN_CLASS_D_AND_ZFA, INSN_CLASS_Q_AND_ZFA, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 4bb54b7eaf0..1ccf0685b2b 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -829,6 +829,11 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_LU|MASK_RM, match_opcode, 0 }, {"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 }, +/* Zfbfmin instructions. */ +{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 }, +{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 }, +{"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 }, + /* Single-precision floating-point instruction subset. */ {"frcsr", 0, INSN_CLASS_F_INX, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, {"frsr", 0, INSN_CLASS_F_INX, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, -- 2.17.1