* [PING] [PATCH 0/3 v2] RISC-V: Add support for Zfbfmin Zvfbfmin and Zvfbfwma extension
@ 2024-06-06 7:59 Xiao Zeng
2024-06-06 7:59 ` [PATCH 1/3] RISC-V: Add support for Zfbfmin extension Xiao Zeng
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Xiao Zeng @ 2024-06-06 7:59 UTC (permalink / raw)
To: binutils; +Cc: kito.cheng, palmer, nelson, zhengyu, Xiao Zeng
These three extensions are already supported in gcc, and detailed
information can be found in each patch.
Xiao Zeng (3):
RISC-V: Add support for Zfbfmin extension
RISC-V: Add support for Zvfbfmin extension
RISC-V: Add support for Zvfbfwma extension
bfd/elfxx-riscv.c | 19 +++++++++++++++++++
gas/NEWS | 6 ++++++
gas/testsuite/gas/riscv/march-help.l | 3 +++
gas/testsuite/gas/riscv/zfbfmin.d | 11 +++++++++++
gas/testsuite/gas/riscv/zfbfmin.s | 6 ++++++
gas/testsuite/gas/riscv/zvfbfmin.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zvfbfmin.s | 7 +++++++
gas/testsuite/gas/riscv/zvfbfwma.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zvfbfwma.s | 7 +++++++
include/opcode/riscv-opc.h | 24 ++++++++++++++++++++++++
include/opcode/riscv.h | 3 +++
opcodes/riscv-opc.c | 13 +++++++++++++
12 files changed, 123 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zfbfmin.d
create mode 100644 gas/testsuite/gas/riscv/zfbfmin.s
create mode 100644 gas/testsuite/gas/riscv/zvfbfmin.d
create mode 100644 gas/testsuite/gas/riscv/zvfbfmin.s
create mode 100644 gas/testsuite/gas/riscv/zvfbfwma.d
create mode 100644 gas/testsuite/gas/riscv/zvfbfwma.s
--
2.17.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/3] RISC-V: Add support for Zfbfmin extension
2024-06-06 7:59 [PING] [PATCH 0/3 v2] RISC-V: Add support for Zfbfmin Zvfbfmin and Zvfbfwma extension Xiao Zeng
@ 2024-06-06 7:59 ` Xiao Zeng
2024-06-06 7:59 ` [PATCH 2/3] RISC-V: Add support for Zvfbfmin extension Xiao Zeng
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Xiao Zeng @ 2024-06-06 7:59 UTC (permalink / raw)
To: binutils; +Cc: kito.cheng, palmer, nelson, zhengyu, Xiao Zeng
This implements the Zfbfmin extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zfbfmin---scalar-bf16-converts>
1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and
FMV.H.X instructions as defined in the Zfh extension.
2 The Zfhmin extension includes the following instructions from the Zfh
extension: FLH, FSH, FMV.X.H, FMV.H.X... View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/zfh.adoc>
3 Zfhmin extension depend on 'F'.
4 Simply put, just make Zfbfmin dependent on Zfhmin.
Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and
FMV.H.X instructions an independent extension to achieve precise dependency
relationships for the Zfbfmin.
5 For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=35224ead63732a3550ba4b1332c06e9dc7999c31>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zfbfmin.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zfbfmin.d: New test.
* testsuite/gas/riscv/zfbfmin.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_FCVT_BF16_S): Define.
(MASK_FCVT_BF16_S): Ditto.
(MATCH_FCVT_S_BF16): Ditto.
(MASK_FCVT_S_BF16): Ditto.
(DECLARE_INSN): New declarations for Zfbfmin.
* opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZFBFMIN.
opcodes/ChangeLog:
* riscv-opc.c: Add Zfbfmin instructions.
---
bfd/elfxx-riscv.c | 6 ++++++
gas/NEWS | 2 ++
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/zfbfmin.d | 11 +++++++++++
gas/testsuite/gas/riscv/zfbfmin.s | 6 ++++++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 5 +++++
8 files changed, 40 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zfbfmin.d
create mode 100644 gas/testsuite/gas/riscv/zfbfmin.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 5cb063a68a9..1d70139725a 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1222,6 +1222,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zihpm", "zicsr", check_implicit_always},
{"zcd", "d", check_implicit_always},
{"zcf", "f", check_implicit_always},
+ {"zfbfmin", "zfhmin", check_implicit_always},
{"zfa", "f", check_implicit_always},
{"d", "f", check_implicit_always},
{"zfh", "zfhmin", check_implicit_always},
@@ -1359,6 +1360,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2582,6 +2584,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
&& riscv_subset_supports (rps, "q"))
|| (riscv_subset_supports (rps, "zhinxmin")
&& riscv_subset_supports (rps, "zqinx")));
+ case INSN_CLASS_ZFBFMIN:
+ return riscv_subset_supports (rps, "zfbfmin");
case INSN_CLASS_ZFA:
return riscv_subset_supports (rps, "zfa");
case INSN_CLASS_D_AND_ZFA:
@@ -2836,6 +2840,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "zhinxmin";
else
return _("zfhmin' and `q', or `zhinxmin' and `zqinx");
+ case INSN_CLASS_ZFBFMIN:
+ return "zfbfmin";
case INSN_CLASS_ZFA:
return "zfa";
case INSN_CLASS_D_AND_ZFA:
diff --git a/gas/NEWS b/gas/NEWS
index e51c3bbba6d..cdf30941894 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -21,6 +21,8 @@
* Add support for RISC-V Zcmp extension with version 1.0.
+* Add support for RISC-V Zfbfmin extension with version 1.0.
+
* The base register operand in D(X,B) and D(L,B) may be explicitly omitted
in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0)
D(X,%r0), D(L,0), and D(L,%r0).
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 5b5a36633e1..57c73b3074e 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -25,6 +25,7 @@ All available -march extensions for RISC-V:
zabha 1.0
zalrsc 1.0
zawrs 1.0
+ zfbfmin 1.0
zfa 1.0
zfh 1.0
zfhmin 1.0
diff --git a/gas/testsuite/gas/riscv/zfbfmin.d b/gas/testsuite/gas/riscv/zfbfmin.d
new file mode 100644
index 00000000000..7cacc0bd684
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfbfmin.d
@@ -0,0 +1,11 @@
+#as: -march=rv64i_zfbfmin
+#objdump: -d
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+4485f553[ ]+fcvt.bf16.s[ ]+fa0,fa1
+[ ]+[0-9a-f]+:[ ]+44858553[ ]+fcvt.bf16.s[ ]+fa0,fa1,rne
+[ ]+[0-9a-f]+:[ ]+40658553[ ]+fcvt.s.bf16[ ]+fa0,fa1
diff --git a/gas/testsuite/gas/riscv/zfbfmin.s b/gas/testsuite/gas/riscv/zfbfmin.s
new file mode 100644
index 00000000000..c9a9af3e394
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfbfmin.s
@@ -0,0 +1,6 @@
+target:
+ # fcvt.bf16.s
+ fcvt.bf16.s fa0, fa1
+ fcvt.bf16.s fa0, fa1, rne
+ # fcvt.s.bf16
+ fcvt.s.bf16 fa0, fa1
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index cd957ef9b6f..ef33aeb1b36 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2365,6 +2365,11 @@
#define MASK_WRS_NTO 0xffffffff
#define MATCH_WRS_STO 0x01d00073
#define MASK_WRS_STO 0xffffffff
+/* Zfbfmin intructions. */
+#define MATCH_FCVT_BF16_S 0x44800053
+#define MASK_FCVT_BF16_S 0xfff0007f
+#define MATCH_FCVT_S_BF16 0x40600053
+#define MASK_FCVT_S_BF16 0xfff0007f
/* Vendor-specific (CORE-V) Xcvmac instructions. */
#define MATCH_CV_MAC 0x9000302b
#define MASK_CV_MAC 0xfe00707f
@@ -3969,6 +3974,9 @@ DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL)
/* Zawrs instructions. */
DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
+/* Zfbfmin instructions. */
+DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S)
+DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16)
/* Zvbb/Zvkb instructions. */
DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 0653ae57255..dfb86966b0a 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -449,6 +449,7 @@ enum riscv_insn_class
INSN_CLASS_ZFHMIN_INX,
INSN_CLASS_ZFHMIN_AND_D_INX,
INSN_CLASS_ZFHMIN_AND_Q_INX,
+ INSN_CLASS_ZFBFMIN,
INSN_CLASS_ZFA,
INSN_CLASS_D_AND_ZFA,
INSN_CLASS_Q_AND_ZFA,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 4bb54b7eaf0..1ccf0685b2b 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -829,6 +829,11 @@ const struct riscv_opcode riscv_opcodes[] =
{"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_LU|MASK_RM, match_opcode, 0 },
{"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
+/* Zfbfmin instructions. */
+{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 },
+{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 },
+{"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 },
+
/* Single-precision floating-point instruction subset. */
{"frcsr", 0, INSN_CLASS_F_INX, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
{"frsr", 0, INSN_CLASS_F_INX, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
--
2.17.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/3] RISC-V: Add support for Zvfbfmin extension
2024-06-06 7:59 [PING] [PATCH 0/3 v2] RISC-V: Add support for Zfbfmin Zvfbfmin and Zvfbfwma extension Xiao Zeng
2024-06-06 7:59 ` [PATCH 1/3] RISC-V: Add support for Zfbfmin extension Xiao Zeng
@ 2024-06-06 7:59 ` Xiao Zeng
2024-06-06 7:59 ` [PATCH 3/3] RISC-V: Add support for Zvfbfwma extension Xiao Zeng
2024-06-06 8:16 ` [PING] [PATCH 0/3 v2] RISC-V: Add support for Zfbfmin Zvfbfmin and " Nelson Chu
3 siblings, 0 replies; 7+ messages in thread
From: Xiao Zeng @ 2024-06-06 7:59 UTC (permalink / raw)
To: binutils; +Cc: kito.cheng, palmer, nelson, zhengyu, Xiao Zeng
This implements the Zvfbfmin extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfmin---vector-bf16-converts>
Depending on different usage scenarios, the Zvfbfmin extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies
in scenario of Embedded Processor. In scenario of Application
Processor, it is necessary to explicitly indicate the dependent
'V' extension.
For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zvfbfmin.d: New test.
* testsuite/gas/riscv/zvfbfmin.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define.
(MASK_VFNCVTBF16_F_F_W): Ditto.
(MATCH_VFWCVTBF16_F_F_V): Ditto.
(MASK_VFWCVTBF16_F_F_V): Ditto.
(DECLARE_INSN): New declarations for Zvfbfmin.
* opcode/riscv.h (enum riscv_insn_class): Add
INSN_CLASS_ZVFBFMIN
opcodes/ChangeLog:
* riscv-opc.c: Add Zvfbfmin instructions.
---
bfd/elfxx-riscv.c | 6 ++++++
gas/NEWS | 2 ++
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/zvfbfmin.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zvfbfmin.s | 7 +++++++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 4 ++++
8 files changed, 41 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvfbfmin.d
create mode 100644 gas/testsuite/gas/riscv/zvfbfmin.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 1d70139725a..0131ce85477 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1192,6 +1192,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"v", "zve64d", check_implicit_always},
{"v", "zvl128b", check_implicit_always},
{"zabha", "a", check_implicit_always},
+ {"zvfbfmin", "zve32f", check_implicit_always},
{"zvfh", "zvfhmin", check_implicit_always},
{"zvfh", "zfhmin", check_implicit_always},
{"zvfhmin", "zve32f", check_implicit_always},
@@ -1393,6 +1394,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2647,6 +2649,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zvbb");
case INSN_CLASS_ZVBC:
return riscv_subset_supports (rps, "zvbc");
+ case INSN_CLASS_ZVFBFMIN:
+ return riscv_subset_supports (rps, "zvfbfmin");
case INSN_CLASS_ZVKB:
return riscv_subset_supports (rps, "zvkb");
case INSN_CLASS_ZVKG:
@@ -2917,6 +2921,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvbb");
case INSN_CLASS_ZVBC:
return _("zvbc");
+ case INSN_CLASS_ZVFBFMIN:
+ return "zvfbfmin";
case INSN_CLASS_ZVKB:
return _("zvkb");
case INSN_CLASS_ZVKG:
diff --git a/gas/NEWS b/gas/NEWS
index cdf30941894..a668a521772 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -23,6 +23,8 @@
* Add support for RISC-V Zfbfmin extension with version 1.0.
+* Add support for RISC-V Zvfbfmin extension with version 1.0.
+
* The base register operand in D(X,B) and D(L,B) may be explicitly omitted
in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0)
D(X,%r0), D(L,0), and D(L,%r0).
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 57c73b3074e..38c70e269bf 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -58,6 +58,7 @@ All available -march extensions for RISC-V:
zve64d 1.0
zvbb 1.0
zvbc 1.0
+ zvfbfmin 1.0
zvfh 1.0
zvfhmin 1.0
zvkb 1.0
diff --git a/gas/testsuite/gas/riscv/zvfbfmin.d b/gas/testsuite/gas/riscv/zvfbfmin.d
new file mode 100644
index 00000000000..ce973812fe1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfmin.d
@@ -0,0 +1,12 @@
+#as: -march=rv64iv_zvfbfmin
+#objdump: -d
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+4a8e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+488e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+48869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8,v0.t
diff --git a/gas/testsuite/gas/riscv/zvfbfmin.s b/gas/testsuite/gas/riscv/zvfbfmin.s
new file mode 100644
index 00000000000..9a4493d84d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfmin.s
@@ -0,0 +1,7 @@
+target:
+ # vfncvtbf16.f.f.w
+ vfncvtbf16.f.f.w v4, v8
+ vfncvtbf16.f.f.w v4, v8, v0.t
+ # vfwcvtbf16.f.f.v
+ vfwcvtbf16.f.f.v v4, v8
+ vfwcvtbf16.f.f.v v4, v8, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index ef33aeb1b36..c5270d017b2 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2370,6 +2370,11 @@
#define MASK_FCVT_BF16_S 0xfff0007f
#define MATCH_FCVT_S_BF16 0x40600053
#define MASK_FCVT_S_BF16 0xfff0007f
+/* Zvfbfmin intructions. */
+#define MATCH_VFNCVTBF16_F_F_W 0x480e9057
+#define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f
+#define MATCH_VFWCVTBF16_F_F_V 0x48069057
+#define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f
/* Vendor-specific (CORE-V) Xcvmac instructions. */
#define MATCH_CV_MAC 0x9000302b
#define MASK_CV_MAC 0xfe00707f
@@ -3977,6 +3982,9 @@ DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
/* Zfbfmin instructions. */
DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S)
DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16)
+/* Zvfbfmin instructions. */
+DECLARE_INSN(VFNCVTBF16_F_F_W, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W)
+DECLARE_INSN(VFWCVTBF16_F_F_V, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V)
/* Zvbb/Zvkb instructions. */
DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index dfb86966b0a..06415634c7f 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -474,6 +474,7 @@ enum riscv_insn_class
INSN_CLASS_ZVEF,
INSN_CLASS_ZVBB,
INSN_CLASS_ZVBC,
+ INSN_CLASS_ZVFBFMIN,
INSN_CLASS_ZVKB,
INSN_CLASS_ZVKG,
INSN_CLASS_ZVKNED,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 1ccf0685b2b..eccd3f6fae1 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2017,6 +2017,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_opcode, 0},
{"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_opcode, 0},
+/* Zvfbfmin instructions. */
+{"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0},
+{"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0},
+
/* Zvbb/Zvkb instructions. */
{"vandn.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDN_VV, MASK_VANDN_VV, match_opcode, 0},
{"vandn.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDN_VX, MASK_VANDN_VX, match_opcode, 0},
--
2.17.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 3/3] RISC-V: Add support for Zvfbfwma extension
2024-06-06 7:59 [PING] [PATCH 0/3 v2] RISC-V: Add support for Zfbfmin Zvfbfmin and Zvfbfwma extension Xiao Zeng
2024-06-06 7:59 ` [PATCH 1/3] RISC-V: Add support for Zfbfmin extension Xiao Zeng
2024-06-06 7:59 ` [PATCH 2/3] RISC-V: Add support for Zvfbfmin extension Xiao Zeng
@ 2024-06-06 7:59 ` Xiao Zeng
2024-06-06 8:16 ` [PING] [PATCH 0/3 v2] RISC-V: Add support for Zfbfmin Zvfbfmin and " Nelson Chu
3 siblings, 0 replies; 7+ messages in thread
From: Xiao Zeng @ 2024-06-06 7:59 UTC (permalink / raw)
To: binutils; +Cc: kito.cheng, palmer, nelson, zhengyu, Xiao Zeng
This implements the Zvfbfwma extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfwma---vector-bf16-widening-mul-add>
1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin extension."
1.1 In Embedded Processor: Zvfbfwma -> Zvfbfmin -> Zve32f
1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V
1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin
2 Depending on different usage scenarios, the Zvfbfwma extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies in
scenario of Embedded Processor. This is consistent with the processing
strategy in Zvfbfmin. In scenario of Application Processor, it is
necessary to explicitly indicate the dependent 'V' extension.
For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=38dd4e26e07c6be7cf4d169141ee4f3a03f3a09d>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfwma.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zvfbfwma.d: New test.
* testsuite/gas/riscv/zvfbfwma.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VFWMACCBF16_VF): Define.
(MASK_VFWMACCBF16_VF): Ditto.
(MATCH_VFWMACCBF16_VV): Ditto.
(MASK_VFWMACCBF16_VV): Ditto.
(DECLARE_INSN): New declarations for Zvfbfwma.
* opcode/riscv.h (enum riscv_insn_class): Add
INSN_CLASS_ZVFBFWMA
opcodes/ChangeLog:
* riscv-opc.c: Add Zvfbfwma instructions.
---
bfd/elfxx-riscv.c | 7 +++++++
gas/NEWS | 2 ++
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/zvfbfwma.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zvfbfwma.s | 7 +++++++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 4 ++++
8 files changed, 42 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvfbfwma.d
create mode 100644 gas/testsuite/gas/riscv/zvfbfwma.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 0131ce85477..1fe7e5d3df2 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1193,6 +1193,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"v", "zvl128b", check_implicit_always},
{"zabha", "a", check_implicit_always},
{"zvfbfmin", "zve32f", check_implicit_always},
+ {"zvfbfwma", "zve32f", check_implicit_always},
+ {"zvfbfwma", "zfbfmin", check_implicit_always},
{"zvfh", "zvfhmin", check_implicit_always},
{"zvfh", "zfhmin", check_implicit_always},
{"zvfhmin", "zve32f", check_implicit_always},
@@ -1395,6 +1397,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvfbfwma", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2651,6 +2654,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zvbc");
case INSN_CLASS_ZVFBFMIN:
return riscv_subset_supports (rps, "zvfbfmin");
+ case INSN_CLASS_ZVFBFWMA:
+ return riscv_subset_supports (rps, "zvfbfwma");
case INSN_CLASS_ZVKB:
return riscv_subset_supports (rps, "zvkb");
case INSN_CLASS_ZVKG:
@@ -2923,6 +2928,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvbc");
case INSN_CLASS_ZVFBFMIN:
return "zvfbfmin";
+ case INSN_CLASS_ZVFBFWMA:
+ return "zvfbfwma";
case INSN_CLASS_ZVKB:
return _("zvkb");
case INSN_CLASS_ZVKG:
diff --git a/gas/NEWS b/gas/NEWS
index a668a521772..145ce413bff 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -25,6 +25,8 @@
* Add support for RISC-V Zvfbfmin extension with version 1.0.
+* Add support for RISC-V Zvfbfwma extension with version 1.0.
+
* The base register operand in D(X,B) and D(L,B) may be explicitly omitted
in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0)
D(X,%r0), D(L,0), and D(L,%r0).
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 38c70e269bf..dd82752cd30 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -59,6 +59,7 @@ All available -march extensions for RISC-V:
zvbb 1.0
zvbc 1.0
zvfbfmin 1.0
+ zvfbfwma 1.0
zvfh 1.0
zvfhmin 1.0
zvkb 1.0
diff --git a/gas/testsuite/gas/riscv/zvfbfwma.d b/gas/testsuite/gas/riscv/zvfbfwma.d
new file mode 100644
index 00000000000..05da1328eea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfwma.d
@@ -0,0 +1,12 @@
+#as: -march=rv64iv_zvfbfwma
+#objdump: -d
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+ee865257[ ]+vfwmaccbf16.vf[ ]+v4,fa2,v8
+[ ]+[0-9a-f]+:[ ]+ec865257[ ]+vfwmaccbf16.vf[ ]+v4,fa2,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+ee861257[ ]+vfwmaccbf16.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+ec861257[ ]+vfwmaccbf16.vv[ ]+v4,v12,v8,v0.t
diff --git a/gas/testsuite/gas/riscv/zvfbfwma.s b/gas/testsuite/gas/riscv/zvfbfwma.s
new file mode 100644
index 00000000000..f824af98361
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfwma.s
@@ -0,0 +1,7 @@
+target:
+ # vfwmaccbf16.vf
+ vfwmaccbf16.vf v4, fa2, v8
+ vfwmaccbf16.vf v4, fa2, v8, v0.t
+ # vfwmaccbf16.vv
+ vfwmaccbf16.vv v4, v12, v8
+ vfwmaccbf16.vv v4, v12, v8, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index c5270d017b2..e8c08e800c6 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2375,6 +2375,11 @@
#define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f
#define MATCH_VFWCVTBF16_F_F_V 0x48069057
#define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f
+/* Zvfbfwma intructions. */
+#define MATCH_VFWMACCBF16_VF 0xec005057
+#define MASK_VFWMACCBF16_VF 0xfc00707f
+#define MATCH_VFWMACCBF16_VV 0xec001057
+#define MASK_VFWMACCBF16_VV 0xfc00707f
/* Vendor-specific (CORE-V) Xcvmac instructions. */
#define MATCH_CV_MAC 0x9000302b
#define MASK_CV_MAC 0xfe00707f
@@ -3985,6 +3990,9 @@ DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16)
/* Zvfbfmin instructions. */
DECLARE_INSN(VFNCVTBF16_F_F_W, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W)
DECLARE_INSN(VFWCVTBF16_F_F_V, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V)
+/* Zvfbfwma instructions. */
+DECLARE_INSN(VFWMACCBF16_VF, MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF)
+DECLARE_INSN(VFWMACCBF16_VV, MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV)
/* Zvbb/Zvkb instructions. */
DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 06415634c7f..33df56d13af 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -475,6 +475,7 @@ enum riscv_insn_class
INSN_CLASS_ZVBB,
INSN_CLASS_ZVBC,
INSN_CLASS_ZVFBFMIN,
+ INSN_CLASS_ZVFBFWMA,
INSN_CLASS_ZVKB,
INSN_CLASS_ZVKG,
INSN_CLASS_ZVKNED,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index eccd3f6fae1..ff08bd595c0 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2021,6 +2021,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0},
{"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0},
+/* Zvfbfwma instructions. */
+{"vfwmaccbf16.vf", 0, INSN_CLASS_ZVFBFWMA, "Vd,S,VtVm", MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF, match_opcode, 0},
+{"vfwmaccbf16.vv", 0, INSN_CLASS_ZVFBFWMA, "Vd,Vs,VtVm", MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV, match_opcode, 0},
+
/* Zvbb/Zvkb instructions. */
{"vandn.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDN_VV, MASK_VANDN_VV, match_opcode, 0},
{"vandn.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDN_VX, MASK_VANDN_VX, match_opcode, 0},
--
2.17.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PING] [PATCH 0/3 v2] RISC-V: Add support for Zfbfmin Zvfbfmin and Zvfbfwma extension
2024-06-06 7:59 [PING] [PATCH 0/3 v2] RISC-V: Add support for Zfbfmin Zvfbfmin and Zvfbfwma extension Xiao Zeng
` (2 preceding siblings ...)
2024-06-06 7:59 ` [PATCH 3/3] RISC-V: Add support for Zvfbfwma extension Xiao Zeng
@ 2024-06-06 8:16 ` Nelson Chu
2024-06-06 8:39 ` Xiao Zeng
3 siblings, 1 reply; 7+ messages in thread
From: Nelson Chu @ 2024-06-06 8:16 UTC (permalink / raw)
To: Xiao Zeng; +Cc: binutils, kito.cheng, palmer, zhengyu
[-- Attachment #1: Type: text/plain, Size: 1678 bytes --]
Cool. As I said I forgot that half to single/double precision doesn't need
to care about the rounding mode, the encoding and fcvt.s.bf16 without rm
operand is right.
Looks good, so committed.
Thanks
Nelson
On Thu, Jun 6, 2024 at 3:53 PM Xiao Zeng <zengxiao@eswincomputing.com>
wrote:
> These three extensions are already supported in gcc, and detailed
> information can be found in each patch.
>
> Xiao Zeng (3):
> RISC-V: Add support for Zfbfmin extension
> RISC-V: Add support for Zvfbfmin extension
> RISC-V: Add support for Zvfbfwma extension
>
> bfd/elfxx-riscv.c | 19 +++++++++++++++++++
> gas/NEWS | 6 ++++++
> gas/testsuite/gas/riscv/march-help.l | 3 +++
> gas/testsuite/gas/riscv/zfbfmin.d | 11 +++++++++++
> gas/testsuite/gas/riscv/zfbfmin.s | 6 ++++++
> gas/testsuite/gas/riscv/zvfbfmin.d | 12 ++++++++++++
> gas/testsuite/gas/riscv/zvfbfmin.s | 7 +++++++
> gas/testsuite/gas/riscv/zvfbfwma.d | 12 ++++++++++++
> gas/testsuite/gas/riscv/zvfbfwma.s | 7 +++++++
> include/opcode/riscv-opc.h | 24 ++++++++++++++++++++++++
> include/opcode/riscv.h | 3 +++
> opcodes/riscv-opc.c | 13 +++++++++++++
> 12 files changed, 123 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/zfbfmin.d
> create mode 100644 gas/testsuite/gas/riscv/zfbfmin.s
> create mode 100644 gas/testsuite/gas/riscv/zvfbfmin.d
> create mode 100644 gas/testsuite/gas/riscv/zvfbfmin.s
> create mode 100644 gas/testsuite/gas/riscv/zvfbfwma.d
> create mode 100644 gas/testsuite/gas/riscv/zvfbfwma.s
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: Re: [PING] [PATCH 0/3 v2] RISC-V: Add support for Zfbfmin Zvfbfmin and Zvfbfwma extension
2024-06-06 8:16 ` [PING] [PATCH 0/3 v2] RISC-V: Add support for Zfbfmin Zvfbfmin and " Nelson Chu
@ 2024-06-06 8:39 ` Xiao Zeng
0 siblings, 0 replies; 7+ messages in thread
From: Xiao Zeng @ 2024-06-06 8:39 UTC (permalink / raw)
To: Nelson Chu; +Cc: binutils, kito.cheng, palmer, zhengyu
2024-06-06 16:16 Nelson Chu <nelson@rivosinc.com> wrote:
>
>Cool. As I said I forgot that half to single/double precision doesn't need
>to care about the rounding mode, the encoding and fcvt.s.bf16 without rm
>operand is right.
>Looks good, so committed.
Thanks.
>
>Thanks
>Nelson
>
>On Thu, Jun 6, 2024 at 3:53 PM Xiao Zeng <zengxiao@eswincomputing.com>
>wrote:
>
>> These three extensions are already supported in gcc, and detailed
>> information can be found in each patch.
>>
>> Xiao Zeng (3):
>> RISC-V: Add support for Zfbfmin extension
>> RISC-V: Add support for Zvfbfmin extension
>> RISC-V: Add support for Zvfbfwma extension
>>
>> bfd/elfxx-riscv.c | 19 +++++++++++++++++++
>> gas/NEWS | 6 ++++++
>> gas/testsuite/gas/riscv/march-help.l | 3 +++
>> gas/testsuite/gas/riscv/zfbfmin.d | 11 +++++++++++
>> gas/testsuite/gas/riscv/zfbfmin.s | 6 ++++++
>> gas/testsuite/gas/riscv/zvfbfmin.d | 12 ++++++++++++
>> gas/testsuite/gas/riscv/zvfbfmin.s | 7 +++++++
>> gas/testsuite/gas/riscv/zvfbfwma.d | 12 ++++++++++++
>> gas/testsuite/gas/riscv/zvfbfwma.s | 7 +++++++
>> include/opcode/riscv-opc.h | 24 ++++++++++++++++++++++++
>> include/opcode/riscv.h | 3 +++
>> opcodes/riscv-opc.c | 13 +++++++++++++
>> 12 files changed, 123 insertions(+)
>> create mode 100644 gas/testsuite/gas/riscv/zfbfmin.d
>> create mode 100644 gas/testsuite/gas/riscv/zfbfmin.s
>> create mode 100644 gas/testsuite/gas/riscv/zvfbfmin.d
>> create mode 100644 gas/testsuite/gas/riscv/zvfbfmin.s
>> create mode 100644 gas/testsuite/gas/riscv/zvfbfwma.d
>> create mode 100644 gas/testsuite/gas/riscv/zvfbfwma.s
>>
>> --
>> 2.17.1
>>
>>
Thanks
Xiao Zeng
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/3] RISC-V: Add support for Zvfbfmin extension
2024-05-30 9:41 [PATCH 0/3] " Xiao Zeng
@ 2024-05-30 9:41 ` Xiao Zeng
0 siblings, 0 replies; 7+ messages in thread
From: Xiao Zeng @ 2024-05-30 9:41 UTC (permalink / raw)
To: binutils; +Cc: kito.cheng, palmer, nelson, zhengyu, Xiao Zeng
This implements the Zvfbfmin extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfmin---vector-bf16-converts>
Depending on different usage scenarios, the Zvfbfmin extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies
in scenario of Embedded Processor. In scenario of Application
Processor, it is necessary to explicitly indicate the dependent
'V' extension.
For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zvfbfmin-rv32.d: New test.
* testsuite/gas/riscv/zvfbfmin-rv32.s: New test.
* testsuite/gas/riscv/zvfbfmin-rv64.d: New test.
* testsuite/gas/riscv/zvfbfmin-rv64.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define.
(MASK_VFNCVTBF16_F_F_W): Ditto.
(MATCH_VFWCVTBF16_F_F_V): Ditto.
(MASK_VFWCVTBF16_F_F_V): Ditto.
(DECLARE_INSN): New declarations for Zvfbfmin.
* opcode/riscv.h (enum riscv_insn_class): Add
INSN_CLASS_ZVFBFMIN
opcodes/ChangeLog:
* riscv-opc.c: Add Zvfbfmin instructions.
---
bfd/elfxx-riscv.c | 6 ++++++
gas/NEWS | 2 ++
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/zvfbfmin-rv32.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zvfbfmin-rv32.s | 7 +++++++
gas/testsuite/gas/riscv/zvfbfmin-rv64.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zvfbfmin-rv64.s | 7 +++++++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 4 ++++
10 files changed, 60 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv32.d
create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv32.s
create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv64.d
create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv64.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index d9709a232e6..3d303f02b58 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1192,6 +1192,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"v", "zve64d", check_implicit_always},
{"v", "zvl128b", check_implicit_always},
{"zabha", "a", check_implicit_always},
+ {"zvfbfmin", "zve32f", check_implicit_always},
{"zvfh", "zvfhmin", check_implicit_always},
{"zvfh", "zfhmin", check_implicit_always},
{"zvfhmin", "zve32f", check_implicit_always},
@@ -1394,6 +1395,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2644,6 +2646,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zvbb");
case INSN_CLASS_ZVBC:
return riscv_subset_supports (rps, "zvbc");
+ case INSN_CLASS_ZVFBFMIN:
+ return riscv_subset_supports (rps, "zvfbfmin");
case INSN_CLASS_ZVKB:
return riscv_subset_supports (rps, "zvkb");
case INSN_CLASS_ZVKG:
@@ -2908,6 +2912,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvbb");
case INSN_CLASS_ZVBC:
return _("zvbc");
+ case INSN_CLASS_ZVFBFMIN:
+ return "zvfbfmin";
case INSN_CLASS_ZVKB:
return _("zvkb");
case INSN_CLASS_ZVKG:
diff --git a/gas/NEWS b/gas/NEWS
index b88c54fc5c3..2c75966d0ce 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for RISC-V Zvfbfmin extension with version 1.0.
+
* Add support for RISC-V Zfbfmin extension with version 1.0.
* In x86 Intel syntax undue mnemonic suffixes are now warned about. This is
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 9deaa841622..1a2ac1eaa08 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -59,6 +59,7 @@ All available -march extensions for RISC-V:
zvbb 1.0
zvbc 1.0
zvfh 1.0
+ zvfbfmin 1.0
zvfhmin 1.0
zvkb 1.0
zvkg 1.0
diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv32.d b/gas/testsuite/gas/riscv/zvfbfmin-rv32.d
new file mode 100644
index 00000000000..b52e19d30be
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfmin-rv32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_zvfbfmin
+#objdump: -d
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+4a8e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+488e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+48869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8,v0.t
diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv32.s b/gas/testsuite/gas/riscv/zvfbfmin-rv32.s
new file mode 100644
index 00000000000..9a4493d84d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfmin-rv32.s
@@ -0,0 +1,7 @@
+target:
+ # vfncvtbf16.f.f.w
+ vfncvtbf16.f.f.w v4, v8
+ vfncvtbf16.f.f.w v4, v8, v0.t
+ # vfwcvtbf16.f.f.v
+ vfwcvtbf16.f.f.v v4, v8
+ vfwcvtbf16.f.f.v v4, v8, v0.t
diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv64.d b/gas/testsuite/gas/riscv/zvfbfmin-rv64.d
new file mode 100644
index 00000000000..ce973812fe1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfmin-rv64.d
@@ -0,0 +1,12 @@
+#as: -march=rv64iv_zvfbfmin
+#objdump: -d
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+4a8e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+488e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+48869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8,v0.t
diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv64.s b/gas/testsuite/gas/riscv/zvfbfmin-rv64.s
new file mode 100644
index 00000000000..9a4493d84d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfmin-rv64.s
@@ -0,0 +1,7 @@
+target:
+ # vfncvtbf16.f.f.w
+ vfncvtbf16.f.f.w v4, v8
+ vfncvtbf16.f.f.w v4, v8, v0.t
+ # vfwcvtbf16.f.f.v
+ vfwcvtbf16.f.f.v v4, v8
+ vfwcvtbf16.f.f.v v4, v8, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 26d60bc585e..32b971fb2b3 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2370,6 +2370,11 @@
#define MASK_FCVT_BF16_S 0xfff0007f
#define MATCH_FCVT_S_BF16 0x40600053
#define MASK_FCVT_S_BF16 0xfff0007f
+/* Zvfbfmin intructions. */
+#define MATCH_VFNCVTBF16_F_F_W 0x480e9057
+#define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f
+#define MATCH_VFWCVTBF16_F_F_V 0x48069057
+#define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f
/* Vendor-specific (CORE-V) Xcvmac instructions. */
#define MATCH_CV_MAC 0x9000302b
#define MASK_CV_MAC 0xfe00707f
@@ -3920,6 +3925,9 @@ DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
/* Zfbfmin instructions. */
DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S)
DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16)
+/* Zvfbfmin instructions. */
+DECLARE_INSN(VFNCVTBF16_F_F_W, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W)
+DECLARE_INSN(VFWCVTBF16_F_F_V, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V)
/* Zvbb/Zvkb instructions. */
DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 0e58dbe3d03..4d21b6c3926 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -471,6 +471,7 @@ enum riscv_insn_class
INSN_CLASS_ZVEF,
INSN_CLASS_ZVBB,
INSN_CLASS_ZVBC,
+ INSN_CLASS_ZVFBFMIN,
INSN_CLASS_ZVKB,
INSN_CLASS_ZVKG,
INSN_CLASS_ZVKNED,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 9f99aa6c792..0a470aee7cc 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2041,6 +2041,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
{"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
+/* Zvfbfmin instructions. */
+{"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0},
+{"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0},
+
/* Zvkg instructions. */
{"vghsh.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0},
{"vgmul.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0},
--
2.17.1
^ permalink raw reply [flat|nested] 7+ messages in thread
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2024-06-06 7:59 [PING] [PATCH 0/3 v2] RISC-V: Add support for Zfbfmin Zvfbfmin and Zvfbfwma extension Xiao Zeng
2024-06-06 7:59 ` [PATCH 1/3] RISC-V: Add support for Zfbfmin extension Xiao Zeng
2024-06-06 7:59 ` [PATCH 2/3] RISC-V: Add support for Zvfbfmin extension Xiao Zeng
2024-06-06 7:59 ` [PATCH 3/3] RISC-V: Add support for Zvfbfwma extension Xiao Zeng
2024-06-06 8:16 ` [PING] [PATCH 0/3 v2] RISC-V: Add support for Zfbfmin Zvfbfmin and " Nelson Chu
2024-06-06 8:39 ` Xiao Zeng
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