* [PING^1] [PATCH 0/2] RISC-V: Add support for Zimop and Zcmop extension @ 2024-06-12 1:28 Xiao Zeng 2024-06-12 1:28 ` [PATCH 1/2] RISC-V: Add support for Zimop extension Xiao Zeng 2024-06-12 1:28 ` [PATCH 2/2] RISC-V: Add support for Zcmop extension Xiao Zeng 0 siblings, 2 replies; 7+ messages in thread From: Xiao Zeng @ 2024-06-12 1:28 UTC (permalink / raw) To: binutils; +Cc: kito.cheng, palmer, nelson, zhengyu, Xiao Zeng Xiao Zeng (2): RISC-V: Add support for Zimop extension RISC-V: Add support for Zcmop extension bfd/elfxx-riscv.c | 11 ++ gas/NEWS | 4 + gas/testsuite/gas/riscv/march-help.l | 2 + gas/testsuite/gas/riscv/zcmop.d | 16 +++ gas/testsuite/gas/riscv/zcmop.s | 10 ++ gas/testsuite/gas/riscv/zimop.d | 48 +++++++++ gas/testsuite/gas/riscv/zimop.s | 43 ++++++++ include/opcode/riscv-opc.h | 148 +++++++++++++++++++++++++++ include/opcode/riscv.h | 2 + opcodes/riscv-opc.c | 52 ++++++++++ 10 files changed, 336 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zcmop.d create mode 100644 gas/testsuite/gas/riscv/zcmop.s create mode 100644 gas/testsuite/gas/riscv/zimop.d create mode 100644 gas/testsuite/gas/riscv/zimop.s -- 2.17.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] RISC-V: Add support for Zimop extension 2024-06-12 1:28 [PING^1] [PATCH 0/2] RISC-V: Add support for Zimop and Zcmop extension Xiao Zeng @ 2024-06-12 1:28 ` Xiao Zeng 2024-06-14 6:42 ` [PATCH v1] " Jin Ma 2024-06-12 1:28 ` [PATCH 2/2] RISC-V: Add support for Zcmop extension Xiao Zeng 1 sibling, 1 reply; 7+ messages in thread From: Xiao Zeng @ 2024-06-12 1:28 UTC (permalink / raw) To: binutils; +Cc: kito.cheng, palmer, nelson, zhengyu, Xiao Zeng This implements the Zimop (May-Be-Operations) extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zimop (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zimop.d: New test. * testsuite/gas/riscv/zimop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_MOP_R_0): Define. (MASK_MOP_R_0): Ditto. (MATCH_MOP_R_1): Ditto. (MASK_MOP_R_1): Ditto. (MATCH_MOP_R_2): Ditto. (MASK_MOP_R_2): Ditto. (MATCH_MOP_R_3): Ditto. (MASK_MOP_R_3): Ditto. (MATCH_MOP_R_4): Ditto. (MASK_MOP_R_4): Ditto. (MATCH_MOP_R_5): Ditto. (MASK_MOP_R_5): Ditto. (MATCH_MOP_R_6): Ditto. (MASK_MOP_R_6): Ditto. (MATCH_MOP_R_7): Ditto. (MASK_MOP_R_7): Ditto. (MATCH_MOP_R_8): Ditto. (MASK_MOP_R_8): Ditto. (MATCH_MOP_R_9): Ditto. (MASK_MOP_R_9): Ditto. (MATCH_MOP_R_10): Ditto. (MASK_MOP_R_10): Ditto. (MATCH_MOP_R_11): Ditto. (MASK_MOP_R_11): Ditto. (MATCH_MOP_R_12): Ditto. (MASK_MOP_R_12): Ditto. (MATCH_MOP_R_13): Ditto. (MASK_MOP_R_13): Ditto. (MATCH_MOP_R_14): Ditto. (MASK_MOP_R_14): Ditto. (MATCH_MOP_R_15): Ditto. (MASK_MOP_R_15): Ditto. (MATCH_MOP_R_16): Ditto. (MASK_MOP_R_16): Ditto. (MATCH_MOP_R_17): Ditto. (MASK_MOP_R_17): Ditto. (MATCH_MOP_R_18): Ditto. (MASK_MOP_R_18): Ditto. (MATCH_MOP_R_19): Ditto. (MASK_MOP_R_19): Ditto. (MATCH_MOP_R_20): Ditto. (MASK_MOP_R_20): Ditto. (MATCH_MOP_R_21): Ditto. (MASK_MOP_R_21): Ditto. (MATCH_MOP_R_22): Ditto. (MASK_MOP_R_22): Ditto. (MATCH_MOP_R_23): Ditto. (MASK_MOP_R_23): Ditto. (MATCH_MOP_R_24): Ditto. (MASK_MOP_R_24): Ditto. (MATCH_MOP_R_25): Ditto. (MASK_MOP_R_25): Ditto. (MATCH_MOP_R_26): Ditto. (MASK_MOP_R_26): Ditto. (MATCH_MOP_R_27): Ditto. (MASK_MOP_R_27): Ditto. (MATCH_MOP_R_28): Ditto. (MASK_MOP_R_28): Ditto. (MATCH_MOP_R_29): Ditto. (MASK_MOP_R_29): Ditto. (MATCH_MOP_R_30): Ditto. (MASK_MOP_R_30): Ditto. (MATCH_MOP_R_31): Ditto. (MASK_MOP_R_31): Ditto. (MATCH_MOP_RR_0): Ditto. (MASK_MOP_RR_0): Ditto. (MATCH_MOP_RR_1): Ditto. (MASK_MOP_RR_1): Ditto. (MATCH_MOP_RR_2): Ditto. (MASK_MOP_RR_2): Ditto. (MATCH_MOP_RR_3): Ditto. (MASK_MOP_RR_3): Ditto. (MATCH_MOP_RR_4): Ditto. (MASK_MOP_RR_4): Ditto. (MATCH_MOP_RR_5): Ditto. (MASK_MOP_RR_5): Ditto. (MATCH_MOP_RR_6): Ditto. (MASK_MOP_RR_6): Ditto. (MATCH_MOP_RR_7): Ditto. (MASK_MOP_RR_7): Ditto. (DECLARE_INSN): New declarations for Zimop. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZIMOP. opcodes/ChangeLog: * riscv-opc.c: Add Zimop instructions. --- bfd/elfxx-riscv.c | 5 ++ gas/NEWS | 2 + gas/testsuite/gas/riscv/march-help.l | 1 + gas/testsuite/gas/riscv/zimop.d | 48 +++++++++++ gas/testsuite/gas/riscv/zimop.s | 43 ++++++++++ include/opcode/riscv-opc.h | 122 +++++++++++++++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 42 +++++++++ 8 files changed, 264 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zimop.d create mode 100644 gas/testsuite/gas/riscv/zimop.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 1fe7e5d3df2..87b88513f5c 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1358,6 +1358,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zimop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zaamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2533,6 +2534,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, || riscv_subset_supports (rps, "zca"))); case INSN_CLASS_ZIHINTPAUSE: return riscv_subset_supports (rps, "zihintpause"); + case INSN_CLASS_ZIMOP: + return riscv_subset_supports (rps, "zimop"); case INSN_CLASS_M: return riscv_subset_supports (rps, "m"); case INSN_CLASS_ZMMUL: @@ -2773,6 +2776,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("c' or `zca"); case INSN_CLASS_ZIHINTPAUSE: return "zihintpause"; + case INSN_CLASS_ZIMOP: + return "zimop"; case INSN_CLASS_M: return "m"; case INSN_CLASS_ZMMUL: diff --git a/gas/NEWS b/gas/NEWS index 145ce413bff..e6c1507349f 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -19,6 +19,8 @@ * Remove support for RISC-V privileged spec 1.9.1, but linker can still recognize it in case of linking old objects. +* Add support for RISC-V Zimop extension with version 1.0. + * Add support for RISC-V Zcmp extension with version 1.0. * Add support for RISC-V Zfbfmin extension with version 1.0. diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index dd82752cd30..dace28179b8 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -20,6 +20,7 @@ All available -march extensions for RISC-V: zihintntl 1.0 zihintpause 2.0 zihpm 2.0 + zimop 1.0 zmmul 1.0 zaamo 1.0 zabha 1.0 diff --git a/gas/testsuite/gas/riscv/zimop.d b/gas/testsuite/gas/riscv/zimop.d new file mode 100644 index 00000000000..becb72ca650 --- /dev/null +++ b/gas/testsuite/gas/riscv/zimop.d @@ -0,0 +1,48 @@ +#as: -march=rv64i_zimop +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+81c5c573[ ]+mop.r.0[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+81d5c573[ ]+mop.r.1[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+81e5c573[ ]+mop.r.2[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+81f5c573[ ]+mop.r.3[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+85c5c573[ ]+mop.r.4[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+85d5c573[ ]+mop.r.5[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+85e5c573[ ]+mop.r.6[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+85f5c573[ ]+mop.r.7[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+89c5c573[ ]+mop.r.8[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+89d5c573[ ]+mop.r.9[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+89e5c573[ ]+mop.r.10[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+89f5c573[ ]+mop.r.11[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+8dc5c573[ ]+mop.r.12[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+8dd5c573[ ]+mop.r.13[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+8de5c573[ ]+mop.r.14[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+8df5c573[ ]+mop.r.15[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c1c5c573[ ]+mop.r.16[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c1d5c573[ ]+mop.r.17[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c1e5c573[ ]+mop.r.18[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c1f5c573[ ]+mop.r.19[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c5c5c573[ ]+mop.r.20[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c5d5c573[ ]+mop.r.21[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c5e5c573[ ]+mop.r.22[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c5f5c573[ ]+mop.r.23[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c9c5c573[ ]+mop.r.24[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c9d5c573[ ]+mop.r.25[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c9e5c573[ ]+mop.r.26[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c9f5c573[ ]+mop.r.27[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+cdc5c573[ ]+mop.r.28[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+cdd5c573[ ]+mop.r.29[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+cde5c573[ ]+mop.r.30[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+cdf5c573[ ]+mop.r.31[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+82c5c573[ ]+mop.rr.0[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+86c5c573[ ]+mop.rr.1[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+8ac5c573[ ]+mop.rr.2[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+8ec5c573[ ]+mop.rr.3[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+c2c5c573[ ]+mop.rr.4[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+c6c5c573[ ]+mop.rr.5[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+cac5c573[ ]+mop.rr.6[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+cec5c573[ ]+mop.rr.7[ ]+a0,a1,a2 diff --git a/gas/testsuite/gas/riscv/zimop.s b/gas/testsuite/gas/riscv/zimop.s new file mode 100644 index 00000000000..d244c1fb0fb --- /dev/null +++ b/gas/testsuite/gas/riscv/zimop.s @@ -0,0 +1,43 @@ +target: + # mop.r.n + mop.r.0 a0, a1 + mop.r.1 a0, a1 + mop.r.2 a0, a1 + mop.r.3 a0, a1 + mop.r.4 a0, a1 + mop.r.5 a0, a1 + mop.r.6 a0, a1 + mop.r.7 a0, a1 + mop.r.8 a0, a1 + mop.r.9 a0, a1 + mop.r.10 a0, a1 + mop.r.11 a0, a1 + mop.r.12 a0, a1 + mop.r.13 a0, a1 + mop.r.14 a0, a1 + mop.r.15 a0, a1 + mop.r.16 a0, a1 + mop.r.17 a0, a1 + mop.r.18 a0, a1 + mop.r.19 a0, a1 + mop.r.20 a0, a1 + mop.r.21 a0, a1 + mop.r.22 a0, a1 + mop.r.23 a0, a1 + mop.r.24 a0, a1 + mop.r.25 a0, a1 + mop.r.26 a0, a1 + mop.r.27 a0, a1 + mop.r.28 a0, a1 + mop.r.29 a0, a1 + mop.r.30 a0, a1 + mop.r.31 a0, a1 + # mop.rr.n + mop.rr.0 a0, a1, a2 + mop.rr.1 a0, a1, a2 + mop.rr.2 a0, a1, a2 + mop.rr.3 a0, a1, a2 + mop.rr.4 a0, a1, a2 + mop.rr.5 a0, a1, a2 + mop.rr.6 a0, a1, a2 + mop.rr.7 a0, a1, a2 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index e8c08e800c6..8ba95399430 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2360,6 +2360,87 @@ #define MASK_C_NTL_S1 0xffff #define MATCH_C_NTL_ALL 0x9016 #define MASK_C_NTL_ALL 0xffff +/* Zimop instructions. */ +#define MATCH_MOP_R_0 0x81c04073 +#define MASK_MOP_R_0 0xfff0707f +#define MATCH_MOP_R_1 0x81d04073 +#define MASK_MOP_R_1 0xfff0707f +#define MATCH_MOP_R_2 0x81e04073 +#define MASK_MOP_R_2 0xfff0707f +#define MATCH_MOP_R_3 0x81f04073 +#define MASK_MOP_R_3 0xfff0707f +#define MATCH_MOP_R_4 0x85c04073 +#define MASK_MOP_R_4 0xfff0707f +#define MATCH_MOP_R_5 0x85d04073 +#define MASK_MOP_R_5 0xfff0707f +#define MATCH_MOP_R_6 0x85e04073 +#define MASK_MOP_R_6 0xfff0707f +#define MATCH_MOP_R_7 0x85f04073 +#define MASK_MOP_R_7 0xfff0707f +#define MATCH_MOP_R_8 0x89c04073 +#define MASK_MOP_R_8 0xfff0707f +#define MATCH_MOP_R_9 0x89d04073 +#define MASK_MOP_R_9 0xfff0707f +#define MATCH_MOP_R_10 0x89e04073 +#define MASK_MOP_R_10 0xfff0707f +#define MATCH_MOP_R_11 0x89f04073 +#define MASK_MOP_R_11 0xfff0707f +#define MATCH_MOP_R_12 0x8dc04073 +#define MASK_MOP_R_12 0xfff0707f +#define MATCH_MOP_R_13 0x8dd04073 +#define MASK_MOP_R_13 0xfff0707f +#define MATCH_MOP_R_14 0x8de04073 +#define MASK_MOP_R_14 0xfff0707f +#define MATCH_MOP_R_15 0x8df04073 +#define MASK_MOP_R_15 0xfff0707f +#define MATCH_MOP_R_16 0xc1c04073 +#define MASK_MOP_R_16 0xfff0707f +#define MATCH_MOP_R_17 0xc1d04073 +#define MASK_MOP_R_17 0xfff0707f +#define MATCH_MOP_R_18 0xc1e04073 +#define MASK_MOP_R_18 0xfff0707f +#define MATCH_MOP_R_19 0xc1f04073 +#define MASK_MOP_R_19 0xfff0707f +#define MATCH_MOP_R_20 0xc5c04073 +#define MASK_MOP_R_20 0xfff0707f +#define MATCH_MOP_R_21 0xc5d04073 +#define MASK_MOP_R_21 0xfff0707f +#define MATCH_MOP_R_22 0xc5e04073 +#define MASK_MOP_R_22 0xfff0707f +#define MATCH_MOP_R_23 0xc5f04073 +#define MASK_MOP_R_23 0xfff0707f +#define MATCH_MOP_R_24 0xc9c04073 +#define MASK_MOP_R_24 0xfff0707f +#define MATCH_MOP_R_25 0xc9d04073 +#define MASK_MOP_R_25 0xfff0707f +#define MATCH_MOP_R_26 0xc9e04073 +#define MASK_MOP_R_26 0xfff0707f +#define MATCH_MOP_R_27 0xc9f04073 +#define MASK_MOP_R_27 0xfff0707f +#define MATCH_MOP_R_28 0xcdc04073 +#define MASK_MOP_R_28 0xfff0707f +#define MATCH_MOP_R_29 0xcdd04073 +#define MASK_MOP_R_29 0xfff0707f +#define MATCH_MOP_R_30 0xcde04073 +#define MASK_MOP_R_30 0xfff0707f +#define MATCH_MOP_R_31 0xcdf04073 +#define MASK_MOP_R_31 0xfff0707f +#define MATCH_MOP_RR_0 0x82004073 +#define MASK_MOP_RR_0 0xfe00707f +#define MATCH_MOP_RR_1 0x86004073 +#define MASK_MOP_RR_1 0xfe00707f +#define MATCH_MOP_RR_2 0x8a004073 +#define MASK_MOP_RR_2 0xfe00707f +#define MATCH_MOP_RR_3 0x8e004073 +#define MASK_MOP_RR_3 0xfe00707f +#define MATCH_MOP_RR_4 0xc2004073 +#define MASK_MOP_RR_4 0xfe00707f +#define MATCH_MOP_RR_5 0xc6004073 +#define MASK_MOP_RR_5 0xfe00707f +#define MATCH_MOP_RR_6 0xca004073 +#define MASK_MOP_RR_6 0xfe00707f +#define MATCH_MOP_RR_7 0xce004073 +#define MASK_MOP_RR_7 0xfe00707f /* Zawrs instructions. */ #define MATCH_WRS_NTO 0x00d00073 #define MASK_WRS_NTO 0xffffffff @@ -3981,6 +4062,47 @@ DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, MASK_C_NTL_P1) DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL) DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1) DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL) +/* Zimop instructions. */ +DECLARE_INSN(MOP_R_0, MATCH_MOP_R_0, MASK_MOP_R_0) +DECLARE_INSN(MOP_R_1, MATCH_MOP_R_1, MASK_MOP_R_1) +DECLARE_INSN(MOP_R_2, MATCH_MOP_R_2, MASK_MOP_R_2) +DECLARE_INSN(MOP_R_3, MATCH_MOP_R_3, MASK_MOP_R_3) +DECLARE_INSN(MOP_R_4, MATCH_MOP_R_4, MASK_MOP_R_4) +DECLARE_INSN(MOP_R_5, MATCH_MOP_R_5, MASK_MOP_R_5) +DECLARE_INSN(MOP_R_6, MATCH_MOP_R_6, MASK_MOP_R_6) +DECLARE_INSN(MOP_R_7, MATCH_MOP_R_7, MASK_MOP_R_7) +DECLARE_INSN(MOP_R_8, MATCH_MOP_R_8, MASK_MOP_R_8) +DECLARE_INSN(MOP_R_9, MATCH_MOP_R_9, MASK_MOP_R_9) +DECLARE_INSN(MOP_R_10, MATCH_MOP_R_10, MASK_MOP_R_10) +DECLARE_INSN(MOP_R_11, MATCH_MOP_R_11, MASK_MOP_R_11) +DECLARE_INSN(MOP_R_12, MATCH_MOP_R_12, MASK_MOP_R_12) +DECLARE_INSN(MOP_R_13, MATCH_MOP_R_13, MASK_MOP_R_13) +DECLARE_INSN(MOP_R_14, MATCH_MOP_R_14, MASK_MOP_R_14) +DECLARE_INSN(MOP_R_15, MATCH_MOP_R_15, MASK_MOP_R_15) +DECLARE_INSN(MOP_R_16, MATCH_MOP_R_16, MASK_MOP_R_16) +DECLARE_INSN(MOP_R_17, MATCH_MOP_R_17, MASK_MOP_R_17) +DECLARE_INSN(MOP_R_18, MATCH_MOP_R_18, MASK_MOP_R_18) +DECLARE_INSN(MOP_R_19, MATCH_MOP_R_19, MASK_MOP_R_19) +DECLARE_INSN(MOP_R_20, MATCH_MOP_R_20, MASK_MOP_R_20) +DECLARE_INSN(MOP_R_21, MATCH_MOP_R_21, MASK_MOP_R_21) +DECLARE_INSN(MOP_R_22, MATCH_MOP_R_22, MASK_MOP_R_22) +DECLARE_INSN(MOP_R_23, MATCH_MOP_R_23, MASK_MOP_R_23) +DECLARE_INSN(MOP_R_24, MATCH_MOP_R_24, MASK_MOP_R_24) +DECLARE_INSN(MOP_R_25, MATCH_MOP_R_25, MASK_MOP_R_25) +DECLARE_INSN(MOP_R_26, MATCH_MOP_R_26, MASK_MOP_R_26) +DECLARE_INSN(MOP_R_27, MATCH_MOP_R_27, MASK_MOP_R_27) +DECLARE_INSN(MOP_R_28, MATCH_MOP_R_28, MASK_MOP_R_28) +DECLARE_INSN(MOP_R_29, MATCH_MOP_R_29, MASK_MOP_R_29) +DECLARE_INSN(MOP_R_30, MATCH_MOP_R_30, MASK_MOP_R_30) +DECLARE_INSN(MOP_R_31, MATCH_MOP_R_31, MASK_MOP_R_31) +DECLARE_INSN(MOP_RR_0, MATCH_MOP_RR_0, MASK_MOP_RR_0) +DECLARE_INSN(MOP_RR_1, MATCH_MOP_RR_1, MASK_MOP_RR_1) +DECLARE_INSN(MOP_RR_2, MATCH_MOP_RR_2, MASK_MOP_RR_2) +DECLARE_INSN(MOP_RR_3, MATCH_MOP_RR_3, MASK_MOP_RR_3) +DECLARE_INSN(MOP_RR_4, MATCH_MOP_RR_4, MASK_MOP_RR_4) +DECLARE_INSN(MOP_RR_5, MATCH_MOP_RR_5, MASK_MOP_RR_5) +DECLARE_INSN(MOP_RR_6, MATCH_MOP_RR_6, MASK_MOP_RR_6) +DECLARE_INSN(MOP_RR_7, MATCH_MOP_RR_7, MASK_MOP_RR_7) /* Zawrs instructions. */ DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 33df56d13af..2b2ed0dbce8 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -437,6 +437,7 @@ enum riscv_insn_class INSN_CLASS_ZIHINTNTL, INSN_CLASS_ZIHINTNTL_AND_C, INSN_CLASS_ZIHINTPAUSE, + INSN_CLASS_ZIMOP, INSN_CLASS_ZMMUL, INSN_CLASS_ZAAMO, INSN_CLASS_ZALRSC, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index ff08bd595c0..45269e095a6 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1090,6 +1090,48 @@ const struct riscv_opcode riscv_opcodes[] = {"czero.eqz", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 }, {"czero.nez", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 }, +/* Zimop instructions. */ +{"mop.r.0", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_0, MASK_MOP_R_0, match_opcode, 0 }, +{"mop.r.1", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_1, MASK_MOP_R_1, match_opcode, 0 }, +{"mop.r.2", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_2, MASK_MOP_R_2, match_opcode, 0 }, +{"mop.r.3", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_3, MASK_MOP_R_3, match_opcode, 0 }, +{"mop.r.4", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_4, MASK_MOP_R_4, match_opcode, 0 }, +{"mop.r.5", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_5, MASK_MOP_R_5, match_opcode, 0 }, +{"mop.r.6", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_6, MASK_MOP_R_6, match_opcode, 0 }, +{"mop.r.7", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_7, MASK_MOP_R_7, match_opcode, 0 }, +{"mop.r.8", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_8, MASK_MOP_R_8, match_opcode, 0 }, +{"mop.r.9", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_9, MASK_MOP_R_9, match_opcode, 0 }, +{"mop.r.10", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_10, MASK_MOP_R_10, match_opcode, 0 }, +{"mop.r.11", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_11, MASK_MOP_R_11, match_opcode, 0 }, +{"mop.r.12", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_12, MASK_MOP_R_12, match_opcode, 0 }, +{"mop.r.13", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_13, MASK_MOP_R_13, match_opcode, 0 }, +{"mop.r.14", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_14, MASK_MOP_R_14, match_opcode, 0 }, +{"mop.r.15", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_15, MASK_MOP_R_15, match_opcode, 0 }, +{"mop.r.16", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_16, MASK_MOP_R_16, match_opcode, 0 }, +{"mop.r.17", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_17, MASK_MOP_R_17, match_opcode, 0 }, +{"mop.r.18", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_18, MASK_MOP_R_18, match_opcode, 0 }, +{"mop.r.19", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_19, MASK_MOP_R_19, match_opcode, 0 }, +{"mop.r.20", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_20, MASK_MOP_R_20, match_opcode, 0 }, +{"mop.r.21", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_21, MASK_MOP_R_21, match_opcode, 0 }, +{"mop.r.22", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_22, MASK_MOP_R_22, match_opcode, 0 }, +{"mop.r.23", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_23, MASK_MOP_R_23, match_opcode, 0 }, +{"mop.r.24", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_24, MASK_MOP_R_24, match_opcode, 0 }, +{"mop.r.25", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_25, MASK_MOP_R_25, match_opcode, 0 }, +{"mop.r.26", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_26, MASK_MOP_R_26, match_opcode, 0 }, +{"mop.r.27", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_27, MASK_MOP_R_27, match_opcode, 0 }, +{"mop.r.28", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_28, MASK_MOP_R_28, match_opcode, 0 }, +{"mop.r.29", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_29, MASK_MOP_R_29, match_opcode, 0 }, +{"mop.r.30", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_30, MASK_MOP_R_30, match_opcode, 0 }, +{"mop.r.31", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_31, MASK_MOP_R_31, match_opcode, 0 }, +{"mop.rr.0", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_0, MASK_MOP_RR_0, match_opcode, 0 }, +{"mop.rr.1", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_1, MASK_MOP_RR_1, match_opcode, 0 }, +{"mop.rr.2", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_2, MASK_MOP_RR_2, match_opcode, 0 }, +{"mop.rr.3", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_3, MASK_MOP_RR_3, match_opcode, 0 }, +{"mop.rr.4", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_4, MASK_MOP_RR_4, match_opcode, 0 }, +{"mop.rr.5", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_5, MASK_MOP_RR_5, match_opcode, 0 }, +{"mop.rr.6", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_6, MASK_MOP_RR_6, match_opcode, 0 }, +{"mop.rr.7", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_7, MASK_MOP_RR_7, match_opcode, 0 }, + /* Zawrs instructions. */ {"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 }, {"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 }, -- 2.17.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1] RISC-V: Add support for Zimop extension 2024-06-12 1:28 ` [PATCH 1/2] RISC-V: Add support for Zimop extension Xiao Zeng @ 2024-06-14 6:42 ` Jin Ma 2024-06-14 10:04 ` Xiao Zeng 0 siblings, 1 reply; 7+ messages in thread From: Jin Ma @ 2024-06-14 6:42 UTC (permalink / raw) To: zengxiao; +Cc: binutils, kito.cheng, nelson, palmer, zhengyu, Jin Ma > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h > index ae14e14d427..a6d7e4b24e2 100644 > --- a/include/opcode/riscv-opc.h > +++ b/include/opcode/riscv-opc.h > @@ -2360,6 +2360,87 @@ > #define MASK_C_NTL_S1 0xffff > #define MATCH_C_NTL_ALL 0x9016 > #define MASK_C_NTL_ALL 0xffff > +/* Zimop instructions. */ > +#define MATCH_MOP_R_0 0x81c04073 > +#define MASK_MOP_R_0 0xfff0707f > +#define MATCH_MOP_R_1 0x81d04073 > +#define MASK_MOP_R_1 0xfff0707f > +#define MATCH_MOP_R_2 0x81e04073 > +#define MASK_MOP_R_2 0xfff0707f > +#define MATCH_MOP_R_3 0x81f04073 > +#define MASK_MOP_R_3 0xfff0707f > +#define MATCH_MOP_R_4 0x85c04073 > +#define MASK_MOP_R_4 0xfff0707f > +#define MATCH_MOP_R_5 0x85d04073 > +#define MASK_MOP_R_5 0xfff0707f > +#define MATCH_MOP_R_6 0x85e04073 > +#define MASK_MOP_R_6 0xfff0707f > +#define MATCH_MOP_R_7 0x85f04073 > +#define MASK_MOP_R_7 0xfff0707f > +#define MATCH_MOP_R_8 0x89c04073 > +#define MASK_MOP_R_8 0xfff0707f > +#define MATCH_MOP_R_9 0x89d04073 > +#define MASK_MOP_R_9 0xfff0707f > +#define MATCH_MOP_R_10 0x89e04073 > +#define MASK_MOP_R_10 0xfff0707f > +#define MATCH_MOP_R_11 0x89f04073 > +#define MASK_MOP_R_11 0xfff0707f > +#define MATCH_MOP_R_12 0x8dc04073 > +#define MASK_MOP_R_12 0xfff0707f > +#define MATCH_MOP_R_13 0x8dd04073 > +#define MASK_MOP_R_13 0xfff0707f > +#define MATCH_MOP_R_14 0x8de04073 > +#define MASK_MOP_R_14 0xfff0707f > +#define MATCH_MOP_R_15 0x8df04073 > +#define MASK_MOP_R_15 0xfff0707f > +#define MATCH_MOP_R_16 0xc1c04073 > +#define MASK_MOP_R_16 0xfff0707f > +#define MATCH_MOP_R_17 0xc1d04073 > +#define MASK_MOP_R_17 0xfff0707f > +#define MATCH_MOP_R_18 0xc1e04073 > +#define MASK_MOP_R_18 0xfff0707f > +#define MATCH_MOP_R_19 0xc1f04073 > +#define MASK_MOP_R_19 0xfff0707f > +#define MATCH_MOP_R_20 0xc5c04073 > +#define MASK_MOP_R_20 0xfff0707f > +#define MATCH_MOP_R_21 0xc5d04073 > +#define MASK_MOP_R_21 0xfff0707f > +#define MATCH_MOP_R_22 0xc5e04073 > +#define MASK_MOP_R_22 0xfff0707f > +#define MATCH_MOP_R_23 0xc5f04073 > +#define MASK_MOP_R_23 0xfff0707f > +#define MATCH_MOP_R_24 0xc9c04073 > +#define MASK_MOP_R_24 0xfff0707f > +#define MATCH_MOP_R_25 0xc9d04073 > +#define MASK_MOP_R_25 0xfff0707f > +#define MATCH_MOP_R_26 0xc9e04073 > +#define MASK_MOP_R_26 0xfff0707f > +#define MATCH_MOP_R_27 0xc9f04073 > +#define MASK_MOP_R_27 0xfff0707f > +#define MATCH_MOP_R_28 0xcdc04073 > +#define MASK_MOP_R_28 0xfff0707f > +#define MATCH_MOP_R_29 0xcdd04073 > +#define MASK_MOP_R_29 0xfff0707f > +#define MATCH_MOP_R_30 0xcde04073 > +#define MASK_MOP_R_30 0xfff0707f > +#define MATCH_MOP_R_31 0xcdf04073 > +#define MASK_MOP_R_31 0xfff0707f > +#define MATCH_MOP_RR_0 0x82004073 > +#define MASK_MOP_RR_0 0xfe00707f > +#define MATCH_MOP_RR_1 0x86004073 > +#define MASK_MOP_RR_1 0xfe00707f > +#define MATCH_MOP_RR_2 0x8a004073 > +#define MASK_MOP_RR_2 0xfe00707f > +#define MATCH_MOP_RR_3 0x8e004073 > +#define MASK_MOP_RR_3 0xfe00707f > +#define MATCH_MOP_RR_4 0xc2004073 > +#define MASK_MOP_RR_4 0xfe00707f > +#define MATCH_MOP_RR_5 0xc6004073 > +#define MASK_MOP_RR_5 0xfe00707f > +#define MATCH_MOP_RR_6 0xca004073 > +#define MASK_MOP_RR_6 0xfe00707f > +#define MATCH_MOP_RR_7 0xce004073 > +#define MASK_MOP_RR_7 0xfe00707f Might it be better to remove the redundant MASK_MOP_R_* and MASK_MOP_RR*? Because they are all the same value. > /* Zawrs instructions. */ > #define MATCH_WRS_NTO 0x00d00073 > #define MASK_WRS_NTO 0xffffffff > @@ -3909,6 +3990,47 @@ DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, MASK_C_NTL_P1) > DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL) > DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1) > DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL) > +/* Zimop instructions. */ > +DECLARE_INSN(MOP_R_0, MATCH_MOP_R_0, MASK_MOP_R_0) > +DECLARE_INSN(MOP_R_1, MATCH_MOP_R_1, MASK_MOP_R_1) > +DECLARE_INSN(MOP_R_2, MATCH_MOP_R_2, MASK_MOP_R_2) > +DECLARE_INSN(MOP_R_3, MATCH_MOP_R_3, MASK_MOP_R_3) > +DECLARE_INSN(MOP_R_4, MATCH_MOP_R_4, MASK_MOP_R_4) > +DECLARE_INSN(MOP_R_5, MATCH_MOP_R_5, MASK_MOP_R_5) > +DECLARE_INSN(MOP_R_6, MATCH_MOP_R_6, MASK_MOP_R_6) > +DECLARE_INSN(MOP_R_7, MATCH_MOP_R_7, MASK_MOP_R_7) > +DECLARE_INSN(MOP_R_8, MATCH_MOP_R_8, MASK_MOP_R_8) > +DECLARE_INSN(MOP_R_9, MATCH_MOP_R_9, MASK_MOP_R_9) > +DECLARE_INSN(MOP_R_10, MATCH_MOP_R_10, MASK_MOP_R_10) > +DECLARE_INSN(MOP_R_11, MATCH_MOP_R_11, MASK_MOP_R_11) > +DECLARE_INSN(MOP_R_12, MATCH_MOP_R_12, MASK_MOP_R_12) > +DECLARE_INSN(MOP_R_13, MATCH_MOP_R_13, MASK_MOP_R_13) > +DECLARE_INSN(MOP_R_14, MATCH_MOP_R_14, MASK_MOP_R_14) > +DECLARE_INSN(MOP_R_15, MATCH_MOP_R_15, MASK_MOP_R_15) > +DECLARE_INSN(MOP_R_16, MATCH_MOP_R_16, MASK_MOP_R_16) > +DECLARE_INSN(MOP_R_17, MATCH_MOP_R_17, MASK_MOP_R_17) > +DECLARE_INSN(MOP_R_18, MATCH_MOP_R_18, MASK_MOP_R_18) > +DECLARE_INSN(MOP_R_19, MATCH_MOP_R_19, MASK_MOP_R_19) > +DECLARE_INSN(MOP_R_20, MATCH_MOP_R_20, MASK_MOP_R_20) > +DECLARE_INSN(MOP_R_21, MATCH_MOP_R_21, MASK_MOP_R_21) > +DECLARE_INSN(MOP_R_22, MATCH_MOP_R_22, MASK_MOP_R_22) > +DECLARE_INSN(MOP_R_23, MATCH_MOP_R_23, MASK_MOP_R_23) > +DECLARE_INSN(MOP_R_24, MATCH_MOP_R_24, MASK_MOP_R_24) > +DECLARE_INSN(MOP_R_25, MATCH_MOP_R_25, MASK_MOP_R_25) > +DECLARE_INSN(MOP_R_26, MATCH_MOP_R_26, MASK_MOP_R_26) > +DECLARE_INSN(MOP_R_27, MATCH_MOP_R_27, MASK_MOP_R_27) > +DECLARE_INSN(MOP_R_28, MATCH_MOP_R_28, MASK_MOP_R_28) > +DECLARE_INSN(MOP_R_29, MATCH_MOP_R_29, MASK_MOP_R_29) > +DECLARE_INSN(MOP_R_30, MATCH_MOP_R_30, MASK_MOP_R_30) > +DECLARE_INSN(MOP_R_31, MATCH_MOP_R_31, MASK_MOP_R_31) > +DECLARE_INSN(MOP_RR_0, MATCH_MOP_RR_0, MASK_MOP_RR_0) > +DECLARE_INSN(MOP_RR_1, MATCH_MOP_RR_1, MASK_MOP_RR_1) > +DECLARE_INSN(MOP_RR_2, MATCH_MOP_RR_2, MASK_MOP_RR_2) > +DECLARE_INSN(MOP_RR_3, MATCH_MOP_RR_3, MASK_MOP_RR_3) > +DECLARE_INSN(MOP_RR_4, MATCH_MOP_RR_4, MASK_MOP_RR_4) > +DECLARE_INSN(MOP_RR_5, MATCH_MOP_RR_5, MASK_MOP_RR_5) > +DECLARE_INSN(MOP_RR_6, MATCH_MOP_RR_6, MASK_MOP_RR_6) > +DECLARE_INSN(MOP_RR_7, MATCH_MOP_RR_7, MASK_MOP_RR_7) Might not need these? > /* Zawrs instructions. */ > DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) > DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > index d967b78f706..2434810c26e 100644 > --- a/include/opcode/riscv.h > +++ b/include/opcode/riscv.h > @@ -435,6 +435,7 @@ enum riscv_insn_class > INSN_CLASS_ZIHINTNTL, > INSN_CLASS_ZIHINTNTL_AND_C, > INSN_CLASS_ZIHINTPAUSE, > + INSN_CLASS_ZIMOP, > INSN_CLASS_ZMMUL, > INSN_CLASS_ZAWRS, > INSN_CLASS_F_INX, > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 38a4624da7e..f78ca18a6ee 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -1085,6 +1085,48 @@ const struct riscv_opcode riscv_opcodes[] = > {"czero.eqz", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 }, > {"czero.nez", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 }, > > +/* Zimop instructions. */ > +{"mop.r.0", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_0, MASK_MOP_R_0, match_opcode, 0 }, > +{"mop.r.1", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_1, MASK_MOP_R_1, match_opcode, 0 }, > +{"mop.r.2", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_2, MASK_MOP_R_2, match_opcode, 0 }, > +{"mop.r.3", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_3, MASK_MOP_R_3, match_opcode, 0 }, > +{"mop.r.4", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_4, MASK_MOP_R_4, match_opcode, 0 }, > +{"mop.r.5", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_5, MASK_MOP_R_5, match_opcode, 0 }, > +{"mop.r.6", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_6, MASK_MOP_R_6, match_opcode, 0 }, > +{"mop.r.7", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_7, MASK_MOP_R_7, match_opcode, 0 }, > +{"mop.r.8", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_8, MASK_MOP_R_8, match_opcode, 0 }, > +{"mop.r.9", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_9, MASK_MOP_R_9, match_opcode, 0 }, > +{"mop.r.10", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_10, MASK_MOP_R_10, match_opcode, 0 }, > +{"mop.r.11", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_11, MASK_MOP_R_11, match_opcode, 0 }, > +{"mop.r.12", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_12, MASK_MOP_R_12, match_opcode, 0 }, > +{"mop.r.13", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_13, MASK_MOP_R_13, match_opcode, 0 }, > +{"mop.r.14", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_14, MASK_MOP_R_14, match_opcode, 0 }, > +{"mop.r.15", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_15, MASK_MOP_R_15, match_opcode, 0 }, > +{"mop.r.16", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_16, MASK_MOP_R_16, match_opcode, 0 }, > +{"mop.r.17", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_17, MASK_MOP_R_17, match_opcode, 0 }, > +{"mop.r.18", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_18, MASK_MOP_R_18, match_opcode, 0 }, > +{"mop.r.19", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_19, MASK_MOP_R_19, match_opcode, 0 }, > +{"mop.r.20", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_20, MASK_MOP_R_20, match_opcode, 0 }, > +{"mop.r.21", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_21, MASK_MOP_R_21, match_opcode, 0 }, > +{"mop.r.22", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_22, MASK_MOP_R_22, match_opcode, 0 }, > +{"mop.r.23", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_23, MASK_MOP_R_23, match_opcode, 0 }, > +{"mop.r.24", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_24, MASK_MOP_R_24, match_opcode, 0 }, > +{"mop.r.25", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_25, MASK_MOP_R_25, match_opcode, 0 }, > +{"mop.r.26", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_26, MASK_MOP_R_26, match_opcode, 0 }, > +{"mop.r.27", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_27, MASK_MOP_R_27, match_opcode, 0 }, > +{"mop.r.28", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_28, MASK_MOP_R_28, match_opcode, 0 }, > +{"mop.r.29", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_29, MASK_MOP_R_29, match_opcode, 0 }, > +{"mop.r.30", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_30, MASK_MOP_R_30, match_opcode, 0 }, > +{"mop.r.31", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_31, MASK_MOP_R_31, match_opcode, 0 }, > +{"mop.rr.0", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_0, MASK_MOP_RR_0, match_opcode, 0 }, > +{"mop.rr.1", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_1, MASK_MOP_RR_1, match_opcode, 0 }, > +{"mop.rr.2", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_2, MASK_MOP_RR_2, match_opcode, 0 }, > +{"mop.rr.3", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_3, MASK_MOP_RR_3, match_opcode, 0 }, > +{"mop.rr.4", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_4, MASK_MOP_RR_4, match_opcode, 0 }, > +{"mop.rr.5", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_5, MASK_MOP_RR_5, match_opcode, 0 }, > +{"mop.rr.6", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_6, MASK_MOP_RR_6, match_opcode, 0 }, > +{"mop.rr.7", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_7, MASK_MOP_RR_7, match_opcode, 0 }, > + > /* Zawrs instructions. */ > {"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 }, > {"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 }, I noticed that Lyut submitted a similar patch last year, and I think he may have more suggestions. Ref: https://sourceware.org/pipermail/binutils/2023-December/131046.html BR, Jin ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: Re: [PATCH v1] RISC-V: Add support for Zimop extension 2024-06-14 6:42 ` [PATCH v1] " Jin Ma @ 2024-06-14 10:04 ` Xiao Zeng 0 siblings, 0 replies; 7+ messages in thread From: Xiao Zeng @ 2024-06-14 10:04 UTC (permalink / raw) To: Jin Ma; +Cc: binutils, kito.cheng, Nelson Chu, palmer, zhengyu, Jin Ma 2024-06-14 14:42 Jin Ma <jinma@linux.alibaba.com> wrote: > >> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h >> index ae14e14d427..a6d7e4b24e2 100644 >> --- a/include/opcode/riscv-opc.h >> +++ b/include/opcode/riscv-opc.h >> @@ -2360,6 +2360,87 @@ >> #define MASK_C_NTL_S1 0xffff >> #define MATCH_C_NTL_ALL 0x9016 >> #define MASK_C_NTL_ALL 0xffff >> +/* Zimop instructions. */ >> +#define MATCH_MOP_R_0 0x81c04073 >> +#define MASK_MOP_R_0 0xfff0707f >> +#define MATCH_MOP_R_1 0x81d04073 >> +#define MASK_MOP_R_1 0xfff0707f >> +#define MATCH_MOP_R_2 0x81e04073 >> +#define MASK_MOP_R_2 0xfff0707f >> +#define MATCH_MOP_R_3 0x81f04073 >> +#define MASK_MOP_R_3 0xfff0707f >> +#define MATCH_MOP_R_4 0x85c04073 >> +#define MASK_MOP_R_4 0xfff0707f >> +#define MATCH_MOP_R_5 0x85d04073 >> +#define MASK_MOP_R_5 0xfff0707f >> +#define MATCH_MOP_R_6 0x85e04073 >> +#define MASK_MOP_R_6 0xfff0707f >> +#define MATCH_MOP_R_7 0x85f04073 >> +#define MASK_MOP_R_7 0xfff0707f >> +#define MATCH_MOP_R_8 0x89c04073 >> +#define MASK_MOP_R_8 0xfff0707f >> +#define MATCH_MOP_R_9 0x89d04073 >> +#define MASK_MOP_R_9 0xfff0707f >> +#define MATCH_MOP_R_10 0x89e04073 >> +#define MASK_MOP_R_10 0xfff0707f >> +#define MATCH_MOP_R_11 0x89f04073 >> +#define MASK_MOP_R_11 0xfff0707f >> +#define MATCH_MOP_R_12 0x8dc04073 >> +#define MASK_MOP_R_12 0xfff0707f >> +#define MATCH_MOP_R_13 0x8dd04073 >> +#define MASK_MOP_R_13 0xfff0707f >> +#define MATCH_MOP_R_14 0x8de04073 >> +#define MASK_MOP_R_14 0xfff0707f >> +#define MATCH_MOP_R_15 0x8df04073 >> +#define MASK_MOP_R_15 0xfff0707f >> +#define MATCH_MOP_R_16 0xc1c04073 >> +#define MASK_MOP_R_16 0xfff0707f >> +#define MATCH_MOP_R_17 0xc1d04073 >> +#define MASK_MOP_R_17 0xfff0707f >> +#define MATCH_MOP_R_18 0xc1e04073 >> +#define MASK_MOP_R_18 0xfff0707f >> +#define MATCH_MOP_R_19 0xc1f04073 >> +#define MASK_MOP_R_19 0xfff0707f >> +#define MATCH_MOP_R_20 0xc5c04073 >> +#define MASK_MOP_R_20 0xfff0707f >> +#define MATCH_MOP_R_21 0xc5d04073 >> +#define MASK_MOP_R_21 0xfff0707f >> +#define MATCH_MOP_R_22 0xc5e04073 >> +#define MASK_MOP_R_22 0xfff0707f >> +#define MATCH_MOP_R_23 0xc5f04073 >> +#define MASK_MOP_R_23 0xfff0707f >> +#define MATCH_MOP_R_24 0xc9c04073 >> +#define MASK_MOP_R_24 0xfff0707f >> +#define MATCH_MOP_R_25 0xc9d04073 >> +#define MASK_MOP_R_25 0xfff0707f >> +#define MATCH_MOP_R_26 0xc9e04073 >> +#define MASK_MOP_R_26 0xfff0707f >> +#define MATCH_MOP_R_27 0xc9f04073 >> +#define MASK_MOP_R_27 0xfff0707f >> +#define MATCH_MOP_R_28 0xcdc04073 >> +#define MASK_MOP_R_28 0xfff0707f >> +#define MATCH_MOP_R_29 0xcdd04073 >> +#define MASK_MOP_R_29 0xfff0707f >> +#define MATCH_MOP_R_30 0xcde04073 >> +#define MASK_MOP_R_30 0xfff0707f >> +#define MATCH_MOP_R_31 0xcdf04073 >> +#define MASK_MOP_R_31 0xfff0707f >> +#define MATCH_MOP_RR_0 0x82004073 >> +#define MASK_MOP_RR_0 0xfe00707f >> +#define MATCH_MOP_RR_1 0x86004073 >> +#define MASK_MOP_RR_1 0xfe00707f >> +#define MATCH_MOP_RR_2 0x8a004073 >> +#define MASK_MOP_RR_2 0xfe00707f >> +#define MATCH_MOP_RR_3 0x8e004073 >> +#define MASK_MOP_RR_3 0xfe00707f >> +#define MATCH_MOP_RR_4 0xc2004073 >> +#define MASK_MOP_RR_4 0xfe00707f >> +#define MATCH_MOP_RR_5 0xc6004073 >> +#define MASK_MOP_RR_5 0xfe00707f >> +#define MATCH_MOP_RR_6 0xca004073 >> +#define MASK_MOP_RR_6 0xfe00707f >> +#define MATCH_MOP_RR_7 0xce004073 >> +#define MASK_MOP_RR_7 0xfe00707f > >Might it be better to remove the redundant MASK_MOP_R_* and MASK_MOP_RR*? >Because they are all the same value. Yes. > > >> /* Zawrs instructions. */ >> #define MATCH_WRS_NTO 0x00d00073 >> #define MASK_WRS_NTO 0xffffffff >> @@ -3909,6 +3990,47 @@ DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, MASK_C_NTL_P1) >> DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL) >> DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1) >> DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL) >> +/* Zimop instructions. */ >> +DECLARE_INSN(MOP_R_0, MATCH_MOP_R_0, MASK_MOP_R_0) >> +DECLARE_INSN(MOP_R_1, MATCH_MOP_R_1, MASK_MOP_R_1) >> +DECLARE_INSN(MOP_R_2, MATCH_MOP_R_2, MASK_MOP_R_2) >> +DECLARE_INSN(MOP_R_3, MATCH_MOP_R_3, MASK_MOP_R_3) >> +DECLARE_INSN(MOP_R_4, MATCH_MOP_R_4, MASK_MOP_R_4) >> +DECLARE_INSN(MOP_R_5, MATCH_MOP_R_5, MASK_MOP_R_5) >> +DECLARE_INSN(MOP_R_6, MATCH_MOP_R_6, MASK_MOP_R_6) >> +DECLARE_INSN(MOP_R_7, MATCH_MOP_R_7, MASK_MOP_R_7) >> +DECLARE_INSN(MOP_R_8, MATCH_MOP_R_8, MASK_MOP_R_8) >> +DECLARE_INSN(MOP_R_9, MATCH_MOP_R_9, MASK_MOP_R_9) >> +DECLARE_INSN(MOP_R_10, MATCH_MOP_R_10, MASK_MOP_R_10) >> +DECLARE_INSN(MOP_R_11, MATCH_MOP_R_11, MASK_MOP_R_11) >> +DECLARE_INSN(MOP_R_12, MATCH_MOP_R_12, MASK_MOP_R_12) >> +DECLARE_INSN(MOP_R_13, MATCH_MOP_R_13, MASK_MOP_R_13) >> +DECLARE_INSN(MOP_R_14, MATCH_MOP_R_14, MASK_MOP_R_14) >> +DECLARE_INSN(MOP_R_15, MATCH_MOP_R_15, MASK_MOP_R_15) >> +DECLARE_INSN(MOP_R_16, MATCH_MOP_R_16, MASK_MOP_R_16) >> +DECLARE_INSN(MOP_R_17, MATCH_MOP_R_17, MASK_MOP_R_17) >> +DECLARE_INSN(MOP_R_18, MATCH_MOP_R_18, MASK_MOP_R_18) >> +DECLARE_INSN(MOP_R_19, MATCH_MOP_R_19, MASK_MOP_R_19) >> +DECLARE_INSN(MOP_R_20, MATCH_MOP_R_20, MASK_MOP_R_20) >> +DECLARE_INSN(MOP_R_21, MATCH_MOP_R_21, MASK_MOP_R_21) >> +DECLARE_INSN(MOP_R_22, MATCH_MOP_R_22, MASK_MOP_R_22) >> +DECLARE_INSN(MOP_R_23, MATCH_MOP_R_23, MASK_MOP_R_23) >> +DECLARE_INSN(MOP_R_24, MATCH_MOP_R_24, MASK_MOP_R_24) >> +DECLARE_INSN(MOP_R_25, MATCH_MOP_R_25, MASK_MOP_R_25) >> +DECLARE_INSN(MOP_R_26, MATCH_MOP_R_26, MASK_MOP_R_26) >> +DECLARE_INSN(MOP_R_27, MATCH_MOP_R_27, MASK_MOP_R_27) >> +DECLARE_INSN(MOP_R_28, MATCH_MOP_R_28, MASK_MOP_R_28) >> +DECLARE_INSN(MOP_R_29, MATCH_MOP_R_29, MASK_MOP_R_29) >> +DECLARE_INSN(MOP_R_30, MATCH_MOP_R_30, MASK_MOP_R_30) >> +DECLARE_INSN(MOP_R_31, MATCH_MOP_R_31, MASK_MOP_R_31) >> +DECLARE_INSN(MOP_RR_0, MATCH_MOP_RR_0, MASK_MOP_RR_0) >> +DECLARE_INSN(MOP_RR_1, MATCH_MOP_RR_1, MASK_MOP_RR_1) >> +DECLARE_INSN(MOP_RR_2, MATCH_MOP_RR_2, MASK_MOP_RR_2) >> +DECLARE_INSN(MOP_RR_3, MATCH_MOP_RR_3, MASK_MOP_RR_3) >> +DECLARE_INSN(MOP_RR_4, MATCH_MOP_RR_4, MASK_MOP_RR_4) >> +DECLARE_INSN(MOP_RR_5, MATCH_MOP_RR_5, MASK_MOP_RR_5) >> +DECLARE_INSN(MOP_RR_6, MATCH_MOP_RR_6, MASK_MOP_RR_6) >> +DECLARE_INSN(MOP_RR_7, MATCH_MOP_RR_7, MASK_MOP_RR_7) > >Might not need these? Yes. > >> /* Zawrs instructions. */ >> DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) >> DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) >> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h >> index d967b78f706..2434810c26e 100644 >> --- a/include/opcode/riscv.h >> +++ b/include/opcode/riscv.h >> @@ -435,6 +435,7 @@ enum riscv_insn_class >> INSN_CLASS_ZIHINTNTL, >> INSN_CLASS_ZIHINTNTL_AND_C, >> INSN_CLASS_ZIHINTPAUSE, >> + INSN_CLASS_ZIMOP, >> INSN_CLASS_ZMMUL, >> INSN_CLASS_ZAWRS, >> INSN_CLASS_F_INX, >> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c >> index 38a4624da7e..f78ca18a6ee 100644 >> --- a/opcodes/riscv-opc.c >> +++ b/opcodes/riscv-opc.c >> @@ -1085,6 +1085,48 @@ const struct riscv_opcode riscv_opcodes[] = >> {"czero.eqz", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 }, >> {"czero.nez", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 }, >> >> +/* Zimop instructions. */ >> +{"mop.r.0", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_0, MASK_MOP_R_0, match_opcode, 0 }, >> +{"mop.r.1", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_1, MASK_MOP_R_1, match_opcode, 0 }, >> +{"mop.r.2", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_2, MASK_MOP_R_2, match_opcode, 0 }, >> +{"mop.r.3", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_3, MASK_MOP_R_3, match_opcode, 0 }, >> +{"mop.r.4", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_4, MASK_MOP_R_4, match_opcode, 0 }, >> +{"mop.r.5", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_5, MASK_MOP_R_5, match_opcode, 0 }, >> +{"mop.r.6", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_6, MASK_MOP_R_6, match_opcode, 0 }, >> +{"mop.r.7", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_7, MASK_MOP_R_7, match_opcode, 0 }, >> +{"mop.r.8", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_8, MASK_MOP_R_8, match_opcode, 0 }, >> +{"mop.r.9", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_9, MASK_MOP_R_9, match_opcode, 0 }, >> +{"mop.r.10", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_10, MASK_MOP_R_10, match_opcode, 0 }, >> +{"mop.r.11", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_11, MASK_MOP_R_11, match_opcode, 0 }, >> +{"mop.r.12", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_12, MASK_MOP_R_12, match_opcode, 0 }, >> +{"mop.r.13", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_13, MASK_MOP_R_13, match_opcode, 0 }, >> +{"mop.r.14", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_14, MASK_MOP_R_14, match_opcode, 0 }, >> +{"mop.r.15", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_15, MASK_MOP_R_15, match_opcode, 0 }, >> +{"mop.r.16", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_16, MASK_MOP_R_16, match_opcode, 0 }, >> +{"mop.r.17", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_17, MASK_MOP_R_17, match_opcode, 0 }, >> +{"mop.r.18", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_18, MASK_MOP_R_18, match_opcode, 0 }, >> +{"mop.r.19", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_19, MASK_MOP_R_19, match_opcode, 0 }, >> +{"mop.r.20", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_20, MASK_MOP_R_20, match_opcode, 0 }, >> +{"mop.r.21", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_21, MASK_MOP_R_21, match_opcode, 0 }, >> +{"mop.r.22", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_22, MASK_MOP_R_22, match_opcode, 0 }, >> +{"mop.r.23", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_23, MASK_MOP_R_23, match_opcode, 0 }, >> +{"mop.r.24", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_24, MASK_MOP_R_24, match_opcode, 0 }, >> +{"mop.r.25", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_25, MASK_MOP_R_25, match_opcode, 0 }, >> +{"mop.r.26", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_26, MASK_MOP_R_26, match_opcode, 0 }, >> +{"mop.r.27", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_27, MASK_MOP_R_27, match_opcode, 0 }, >> +{"mop.r.28", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_28, MASK_MOP_R_28, match_opcode, 0 }, >> +{"mop.r.29", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_29, MASK_MOP_R_29, match_opcode, 0 }, >> +{"mop.r.30", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_30, MASK_MOP_R_30, match_opcode, 0 }, >> +{"mop.r.31", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_31, MASK_MOP_R_31, match_opcode, 0 }, >> +{"mop.rr.0", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_0, MASK_MOP_RR_0, match_opcode, 0 }, >> +{"mop.rr.1", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_1, MASK_MOP_RR_1, match_opcode, 0 }, >> +{"mop.rr.2", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_2, MASK_MOP_RR_2, match_opcode, 0 }, >> +{"mop.rr.3", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_3, MASK_MOP_RR_3, match_opcode, 0 }, >> +{"mop.rr.4", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_4, MASK_MOP_RR_4, match_opcode, 0 }, >> +{"mop.rr.5", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_5, MASK_MOP_RR_5, match_opcode, 0 }, >> +{"mop.rr.6", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_6, MASK_MOP_RR_6, match_opcode, 0 }, >> +{"mop.rr.7", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_7, MASK_MOP_RR_7, match_opcode, 0 }, >> + >> /* Zawrs instructions. */ >> {"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 }, >> {"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 }, > >I noticed that Lyut submitted a similar patch last year, and I think he may have more suggestions. Thanks for your mention, I will go to help review. > >Ref: >https://sourceware.org/pipermail/binutils/2023-December/131046.html > >BR, >Jin Thanks Xiao Zeng ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] RISC-V: Add support for Zcmop extension 2024-06-12 1:28 [PING^1] [PATCH 0/2] RISC-V: Add support for Zimop and Zcmop extension Xiao Zeng 2024-06-12 1:28 ` [PATCH 1/2] RISC-V: Add support for Zimop extension Xiao Zeng @ 2024-06-12 1:28 ` Xiao Zeng 1 sibling, 0 replies; 7+ messages in thread From: Xiao Zeng @ 2024-06-12 1:28 UTC (permalink / raw) To: binutils; +Cc: kito.cheng, palmer, nelson, zhengyu, Xiao Zeng This implements the Zcmop (Compressed Zimop) extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc> 1 The Zcmop extension requires the Zca extension. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zcmop. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zcmop.d: New test. * testsuite/gas/riscv/zcmop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_C_MOP_1): Define. (MASK_C_MOP_1): Ditto. (MATCH_C_MOP_3): Ditto. (MASK_C_MOP_3): Ditto. (MATCH_C_MOP_5): Ditto. (MASK_C_MOP_5): Ditto. (MATCH_C_MOP_7): Ditto. (MASK_C_MOP_7): Ditto. (MATCH_C_MOP_9): Ditto. (MASK_C_MOP_9): Ditto. (MATCH_C_MOP_11): Ditto. (MASK_C_MOP_11): Ditto. (MATCH_C_MOP_13): Ditto. (MASK_C_MOP_13): Ditto. (MATCH_C_MOP_15): Ditto. (MASK_C_MOP_15): Ditto. (DECLARE_INSN): New declarations for Zcmop. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZCMOP. opcodes/ChangeLog: * riscv-opc.c: Add Zcmop instructions. --- bfd/elfxx-riscv.c | 6 ++++++ gas/NEWS | 2 ++ gas/testsuite/gas/riscv/march-help.l | 1 + gas/testsuite/gas/riscv/zcmop.d | 16 ++++++++++++++++ gas/testsuite/gas/riscv/zcmop.s | 10 ++++++++++ include/opcode/riscv-opc.h | 26 ++++++++++++++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 10 ++++++++++ 8 files changed, 72 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zcmop.d create mode 100644 gas/testsuite/gas/riscv/zcmop.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 87b88513f5c..2dcd6c62a1b 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1271,6 +1271,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zcf", "zca", check_implicit_always}, {"zcd", "zca", check_implicit_always}, {"zcb", "zca", check_implicit_always}, + {"zcmop", "zca", check_implicit_always}, {"zcmp", "zca", check_implicit_always}, {"smaia", "ssaia", check_implicit_always}, {"smcntrpmf", "zicsr", check_implicit_always}, @@ -1432,6 +1433,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zcb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zcmop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2683,6 +2685,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, case INSN_CLASS_ZCB_AND_ZMMUL: return (riscv_subset_supports (rps, "zcb") && riscv_subset_supports (rps, "zmmul")); + case INSN_CLASS_ZCMOP: + return riscv_subset_supports (rps, "zcmop"); case INSN_CLASS_ZCMP: return riscv_subset_supports (rps, "zcmp"); case INSN_CLASS_SVINVAL: @@ -2955,6 +2959,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zcb' and `zbb"); case INSN_CLASS_ZCB_AND_ZMMUL: return _("zcb' and `zmmul', or `zcb' and `m"); + case INSN_CLASS_ZCMOP: + return "zcmop"; case INSN_CLASS_ZCMP: return "zcmp"; case INSN_CLASS_SVINVAL: diff --git a/gas/NEWS b/gas/NEWS index e6c1507349f..4d21dd5362b 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -21,6 +21,8 @@ * Add support for RISC-V Zimop extension with version 1.0. +* Add support for RISC-V Zcmop extension with version 1.0. + * Add support for RISC-V Zcmp extension with version 1.0. * Add support for RISC-V Zfbfmin extension with version 1.0. diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index dace28179b8..817b9aec5f3 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -94,6 +94,7 @@ All available -march extensions for RISC-V: zcb 1.0 zcf 1.0 zcd 1.0 + zcmop 1.0 zcmp 1.0 smaia 1.0 smcntrpmf 1.0 diff --git a/gas/testsuite/gas/riscv/zcmop.d b/gas/testsuite/gas/riscv/zcmop.d new file mode 100644 index 00000000000..5f608c676c3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmop.d @@ -0,0 +1,16 @@ +#as: -march=rv64i_zcmop +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+6081[ ]+c.mop.1 +[ ]+[0-9a-f]+:[ ]+6181[ ]+c.mop.3 +[ ]+[0-9a-f]+:[ ]+6281[ ]+c.mop.5 +[ ]+[0-9a-f]+:[ ]+6381[ ]+c.mop.7 +[ ]+[0-9a-f]+:[ ]+6481[ ]+c.mop.9 +[ ]+[0-9a-f]+:[ ]+6581[ ]+c.mop.11 +[ ]+[0-9a-f]+:[ ]+6681[ ]+c.mop.13 +[ ]+[0-9a-f]+:[ ]+6781[ ]+c.mop.15 diff --git a/gas/testsuite/gas/riscv/zcmop.s b/gas/testsuite/gas/riscv/zcmop.s new file mode 100644 index 00000000000..4b02e694f46 --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmop.s @@ -0,0 +1,10 @@ +target: + # c.mop.n + c.mop.1 + c.mop.3 + c.mop.5 + c.mop.7 + c.mop.9 + c.mop.11 + c.mop.13 + c.mop.15 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 8ba95399430..c7403d42734 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2271,6 +2271,23 @@ #define MASK_C_NOT 0xfc7f #define MATCH_C_MUL 0x9c41 #define MASK_C_MUL 0xfc63 +/* Zcmop instructions. */ +#define MATCH_C_MOP_1 0x6081 +#define MASK_C_MOP_1 0xffff +#define MATCH_C_MOP_3 0x6181 +#define MASK_C_MOP_3 0xffff +#define MATCH_C_MOP_5 0x6281 +#define MASK_C_MOP_5 0xffff +#define MATCH_C_MOP_7 0x6381 +#define MASK_C_MOP_7 0xffff +#define MATCH_C_MOP_9 0x6481 +#define MASK_C_MOP_9 0xffff +#define MATCH_C_MOP_11 0x6581 +#define MASK_C_MOP_11 0xffff +#define MATCH_C_MOP_13 0x6681 +#define MASK_C_MOP_13 0xffff +#define MATCH_C_MOP_15 0x6781 +#define MASK_C_MOP_15 0xffff /* Zcmp instructions. */ #define MATCH_CM_PUSH 0xb802 #define MASK_CM_PUSH 0xff03 @@ -4176,6 +4193,15 @@ DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU) DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH) DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB) DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH) +/* Zcmop instructions. */ +DECLARE_INSN(c_mop_1, MATCH_C_MOP_1, MASK_C_MOP_1) +DECLARE_INSN(c_mop_3, MATCH_C_MOP_3, MASK_C_MOP_3) +DECLARE_INSN(c_mop_5, MATCH_C_MOP_5, MASK_C_MOP_5) +DECLARE_INSN(c_mop_7, MATCH_C_MOP_7, MASK_C_MOP_7) +DECLARE_INSN(c_mop_9, MATCH_C_MOP_9, MASK_C_MOP_9) +DECLARE_INSN(c_mop_11, MATCH_C_MOP_11, MASK_C_MOP_11) +DECLARE_INSN(c_mop_13, MATCH_C_MOP_13, MASK_C_MOP_13) +DECLARE_INSN(c_mop_15, MATCH_C_MOP_15, MASK_C_MOP_15) /* Zcmp instructions. */ DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH) DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 2b2ed0dbce8..8f546772de0 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -487,6 +487,7 @@ enum riscv_insn_class INSN_CLASS_ZCB_AND_ZBA, INSN_CLASS_ZCB_AND_ZBB, INSN_CLASS_ZCB_AND_ZMMUL, + INSN_CLASS_ZCMOP, INSN_CLASS_ZCMP, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 45269e095a6..78144fca675 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2137,6 +2137,16 @@ const struct riscv_opcode riscv_opcodes[] = {"c.zext.b", 0, INSN_CLASS_ZCB, "Cs", MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, 0 }, {"c.sext.w", 64, INSN_CLASS_ZCB, "d", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, +/* Zcmop instructions. */ +{"c.mop.1", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_1, MASK_C_MOP_1, match_opcode, 0 }, +{"c.mop.3", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_3, MASK_C_MOP_3, match_opcode, 0 }, +{"c.mop.5", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_5, MASK_C_MOP_5, match_opcode, 0 }, +{"c.mop.7", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_7, MASK_C_MOP_7, match_opcode, 0 }, +{"c.mop.9", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_9, MASK_C_MOP_9, match_opcode, 0 }, +{"c.mop.11", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_11, MASK_C_MOP_11, match_opcode, 0 }, +{"c.mop.13", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_13, MASK_C_MOP_13, match_opcode, 0 }, +{"c.mop.15", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_15, MASK_C_MOP_15, match_opcode, 0 }, + /* Zcmp instructions. */ {"cm.push", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_PUSH, MASK_CM_PUSH, match_opcode, 0 }, {"cm.pop", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POP, MASK_CM_POP, match_opcode, 0 }, -- 2.17.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PING] [PATCH 0/2] RISC-V: Add support for Zimop and Zcmop extension @ 2024-06-06 9:32 Xiao Zeng 2024-06-06 9:32 ` [PATCH 2/2] RISC-V: Add support for " Xiao Zeng 0 siblings, 1 reply; 7+ messages in thread From: Xiao Zeng @ 2024-06-06 9:32 UTC (permalink / raw) To: binutils; +Cc: kito.cheng, palmer, nelson, zhengyu, Xiao Zeng Xiao Zeng (2): RISC-V: Add support for Zimop extension RISC-V: Add support for Zcmop extension bfd/elfxx-riscv.c | 11 ++ gas/NEWS | 4 + gas/testsuite/gas/riscv/march-help.l | 2 + gas/testsuite/gas/riscv/zcmop.d | 16 +++ gas/testsuite/gas/riscv/zcmop.s | 10 ++ gas/testsuite/gas/riscv/zimop.d | 48 +++++++++ gas/testsuite/gas/riscv/zimop.s | 43 ++++++++ include/opcode/riscv-opc.h | 148 +++++++++++++++++++++++++++ include/opcode/riscv.h | 2 + opcodes/riscv-opc.c | 52 ++++++++++ 10 files changed, 336 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zcmop.d create mode 100644 gas/testsuite/gas/riscv/zcmop.s create mode 100644 gas/testsuite/gas/riscv/zimop.d create mode 100644 gas/testsuite/gas/riscv/zimop.s -- 2.17.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] RISC-V: Add support for Zcmop extension 2024-06-06 9:32 [PING] [PATCH 0/2] RISC-V: Add support for Zimop and " Xiao Zeng @ 2024-06-06 9:32 ` Xiao Zeng 0 siblings, 0 replies; 7+ messages in thread From: Xiao Zeng @ 2024-06-06 9:32 UTC (permalink / raw) To: binutils; +Cc: kito.cheng, palmer, nelson, zhengyu, Xiao Zeng This implements the Zcmop (Compressed Zimop) extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc> 1 The Zcmop extension requires the Zca extension. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zcmop. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zcmop.d: New test. * testsuite/gas/riscv/zcmop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_C_MOP_1): Define. (MASK_C_MOP_1): Ditto. (MATCH_C_MOP_3): Ditto. (MASK_C_MOP_3): Ditto. (MATCH_C_MOP_5): Ditto. (MASK_C_MOP_5): Ditto. (MATCH_C_MOP_7): Ditto. (MASK_C_MOP_7): Ditto. (MATCH_C_MOP_9): Ditto. (MASK_C_MOP_9): Ditto. (MATCH_C_MOP_11): Ditto. (MASK_C_MOP_11): Ditto. (MATCH_C_MOP_13): Ditto. (MASK_C_MOP_13): Ditto. (MATCH_C_MOP_15): Ditto. (MASK_C_MOP_15): Ditto. (DECLARE_INSN): New declarations for Zcmop. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZCMOP. opcodes/ChangeLog: * riscv-opc.c: Add Zcmop instructions. --- bfd/elfxx-riscv.c | 6 ++++++ gas/NEWS | 2 ++ gas/testsuite/gas/riscv/march-help.l | 1 + gas/testsuite/gas/riscv/zcmop.d | 16 ++++++++++++++++ gas/testsuite/gas/riscv/zcmop.s | 10 ++++++++++ include/opcode/riscv-opc.h | 26 ++++++++++++++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 10 ++++++++++ 8 files changed, 72 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zcmop.d create mode 100644 gas/testsuite/gas/riscv/zcmop.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 87b88513f5c..2dcd6c62a1b 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1271,6 +1271,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zcf", "zca", check_implicit_always}, {"zcd", "zca", check_implicit_always}, {"zcb", "zca", check_implicit_always}, + {"zcmop", "zca", check_implicit_always}, {"zcmp", "zca", check_implicit_always}, {"smaia", "ssaia", check_implicit_always}, {"smcntrpmf", "zicsr", check_implicit_always}, @@ -1432,6 +1433,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zcb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zcmop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2683,6 +2685,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, case INSN_CLASS_ZCB_AND_ZMMUL: return (riscv_subset_supports (rps, "zcb") && riscv_subset_supports (rps, "zmmul")); + case INSN_CLASS_ZCMOP: + return riscv_subset_supports (rps, "zcmop"); case INSN_CLASS_ZCMP: return riscv_subset_supports (rps, "zcmp"); case INSN_CLASS_SVINVAL: @@ -2955,6 +2959,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zcb' and `zbb"); case INSN_CLASS_ZCB_AND_ZMMUL: return _("zcb' and `zmmul', or `zcb' and `m"); + case INSN_CLASS_ZCMOP: + return "zcmop"; case INSN_CLASS_ZCMP: return "zcmp"; case INSN_CLASS_SVINVAL: diff --git a/gas/NEWS b/gas/NEWS index e6c1507349f..4d21dd5362b 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -21,6 +21,8 @@ * Add support for RISC-V Zimop extension with version 1.0. +* Add support for RISC-V Zcmop extension with version 1.0. + * Add support for RISC-V Zcmp extension with version 1.0. * Add support for RISC-V Zfbfmin extension with version 1.0. diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index dace28179b8..817b9aec5f3 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -94,6 +94,7 @@ All available -march extensions for RISC-V: zcb 1.0 zcf 1.0 zcd 1.0 + zcmop 1.0 zcmp 1.0 smaia 1.0 smcntrpmf 1.0 diff --git a/gas/testsuite/gas/riscv/zcmop.d b/gas/testsuite/gas/riscv/zcmop.d new file mode 100644 index 00000000000..5f608c676c3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmop.d @@ -0,0 +1,16 @@ +#as: -march=rv64i_zcmop +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+6081[ ]+c.mop.1 +[ ]+[0-9a-f]+:[ ]+6181[ ]+c.mop.3 +[ ]+[0-9a-f]+:[ ]+6281[ ]+c.mop.5 +[ ]+[0-9a-f]+:[ ]+6381[ ]+c.mop.7 +[ ]+[0-9a-f]+:[ ]+6481[ ]+c.mop.9 +[ ]+[0-9a-f]+:[ ]+6581[ ]+c.mop.11 +[ ]+[0-9a-f]+:[ ]+6681[ ]+c.mop.13 +[ ]+[0-9a-f]+:[ ]+6781[ ]+c.mop.15 diff --git a/gas/testsuite/gas/riscv/zcmop.s b/gas/testsuite/gas/riscv/zcmop.s new file mode 100644 index 00000000000..4b02e694f46 --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmop.s @@ -0,0 +1,10 @@ +target: + # c.mop.n + c.mop.1 + c.mop.3 + c.mop.5 + c.mop.7 + c.mop.9 + c.mop.11 + c.mop.13 + c.mop.15 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 8ba95399430..c7403d42734 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2271,6 +2271,23 @@ #define MASK_C_NOT 0xfc7f #define MATCH_C_MUL 0x9c41 #define MASK_C_MUL 0xfc63 +/* Zcmop instructions. */ +#define MATCH_C_MOP_1 0x6081 +#define MASK_C_MOP_1 0xffff +#define MATCH_C_MOP_3 0x6181 +#define MASK_C_MOP_3 0xffff +#define MATCH_C_MOP_5 0x6281 +#define MASK_C_MOP_5 0xffff +#define MATCH_C_MOP_7 0x6381 +#define MASK_C_MOP_7 0xffff +#define MATCH_C_MOP_9 0x6481 +#define MASK_C_MOP_9 0xffff +#define MATCH_C_MOP_11 0x6581 +#define MASK_C_MOP_11 0xffff +#define MATCH_C_MOP_13 0x6681 +#define MASK_C_MOP_13 0xffff +#define MATCH_C_MOP_15 0x6781 +#define MASK_C_MOP_15 0xffff /* Zcmp instructions. */ #define MATCH_CM_PUSH 0xb802 #define MASK_CM_PUSH 0xff03 @@ -4176,6 +4193,15 @@ DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU) DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH) DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB) DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH) +/* Zcmop instructions. */ +DECLARE_INSN(c_mop_1, MATCH_C_MOP_1, MASK_C_MOP_1) +DECLARE_INSN(c_mop_3, MATCH_C_MOP_3, MASK_C_MOP_3) +DECLARE_INSN(c_mop_5, MATCH_C_MOP_5, MASK_C_MOP_5) +DECLARE_INSN(c_mop_7, MATCH_C_MOP_7, MASK_C_MOP_7) +DECLARE_INSN(c_mop_9, MATCH_C_MOP_9, MASK_C_MOP_9) +DECLARE_INSN(c_mop_11, MATCH_C_MOP_11, MASK_C_MOP_11) +DECLARE_INSN(c_mop_13, MATCH_C_MOP_13, MASK_C_MOP_13) +DECLARE_INSN(c_mop_15, MATCH_C_MOP_15, MASK_C_MOP_15) /* Zcmp instructions. */ DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH) DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 2b2ed0dbce8..8f546772de0 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -487,6 +487,7 @@ enum riscv_insn_class INSN_CLASS_ZCB_AND_ZBA, INSN_CLASS_ZCB_AND_ZBB, INSN_CLASS_ZCB_AND_ZMMUL, + INSN_CLASS_ZCMOP, INSN_CLASS_ZCMP, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 45269e095a6..78144fca675 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2137,6 +2137,16 @@ const struct riscv_opcode riscv_opcodes[] = {"c.zext.b", 0, INSN_CLASS_ZCB, "Cs", MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, 0 }, {"c.sext.w", 64, INSN_CLASS_ZCB, "d", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, +/* Zcmop instructions. */ +{"c.mop.1", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_1, MASK_C_MOP_1, match_opcode, 0 }, +{"c.mop.3", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_3, MASK_C_MOP_3, match_opcode, 0 }, +{"c.mop.5", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_5, MASK_C_MOP_5, match_opcode, 0 }, +{"c.mop.7", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_7, MASK_C_MOP_7, match_opcode, 0 }, +{"c.mop.9", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_9, MASK_C_MOP_9, match_opcode, 0 }, +{"c.mop.11", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_11, MASK_C_MOP_11, match_opcode, 0 }, +{"c.mop.13", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_13, MASK_C_MOP_13, match_opcode, 0 }, +{"c.mop.15", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_15, MASK_C_MOP_15, match_opcode, 0 }, + /* Zcmp instructions. */ {"cm.push", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_PUSH, MASK_CM_PUSH, match_opcode, 0 }, {"cm.pop", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POP, MASK_CM_POP, match_opcode, 0 }, -- 2.17.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 0/2] RISC-V: Add support for Zimop and Zcmop extension @ 2024-05-30 1:51 Xiao Zeng 2024-05-30 1:51 ` [PATCH 2/2] RISC-V: Add support for " Xiao Zeng 0 siblings, 1 reply; 7+ messages in thread From: Xiao Zeng @ 2024-05-30 1:51 UTC (permalink / raw) To: binutils; +Cc: kito.cheng, palmer, nelson, zhengyu, Xiao Zeng RISC-V: Add support for Zimop extension RISC-V: Add support for Zcmop extension Xiao Zeng (2): RISC-V: Add support for Zimop extension RISC-V: Add support for Zcmop extension bfd/elfxx-riscv.c | 11 ++ gas/NEWS | 4 + gas/testsuite/gas/riscv/march-help.l | 2 + gas/testsuite/gas/riscv/zcmop.d | 16 +++ gas/testsuite/gas/riscv/zcmop.s | 10 ++ gas/testsuite/gas/riscv/zimop.d | 48 +++++++++ gas/testsuite/gas/riscv/zimop.s | 43 ++++++++ include/opcode/riscv-opc.h | 148 +++++++++++++++++++++++++++ include/opcode/riscv.h | 2 + opcodes/riscv-opc.c | 52 ++++++++++ 10 files changed, 336 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zcmop.d create mode 100644 gas/testsuite/gas/riscv/zcmop.s create mode 100644 gas/testsuite/gas/riscv/zimop.d create mode 100644 gas/testsuite/gas/riscv/zimop.s -- 2.17.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] RISC-V: Add support for Zcmop extension 2024-05-30 1:51 [PATCH 0/2] RISC-V: Add support for Zimop and " Xiao Zeng @ 2024-05-30 1:51 ` Xiao Zeng 0 siblings, 0 replies; 7+ messages in thread From: Xiao Zeng @ 2024-05-30 1:51 UTC (permalink / raw) To: binutils; +Cc: kito.cheng, palmer, nelson, zhengyu, Xiao Zeng This implements the Zcmop (Compressed Zimop) extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc> 1 The Zcmop extension requires the Zca extension. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zcmop. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zcmop.d: New test. * testsuite/gas/riscv/zcmop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_C_MOP_1): Define. (MASK_C_MOP_1): Ditto. (MATCH_C_MOP_3): Ditto. (MASK_C_MOP_3): Ditto. (MATCH_C_MOP_5): Ditto. (MASK_C_MOP_5): Ditto. (MATCH_C_MOP_7): Ditto. (MASK_C_MOP_7): Ditto. (MATCH_C_MOP_9): Ditto. (MASK_C_MOP_9): Ditto. (MATCH_C_MOP_11): Ditto. (MASK_C_MOP_11): Ditto. (MATCH_C_MOP_13): Ditto. (MASK_C_MOP_13): Ditto. (MATCH_C_MOP_15): Ditto. (MASK_C_MOP_15): Ditto. (DECLARE_INSN): New declarations for Zcmop. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZCMOP. opcodes/ChangeLog: * riscv-opc.c: Add Zcmop instructions. --- bfd/elfxx-riscv.c | 6 ++++++ gas/NEWS | 2 ++ gas/testsuite/gas/riscv/march-help.l | 1 + gas/testsuite/gas/riscv/zcmop.d | 16 ++++++++++++++++ gas/testsuite/gas/riscv/zcmop.s | 10 ++++++++++ include/opcode/riscv-opc.h | 26 ++++++++++++++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 10 ++++++++++ 8 files changed, 72 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zcmop.d create mode 100644 gas/testsuite/gas/riscv/zcmop.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 3db66da274d..dc29dce0084 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1268,6 +1268,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zcd", "zca", check_implicit_always}, {"zcb", "zca", check_implicit_always}, {"zcmp", "zca", check_implicit_always}, + {"zcmop", "zca", check_implicit_always}, {"smaia", "ssaia", check_implicit_always}, {"smcntrpmf", "zicsr", check_implicit_always}, {"smstateen", "ssstateen", check_implicit_always}, @@ -1426,6 +1427,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zcf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zcmop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2669,6 +2671,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, && riscv_subset_supports (rps, "zmmul")); case INSN_CLASS_ZCMP: return riscv_subset_supports (rps, "zcmp"); + case INSN_CLASS_ZCMOP: + return riscv_subset_supports (rps, "zcmop"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2929,6 +2933,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zcb' and `zmmul', or `zcb' and `m"); case INSN_CLASS_ZCMP: return "zcmp"; + case INSN_CLASS_ZCMOP: + return "zcmop"; case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/gas/NEWS b/gas/NEWS index 9478694a78b..6681c5c568a 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for RISC-V Zcmop extension with version 1.0. + * Add support for RISC-V Zimop extension with version 1.0. * Assembler macros as well as the bodies of .irp / .irpc can now use the diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index 53353246353..6a71586a559 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -92,6 +92,7 @@ All available -march extensions for RISC-V: zcf 1.0 zcd 1.0 zcmp 1.0 + zcmop 1.0 smaia 1.0 smcntrpmf 1.0 smepmp 1.0 diff --git a/gas/testsuite/gas/riscv/zcmop.d b/gas/testsuite/gas/riscv/zcmop.d new file mode 100644 index 00000000000..5f608c676c3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmop.d @@ -0,0 +1,16 @@ +#as: -march=rv64i_zcmop +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+6081[ ]+c.mop.1 +[ ]+[0-9a-f]+:[ ]+6181[ ]+c.mop.3 +[ ]+[0-9a-f]+:[ ]+6281[ ]+c.mop.5 +[ ]+[0-9a-f]+:[ ]+6381[ ]+c.mop.7 +[ ]+[0-9a-f]+:[ ]+6481[ ]+c.mop.9 +[ ]+[0-9a-f]+:[ ]+6581[ ]+c.mop.11 +[ ]+[0-9a-f]+:[ ]+6681[ ]+c.mop.13 +[ ]+[0-9a-f]+:[ ]+6781[ ]+c.mop.15 diff --git a/gas/testsuite/gas/riscv/zcmop.s b/gas/testsuite/gas/riscv/zcmop.s new file mode 100644 index 00000000000..4b02e694f46 --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmop.s @@ -0,0 +1,10 @@ +target: + # c.mop.n + c.mop.1 + c.mop.3 + c.mop.5 + c.mop.7 + c.mop.9 + c.mop.11 + c.mop.13 + c.mop.15 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index a6d7e4b24e2..741f866542e 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2280,6 +2280,23 @@ #define MASK_CM_POPRET 0xff03 #define MATCH_CM_POPRETZ 0xbc02 #define MASK_CM_POPRETZ 0xff03 +/* Zcmop instructions. */ +#define MATCH_C_MOP_1 0x6081 +#define MASK_C_MOP_1 0xffff +#define MATCH_C_MOP_3 0x6181 +#define MASK_C_MOP_3 0xffff +#define MATCH_C_MOP_5 0x6281 +#define MASK_C_MOP_5 0xffff +#define MATCH_C_MOP_7 0x6381 +#define MASK_C_MOP_7 0xffff +#define MATCH_C_MOP_9 0x6481 +#define MASK_C_MOP_9 0xffff +#define MATCH_C_MOP_11 0x6581 +#define MASK_C_MOP_11 0xffff +#define MATCH_C_MOP_13 0x6681 +#define MASK_C_MOP_13 0xffff +#define MATCH_C_MOP_15 0x6781 +#define MASK_C_MOP_15 0xffff /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -4100,6 +4117,15 @@ DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH) DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP) DECLARE_INSN(cm_popret, MATCH_CM_POPRET, MASK_CM_POPRET) DECLARE_INSN(cm_popretz, MATCH_CM_POPRETZ, MASK_CM_POPRETZ) +/* Zcmop instructions. */ +DECLARE_INSN(c_mop_1, MATCH_C_MOP_1, MASK_C_MOP_1) +DECLARE_INSN(c_mop_3, MATCH_C_MOP_3, MASK_C_MOP_3) +DECLARE_INSN(c_mop_5, MATCH_C_MOP_5, MASK_C_MOP_5) +DECLARE_INSN(c_mop_7, MATCH_C_MOP_7, MASK_C_MOP_7) +DECLARE_INSN(c_mop_9, MATCH_C_MOP_9, MASK_C_MOP_9) +DECLARE_INSN(c_mop_11, MATCH_C_MOP_11, MASK_C_MOP_11) +DECLARE_INSN(c_mop_13, MATCH_C_MOP_13, MASK_C_MOP_13) +DECLARE_INSN(c_mop_15, MATCH_C_MOP_15, MASK_C_MOP_15) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 83ce37be522..7003e4daf67 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -482,6 +482,7 @@ enum riscv_insn_class INSN_CLASS_ZCB_AND_ZBB, INSN_CLASS_ZCB_AND_ZMMUL, INSN_CLASS_ZCMP, + INSN_CLASS_ZCMOP, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index dee69470f6d..67d773143db 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2130,6 +2130,16 @@ const struct riscv_opcode riscv_opcodes[] = {"cm.popret", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POPRET, MASK_CM_POPRET, match_opcode, 0 }, {"cm.popretz", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POPRETZ, MASK_CM_POPRETZ, match_opcode, 0 }, +/* Zcmop instructions. */ +{"c.mop.1", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_1, MASK_C_MOP_1, match_opcode, 0 }, +{"c.mop.3", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_3, MASK_C_MOP_3, match_opcode, 0 }, +{"c.mop.5", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_5, MASK_C_MOP_5, match_opcode, 0 }, +{"c.mop.7", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_7, MASK_C_MOP_7, match_opcode, 0 }, +{"c.mop.9", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_9, MASK_C_MOP_9, match_opcode, 0 }, +{"c.mop.11", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_11, MASK_C_MOP_11, match_opcode, 0 }, +{"c.mop.13", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_13, MASK_C_MOP_13, match_opcode, 0 }, +{"c.mop.15", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_15, MASK_C_MOP_15, match_opcode, 0 }, + /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, {"csrwi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS }, -- 2.17.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2024-06-14 10:04 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2024-06-12 1:28 [PING^1] [PATCH 0/2] RISC-V: Add support for Zimop and Zcmop extension Xiao Zeng 2024-06-12 1:28 ` [PATCH 1/2] RISC-V: Add support for Zimop extension Xiao Zeng 2024-06-14 6:42 ` [PATCH v1] " Jin Ma 2024-06-14 10:04 ` Xiao Zeng 2024-06-12 1:28 ` [PATCH 2/2] RISC-V: Add support for Zcmop extension Xiao Zeng -- strict thread matches above, loose matches on Subject: below -- 2024-06-06 9:32 [PING] [PATCH 0/2] RISC-V: Add support for Zimop and " Xiao Zeng 2024-06-06 9:32 ` [PATCH 2/2] RISC-V: Add support for " Xiao Zeng 2024-05-30 1:51 [PATCH 0/2] RISC-V: Add support for Zimop and " Xiao Zeng 2024-05-30 1:51 ` [PATCH 2/2] RISC-V: Add support for " Xiao Zeng
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