* [PATCH v1 01/11] [Binutils] aarch64: Enable mandatory feature bits for v9.4-A.
2024-06-12 15:58 [PATCH v2 0/11][Binutils] aarch64: Fix the FEAT_SVE2p1 related issues srinath
@ 2024-06-12 15:58 ` srinath
2024-06-12 15:59 ` [PATCH v2 02/11] [Binutils] aarch64: Fix sve2p1 dupq instruction operands srinath
` (9 subsequent siblings)
10 siblings, 0 replies; 18+ messages in thread
From: srinath @ 2024-06-12 15:58 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 798 bytes --]
Hi,
This patch fixes the mandatory feature bits in v9.4-a architectures,
by enabling FEAT_SVE2p1 for Armv9.4-A architecture by default.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils master?
Regards,
Srinath.
---
gas/testsuite/gas/aarch64/sve2p1-1-bad.d | 2 +-
gas/testsuite/gas/aarch64/sve2p1-1.d | 2 +-
gas/testsuite/gas/aarch64/sve2p1-2-bad.d | 4 ++++
gas/testsuite/gas/aarch64/sve2p1-2-bad.l | 2 ++
gas/testsuite/gas/aarch64/sve2p1-nosve2.s | 1 +
include/opcode/aarch64.h | 3 ++-
6 files changed, 11 insertions(+), 3 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-bad.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-bad.l
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-nosve2.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0001-Binutils-aarch64-Enable-mandatory-feature-bits-fo.patch --]
[-- Type: text/x-patch; name="v1-0001-Binutils-aarch64-Enable-mandatory-feature-bits-fo.patch", Size: 2424 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-bad.d b/gas/testsuite/gas/aarch64/sve2p1-1-bad.d
index a2ca49ef487..c28cdc76c4c 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1-bad.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-1-bad.d
@@ -1,4 +1,4 @@
#name: Illegal test of SVE2.1 min max instructions.
-#as: -march=armv9.4-a
+#as: -march=armv9.3-a
#source: sve2p1-1.s
#error_output: sve2p1-1-bad.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d
index b93920cd02b..f562985b569 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.d
@@ -1,5 +1,5 @@
#name: Test of SVE2.1 instructions
-#as: -march=armv9.4-a+sve2p1
+#as: -march=armv9.4-a
#objdump: -dr
[^:]+: file format .*
diff --git a/gas/testsuite/gas/aarch64/sve2p1-2-bad.d b/gas/testsuite/gas/aarch64/sve2p1-2-bad.d
new file mode 100644
index 00000000000..4d58f4b0bd6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-2-bad.d
@@ -0,0 +1,4 @@
+#name: Illegal test of SVE2.1 instructions.
+#as: -march=armv9.4-a+nosve2
+#source: sve2p1-nosve2.s
+#error_output: sve2p1-2-bad.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-2-bad.l b/gas/testsuite/gas/aarch64/sve2p1-2-bad.l
new file mode 100644
index 00000000000..1e16026f47c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-2-bad.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: selected processor does not support `addqv v0.16b,p0,z16.b'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-nosve2.s b/gas/testsuite/gas/aarch64/sve2p1-nosve2.s
new file mode 100644
index 00000000000..7f457ea26e4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-nosve2.s
@@ -0,0 +1 @@
+addqv v0.16b, p0, z16.b
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 8a21611e3ff..7ae30bb456c 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -327,7 +327,8 @@ enum aarch64_feature_bit {
#define AARCH64_ARCH_V9_1A_FEATURES(X) AARCH64_ARCH_V8_6A_FEATURES (X)
#define AARCH64_ARCH_V9_2A_FEATURES(X) AARCH64_ARCH_V8_7A_FEATURES (X)
#define AARCH64_ARCH_V9_3A_FEATURES(X) AARCH64_ARCH_V8_8A_FEATURES (X)
-#define AARCH64_ARCH_V9_4A_FEATURES(X) AARCH64_ARCH_V8_9A_FEATURES (X)
+#define AARCH64_ARCH_V9_4A_FEATURES(X) (AARCH64_ARCH_V8_9A_FEATURES (X) \
+ | AARCH64_FEATBIT (X, SVE2p1))
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8A(X) (AARCH64_FEATBIT (X, V8) \
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH v2 02/11] [Binutils] aarch64: Fix sve2p1 dupq instruction operands.
2024-06-12 15:58 [PATCH v2 0/11][Binutils] aarch64: Fix the FEAT_SVE2p1 related issues srinath
2024-06-12 15:58 ` [PATCH v1 01/11] [Binutils] aarch64: Enable mandatory feature bits for v9.4-A srinath
@ 2024-06-12 15:59 ` srinath
2024-06-13 6:20 ` Jan Beulich
2024-06-12 15:59 ` [PATCH v1 03/11] [Binutils] aarch64: Fix sve2p1 dupq instruction operands (regenerated files) srinath
` (8 subsequent siblings)
10 siblings, 1 reply; 18+ messages in thread
From: srinath @ 2024-06-12 15:59 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 1806 bytes --]
Hi,
This patch fixes the syntax of sve2p1 "dupq" instruction by modifying the way
2nd operand does the encoding and decoding using the [<imm>] value.
dupq makes use of already existing aarch64_ins_sve_index and aarch64_ext_sve_index
inserter and extractor functions. The definitions of aarch64_ins_sve_index_imm (inserter)
and aarch64_ext_sve_index_imm (extractor) is removed in this patch.
This issues was reported here:
https://sourceware.org/pipermail/binutils/2024-February/132408.html
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils master?
Regards,
Srinath.
---
gas/testsuite/gas/aarch64/sve2p1-1-bad.l | 8 ----
gas/testsuite/gas/aarch64/sve2p1-1.d | 8 ----
gas/testsuite/gas/aarch64/sve2p1-1.s | 9 ----
gas/testsuite/gas/aarch64/sve2p1-2-invalid.d | 3 ++
gas/testsuite/gas/aarch64/sve2p1-2-invalid.l | 47 ++++++++++++++++++++
gas/testsuite/gas/aarch64/sve2p1-2-invalid.s | 10 +++++
gas/testsuite/gas/aarch64/sve2p1-2.d | 34 ++++++++++++++
gas/testsuite/gas/aarch64/sve2p1-2.s | 28 ++++++++++++
include/opcode/aarch64.h | 2 +-
opcodes/aarch64-asm.c | 19 +-------
opcodes/aarch64-asm.h | 1 -
opcodes/aarch64-dis.c | 36 ++-------------
opcodes/aarch64-dis.h | 1 -
opcodes/aarch64-tbl.h | 11 ++---
14 files changed, 134 insertions(+), 83 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-invalid.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-invalid.l
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-invalid.s
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0002-Binutils-aarch64-Fix-sve2p1-dupq-instruction-oper.patch --]
[-- Type: text/x-patch; name="v1-0002-Binutils-aarch64-Fix-sve2p1-dupq-instruction-oper.patch", Size: 15042 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
index 58f5b18ae82..4ea763f0e7d 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
+++ b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
@@ -35,14 +35,6 @@
.*: Error: selected processor does not support `uminqv v4.2d,p3,z2.d'
.*: Error: selected processor does not support `uminqv v8.2d,p4,z1.d'
.*: Error: selected processor does not support `uminqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `dupq z10.b,z20.b\[0\]'
-.*: Error: selected processor does not support `dupq z10.b,z20.b\[15\]'
-.*: Error: selected processor does not support `dupq z10.h,z20.h\[0\]'
-.*: Error: selected processor does not support `dupq z10.h,z20.h\[7\]'
-.*: Error: selected processor does not support `dupq z10.s,z20.s\[0\]'
-.*: Error: selected processor does not support `dupq z10.s,z20.s\[3\]'
-.*: Error: selected processor does not support `dupq z10.d,z20.d\[0\]'
-.*: Error: selected processor does not support `dupq z10.d,z20.d\[1\]'
.*: Error: selected processor does not support `eorqv v0.16b,p0,z16.b'
.*: Error: selected processor does not support `eorqv v1.8h,p1,z8.h'
.*: Error: selected processor does not support `eorqv v2.4s,p2,z4.s'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d
index f562985b569..6afb051e67d 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.d
@@ -44,14 +44,6 @@
.*: 04cf2c44 uminqv v4.2d, p3, z2.d
.*: 04cf3028 uminqv v8.2d, p4, z1.d
.*: 048f3c10 uminqv v16.4s, p7, z0.s
-.*: 0530268a dupq z10.b, z20.b\[0\]
-.*: 053f268a dupq z10.b, z20.b\[15\]
-.*: 0521268a dupq z10.h, z20.h\[0\]
-.*: 052f268a dupq z10.h, z20.h\[7\]
-.*: 0522268a dupq z10.s, z20.s\[0\]
-.*: 052e268a dupq z10.s, z20.s\[3\]
-.*: 0524268a dupq z10.d, z20.d\[0\]
-.*: 052c268a dupq z10.d, z20.d\[1\]
.*: 041d2200 eorqv v0.16b, p0, z16.b
.*: 045d2501 eorqv v1.8h, p1, z8.h
.*: 049d2882 eorqv v2.4s, p2, z4.s
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.s b/gas/testsuite/gas/aarch64/sve2p1-1.s
index 753f27f5ef2..08c777b2c70 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.s
@@ -39,15 +39,6 @@ uminqv v2.4s, p2, z4.s
uminqv v4.2d, p3, z2.d
uminqv v8.2d, p4, z1.d
uminqv v16.4s, p7, z0.s
-dupq z10.b, z20.b[0]
-dupq z10.b, z20.b[15]
-dupq z10.h, z20.h[0]
-dupq z10.h, z20.h[7]
-dupq z10.s, z20.s[0]
-dupq z10.s, z20.s[3]
-dupq z10.d, z20.d[0]
-dupq z10.d, z20.d[1]
-
eorqv v0.16b, p0, z16.b
eorqv v1.8h, p1, z8.h
eorqv v2.4s, p2, z4.s
diff --git a/gas/testsuite/gas/aarch64/sve2p1-2-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.d
new file mode 100644
index 00000000000..3953ca57ac8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.d
@@ -0,0 +1,3 @@
+#name: Test of illegal SVE2.1 dupq instructions.
+#as: -march=armv9.4-a
+#error_output: sve2p1-2-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-2-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.l
new file mode 100644
index 00000000000..26c24885d0b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.l
@@ -0,0 +1,47 @@
+.*: Assembler messages:
+.*: Error: register element index out of range 0 to 15 at operand 2 -- `dupq z0.b,z0.b\[16\]'
+.*: Error: operand mismatch -- `dupq z0.h,z0.b\[16\]'
+.*: Info: did you mean this\?
+.*: Info: dupq z0.b, z0.b\[16\]
+.*: Info: other valid variant\(s\):
+.*: Info: dupq z0.h, z0.h\[16\]
+.*: Info: dupq z0.s, z0.s\[16\]
+.*: Info: dupq z0.d, z0.d\[16\]
+.*: Error: operand mismatch -- `dupq z0.h,z0.s\[16\]'
+.*: Info: did you mean this\?
+.*: Info: dupq z0.h, z0.h\[16\]
+.*: Info: other valid variant\(s\):
+.*: Info: dupq z0.b, z0.b\[16\]
+.*: Info: dupq z0.s, z0.s\[16\]
+.*: Info: dupq z0.d, z0.d\[16\]
+.*: Error: operand mismatch -- `dupq z0.s,z0.d\[16\]'
+.*: Info: did you mean this\?
+.*: Info: dupq z0.s, z0.s\[16\]
+.*: Info: other valid variant\(s\):
+.*: Info: dupq z0.b, z0.b\[16\]
+.*: Info: dupq z0.h, z0.h\[16\]
+.*: Info: dupq z0.d, z0.d\[16\]
+.*: Error: register element index out of range 0 to 7 at operand 2 -- `dupq z0.h,z0.h\[8\]'
+.*: Error: register element index out of range 0 to 3 at operand 2 -- `dupq z0.s,z0.s\[4\]'
+.*: Error: register element index out of range 0 to 1 at operand 2 -- `dupq z0.d,z0.d\[2\]'
+.*: Error: operand mismatch -- `dupq z0.q,z0.d\[16\]'
+.*: Info: did you mean this\?
+.*: Info: dupq z0.d, z0.d\[16\]
+.*: Info: other valid variant\(s\):
+.*: Info: dupq z0.b, z0.b\[16\]
+.*: Info: dupq z0.h, z0.h\[16\]
+.*: Info: dupq z0.s, z0.s\[16\]
+.*: Error: operand mismatch -- `dupq z0.s,z0.q\[16\]'
+.*: Info: did you mean this\?
+.*: Info: dupq z0.s, z0.s\[16\]
+.*: Info: other valid variant\(s\):
+.*: Info: dupq z0.b, z0.b\[16\]
+.*: Info: dupq z0.h, z0.h\[16\]
+.*: Info: dupq z0.d, z0.d\[16\]
+.*: Error: operand mismatch -- `dupq z10.q,z20.q\[0\]'
+.*: Info: did you mean this\?
+.*: Info: dupq z10.b, z20.b\[0\]
+.*: Info: other valid variant\(s\):
+.*: Info: dupq z10.h, z20.h\[0\]
+.*: Info: dupq z10.s, z20.s\[0\]
+.*: Info: dupq z10.d, z20.d\[0\]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-2-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.s
new file mode 100644
index 00000000000..8f5fd528bc7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.s
@@ -0,0 +1,10 @@
+ dupq z0.b, z0.b[16]
+ dupq z0.h, z0.b[16]
+ dupq z0.h, z0.s[16]
+ dupq z0.s, z0.d[16]
+ dupq z0.h, z0.h[8]
+ dupq z0.s, z0.s[4]
+ dupq z0.d, z0.d[2]
+ dupq z0.q, z0.d[16]
+ dupq z0.s, z0.q[16]
+ dupq z10.q, z20.q[0]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-2.d b/gas/testsuite/gas/aarch64/sve2p1-2.d
new file mode 100644
index 00000000000..cd9900da2b0
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-2.d
@@ -0,0 +1,34 @@
+#name: Test of SVE2.1 dupq instructions.
+#as: -march=armv9.4-a
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: 05212400 dupq z0.b, z0.b\[0\]
+.*: 0521241f dupq z31.b, z0.b\[0\]
+.*: 052127e0 dupq z0.b, z31.b\[0\]
+.*: 053f2400 dupq z0.b, z0.b\[15\]
+.*: 053f27ff dupq z31.b, z31.b\[15\]
+.*: 052925e7 dupq z7.b, z15.b\[4\]
+.*: 05222400 dupq z0.h, z0.h\[0\]
+.*: 0522241f dupq z31.h, z0.h\[0\]
+.*: 052227e0 dupq z0.h, z31.h\[0\]
+.*: 053e2400 dupq z0.h, z0.h\[7\]
+.*: 053e27ff dupq z31.h, z31.h\[7\]
+.*: 053225e7 dupq z7.h, z15.h\[4\]
+.*: 05242400 dupq z0.s, z0.s\[0\]
+.*: 0524241f dupq z31.s, z0.s\[0\]
+.*: 052427e0 dupq z0.s, z31.s\[0\]
+.*: 053c2400 dupq z0.s, z0.s\[3\]
+.*: 053c27ff dupq z31.s, z31.s\[3\]
+.*: 053425e7 dupq z7.s, z15.s\[2\]
+.*: 05282400 dupq z0.d, z0.d\[0\]
+.*: 0528241f dupq z31.d, z0.d\[0\]
+.*: 052827e0 dupq z0.d, z31.d\[0\]
+.*: 05382400 dupq z0.d, z0.d\[1\]
+.*: 053827ff dupq z31.d, z31.d\[1\]
+.*: 052825e7 dupq z7.d, z15.d\[0\]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-2.s b/gas/testsuite/gas/aarch64/sve2p1-2.s
new file mode 100644
index 00000000000..4fc3cdc9e26
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-2.s
@@ -0,0 +1,28 @@
+ .text
+ dupq z0.b, z0.b[0]
+ dupq z31.b, z0.b[0]
+ dupq z0.b, z31.b[0]
+ dupq z0.b, z0.b[15]
+ dupq z31.b, z31.b[15]
+ dupq z7.b, z15.b[4]
+
+ dupq z0.h, z0.h[0]
+ dupq z31.h, z0.h[0]
+ dupq z0.h, z31.h[0]
+ dupq z0.h, z0.h[7]
+ dupq z31.h, z31.h[7]
+ dupq z7.h, z15.h[4]
+
+ dupq z0.s, z0.s[0]
+ dupq z31.s, z0.s[0]
+ dupq z0.s, z31.s[0]
+ dupq z0.s, z0.s[3]
+ dupq z31.s, z31.s[3]
+ dupq z7.s, z15.s[2]
+
+ dupq z0.d, z0.d[0]
+ dupq z31.d, z0.d[0]
+ dupq z0.d, z31.d[0]
+ dupq z0.d, z0.d[1]
+ dupq z31.d, z31.d[1]
+ dupq z7.d, z15.d[0]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 7ae30bb456c..db4e99cc868 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -749,8 +749,8 @@ enum aarch64_opnd
AARCH64_OPND_SVE_Zm_imm4, /* SVE vector register with 4bit index. */
AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
- AARCH64_OPND_SVE_Zn_5_INDEX, /* Indexed SVE vector register, for DUPQ. */
AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
+ AARCH64_OPND_SVE_Zn_5_INDEX, /* Indexed SVE vector register, for DUPQ. */
AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 5c6a31167c6..f5cb69270e8 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1281,23 +1281,8 @@ aarch64_ins_sve_index (const aarch64_operand *self,
{
unsigned int esize = aarch64_get_qualifier_esize (info->qualifier);
insert_field (self->fields[0], code, info->reglane.regno, 0);
- insert_fields (code, (info->reglane.index * 2 + 1) * esize, 0,
- 2, FLD_imm5, FLD_SVE_tszh);
- return true;
-}
-
-/* Encode Zn.<T>[<imm>], where <imm> is an immediate with range of 0 to one less
- than the number of elements in 128 bit, which can encode il:tsz. */
-bool
-aarch64_ins_sve_index_imm (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
- const aarch64_inst *inst ATTRIBUTE_UNUSED,
- aarch64_operand_error *errors ATTRIBUTE_UNUSED)
-{
- insert_field (self->fields[0], code, info->reglane.regno, 0);
- unsigned int esize = aarch64_get_qualifier_esize (info->qualifier);
- insert_fields (code, (info->reglane.index * 2 + 1) * esize, 0,
- 2, self->fields[1],self->fields[2]);
+ insert_all_fields_after (self, 1, code,
+ (info->reglane.index * 2 + 1) * esize);
return true;
}
diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h
index edeb6d8de7e..88143eecfcd 100644
--- a/opcodes/aarch64-asm.h
+++ b/opcodes/aarch64-asm.h
@@ -95,7 +95,6 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_one);
AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_two);
AARCH64_DECL_OPD_INSERTER (ins_sve_float_zero_one);
AARCH64_DECL_OPD_INSERTER (ins_sve_index);
-AARCH64_DECL_OPD_INSERTER (ins_sve_index_imm);
AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov);
AARCH64_DECL_OPD_INSERTER (ins_sve_quad_index);
AARCH64_DECL_OPD_INSERTER (ins_sve_reglist);
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 213df616608..d08cf057336 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2222,7 +2222,7 @@ aarch64_ext_sve_index (const aarch64_operand *self,
int val;
info->reglane.regno = extract_field (self->fields[0], code, 0);
- val = extract_fields (code, 0, 2, FLD_SVE_tszh, FLD_imm5);
+ val = extract_all_fields_after (self, 1, code);
if ((val & 31) == 0)
return 0;
while ((val & 1) == 0)
@@ -2231,26 +2231,6 @@ aarch64_ext_sve_index (const aarch64_operand *self,
return true;
}
-/* Decode Zn.<T>[<imm>], where <imm> is an immediate with range of 0 to one less
- than the number of elements in 128 bit, which can encode il:tsz. */
-bool
-aarch64_ext_sve_index_imm (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
- const aarch64_inst *inst ATTRIBUTE_UNUSED,
- aarch64_operand_error *errors ATTRIBUTE_UNUSED)
-{
- int val;
-
- info->reglane.regno = extract_field (self->fields[0], code, 0);
- val = extract_fields (code, 0, 2, self->fields[2], self->fields[1]);
- if ((val & 15) == 0)
- return 0;
- while ((val & 1) == 0)
- val /= 2;
- info->reglane.index = val / 2;
- return true;
-}
-
/* Decode a logical immediate for the MOV alias of SVE DUPM. */
bool
aarch64_ext_sve_limm_mov (const aarch64_operand *self,
@@ -3435,7 +3415,8 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
break;
case sve_index:
- i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
+ i = extract_field (FLD_imm5, inst->value, 0);
+
if ((i & 31) == 0)
return false;
while ((i & 1) == 0)
@@ -3445,17 +3426,6 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
}
break;
- case sve_index1:
- i = extract_fields (inst->value, 0, 2, FLD_SVE_tsz, FLD_SVE_i2h);
- if ((i & 15) == 0)
- return false;
- while ((i & 1) == 0)
- {
- i >>= 1;
- variant += 1;
- }
- break;
-
case sve_limm:
/* Pick the smallest applicable element size. */
if ((inst->value & 0x20600) == 0x600)
diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h
index 9e8f7c214d7..a71524f9c64 100644
--- a/opcodes/aarch64-dis.h
+++ b/opcodes/aarch64-dis.h
@@ -119,7 +119,6 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_one);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_two);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_zero_one);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index);
-AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index_imm);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_limm_mov);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_quad_index);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist);
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 1d12630273e..0ae54bc1ef7 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6518,7 +6518,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SVE2p1_INSNC("fminnmqv",0x6415a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
SVE2p1_INSNC("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index1, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
+ SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 1),
SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0),
SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
@@ -7109,11 +7109,12 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"an indexed SVE vector register") \
Y(SVE_REG, regno, "SVE_Zn", 0, F(FLD_SVE_Zn), \
"an SVE vector register") \
- Y(SVE_REG, sve_index_imm, "SVE_Zn_5_INDEX", 0, \
- F(FLD_SVE_Zn, FLD_SVE_i2h, FLD_SVE_tsz), \
- "a 5 bit idexed SVE vector register") \
- Y(SVE_REG, sve_index, "SVE_Zn_INDEX", 0, F(FLD_SVE_Zn), \
+ Y(SVE_REG, sve_index, "SVE_Zn_INDEX", 0, \
+ F(FLD_SVE_Zn, FLD_SVE_tszh, FLD_imm5), \
"an indexed SVE vector register") \
+ Y(SVE_REG, sve_index, "SVE_Zn_5_INDEX", 0, \
+ F(FLD_SVE_Zn, FLD_imm5), \
+ "a 5 bit indexed SVE vector register") \
Y(SVE_REGLIST, sve_reglist, "SVE_ZnxN", 0, F(FLD_SVE_Zn), \
"a list of SVE vector registers") \
Y(SVE_REG, regno, "SVE_Zt", 0, F(FLD_SVE_Zt), \
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v2 02/11] [Binutils] aarch64: Fix sve2p1 dupq instruction operands.
2024-06-12 15:59 ` [PATCH v2 02/11] [Binutils] aarch64: Fix sve2p1 dupq instruction operands srinath
@ 2024-06-13 6:20 ` Jan Beulich
0 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-06-13 6:20 UTC (permalink / raw)
To: srinath; +Cc: richard.earnshaw, nickc, binutils
On 12.06.2024 17:59, srinath wrote:
>
> Hi,
>
> This patch fixes the syntax of sve2p1 "dupq" instruction by modifying the way
> 2nd operand does the encoding and decoding using the [<imm>] value.
>
> dupq makes use of already existing aarch64_ins_sve_index and aarch64_ext_sve_index
> inserter and extractor functions. The definitions of aarch64_ins_sve_index_imm (inserter)
> and aarch64_ext_sve_index_imm (extractor) is removed in this patch.
>
> This issues was reported here:
> https://sourceware.org/pipermail/binutils/2024-February/132408.html
>
> Regression testing for aarch64-none-elf target and found no regressions.
>
> Ok for binutils master?
>
> Regards,
> Srinath.
> ---
> gas/testsuite/gas/aarch64/sve2p1-1-bad.l | 8 ----
> gas/testsuite/gas/aarch64/sve2p1-1.d | 8 ----
> gas/testsuite/gas/aarch64/sve2p1-1.s | 9 ----
While moving (and extending) these into a separate testcase may be fine, the
removal from sve2p1-1-bad.l is not accompanied by a similar addition
elsewhere. Is that intentional / desirable?
Jan
> gas/testsuite/gas/aarch64/sve2p1-2-invalid.d | 3 ++
> gas/testsuite/gas/aarch64/sve2p1-2-invalid.l | 47 ++++++++++++++++++++
> gas/testsuite/gas/aarch64/sve2p1-2-invalid.s | 10 +++++
> gas/testsuite/gas/aarch64/sve2p1-2.d | 34 ++++++++++++++
> gas/testsuite/gas/aarch64/sve2p1-2.s | 28 ++++++++++++
> include/opcode/aarch64.h | 2 +-
> opcodes/aarch64-asm.c | 19 +-------
> opcodes/aarch64-asm.h | 1 -
> opcodes/aarch64-dis.c | 36 ++-------------
> opcodes/aarch64-dis.h | 1 -
> opcodes/aarch64-tbl.h | 11 ++---
> 14 files changed, 134 insertions(+), 83 deletions(-)
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-invalid.d
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-invalid.l
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-invalid.s
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2.d
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2.s
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v1 03/11] [Binutils] aarch64: Fix sve2p1 dupq instruction operands (regenerated files).
2024-06-12 15:58 [PATCH v2 0/11][Binutils] aarch64: Fix the FEAT_SVE2p1 related issues srinath
2024-06-12 15:58 ` [PATCH v1 01/11] [Binutils] aarch64: Enable mandatory feature bits for v9.4-A srinath
2024-06-12 15:59 ` [PATCH v2 02/11] [Binutils] aarch64: Fix sve2p1 dupq instruction operands srinath
@ 2024-06-12 15:59 ` srinath
2024-06-12 15:59 ` [PATCH v1 04/11] [Binutils] aarch64: Fix sve2p1 extq instruction operands srinath
` (7 subsequent siblings)
10 siblings, 0 replies; 18+ messages in thread
From: srinath @ 2024-06-12 15:59 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, srinath
[-- Attachment #1: Type: text/plain, Size: 280 bytes --]
Hi,
This patch includes the regenerated files for
[Binutils] aarch64: Fix sve2p1 dupq instruction operands.
Regards,
Srinath.
---
opcodes/aarch64-asm-2.c | 1 -
opcodes/aarch64-dis-2.c | 1 -
opcodes/aarch64-opc-2.c | 4 ++--
3 files changed, 2 insertions(+), 4 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0003-Binutils-aarch64-Fix-sve2p1-dupq-instruction-oper.patch --]
[-- Type: text/x-patch; name="v1-0003-Binutils-aarch64-Fix-sve2p1-dupq-instruction-oper.patch", Size: 2761 bytes --]
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index a4b02cd9a25..78798049d34 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -948,7 +948,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 234:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
case 236:
- return aarch64_ins_sve_index_imm (self, info, code, inst, errors);
case 237:
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 238:
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 35501d6777e..7819c1091b1 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -33953,7 +33953,6 @@ aarch64_extract_operand (const aarch64_operand *self,
case 234:
return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
case 236:
- return aarch64_ext_sve_index_imm (self, info, code, inst, errors);
case 237:
return aarch64_ext_sve_index (self, info, code, inst, errors);
case 238:
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index bd1aa4f27c1..ad77a36730c 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -260,8 +260,8 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_imm4", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5, FLD_SVE_imm4}, "an 4bit indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_5_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_SVE_i2h, FLD_SVE_tsz}, "a 5 bit idexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_SVE_tszh, FLD_imm5}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_5_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm5}, "a 5 bit indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH v1 04/11] [Binutils] aarch64: Fix sve2p1 extq instruction operands.
2024-06-12 15:58 [PATCH v2 0/11][Binutils] aarch64: Fix the FEAT_SVE2p1 related issues srinath
` (2 preceding siblings ...)
2024-06-12 15:59 ` [PATCH v1 03/11] [Binutils] aarch64: Fix sve2p1 dupq instruction operands (regenerated files) srinath
@ 2024-06-12 15:59 ` srinath
2024-06-13 6:24 ` Jan Beulich
2024-06-12 15:59 ` [PATCH v1 05/11] [Binutils] aarch64: Fix sve2p1 extq instruction operands (regenerated files) srinath
` (6 subsequent siblings)
10 siblings, 1 reply; 18+ messages in thread
From: srinath @ 2024-06-12 15:59 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 1697 bytes --]
Hi,
This patch fixes the syntax of sve2p1 "extq" instruction by modifying the operands
count to 4. A new operand AARCH64_OPND_SVE_UIMM4 is defined to handle the 4th
argument an 4-bit unsigned immediate of extq instruction. The instruction encoding
is updated to use constraint C_SCAN_MOVPRFX, to enable "extq" instruction to immediately
precede in program order by a MOVPRFX instruction.
This issues was reported here:
https://sourceware.org/pipermail/binutils/2024-February/132408.html
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils master?
Regards,
Srinath.
---
gas/config/tc-aarch64.c | 1 +
gas/testsuite/gas/aarch64/sve2p1-1-bad.l | 6 ------
gas/testsuite/gas/aarch64/sve2p1-1.d | 6 ------
gas/testsuite/gas/aarch64/sve2p1-1.s | 6 ------
gas/testsuite/gas/aarch64/sve2p1-3-invalid.d | 3 +++
gas/testsuite/gas/aarch64/sve2p1-3-invalid.l | 17 +++++++++++++++++
gas/testsuite/gas/aarch64/sve2p1-3-invalid.s | 16 ++++++++++++++++
gas/testsuite/gas/aarch64/sve2p1-3.d | 20 ++++++++++++++++++++
gas/testsuite/gas/aarch64/sve2p1-3.s | 12 ++++++++++++
include/opcode/aarch64.h | 1 +
opcodes/aarch64-opc.c | 5 ++++-
opcodes/aarch64-tbl.h | 4 +++-
12 files changed, 77 insertions(+), 20 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-invalid.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-invalid.l
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-invalid.s
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0004-Binutils-aarch64-Fix-sve2p1-extq-instruction-oper.patch --]
[-- Type: text/x-patch; name="v1-0004-Binutils-aarch64-Fix-sve2p1-extq-instruction-oper.patch", Size: 10106 bytes --]
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 73b733ff727..b8bd5bceb07 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -7007,6 +7007,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_SIMM6:
case AARCH64_OPND_SVE_SIMM8:
case AARCH64_OPND_SVE_UIMM3:
+ case AARCH64_OPND_SVE_UIMM4:
case AARCH64_OPND_SVE_UIMM7:
case AARCH64_OPND_SVE_UIMM8:
case AARCH64_OPND_SVE_UIMM8_53:
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
index 4ea763f0e7d..718700e2ca2 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
+++ b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
@@ -41,12 +41,6 @@
.*: Error: selected processor does not support `eorqv v4.2d,p3,z2.d'
.*: Error: selected processor does not support `eorqv v8.2d,p4,z1.d'
.*: Error: selected processor does not support `eorqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `extq z0.b,z0.b,z10.b\[15\]'
-.*: Error: selected processor does not support `extq z1.b,z1.b,z15.b\[7\]'
-.*: Error: selected processor does not support `extq z2.b,z2.b,z5.b\[3\]'
-.*: Error: selected processor does not support `extq z4.b,z4.b,z12.b\[1\]'
-.*: Error: selected processor does not support `extq z8.b,z8.b,z7.b\[4\]'
-.*: Error: selected processor does not support `extq z16.b,z16.b,z1.b\[8\]'
.*: Error: selected processor does not support `faddqv v1.8h,p1,z8.h'
.*: Error: selected processor does not support `faddqv v2.4s,p2,z4.s'
.*: Error: selected processor does not support `faddqv v4.2d,p3,z2.d'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d
index 6afb051e67d..1c2e928685c 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.d
@@ -50,12 +50,6 @@
.*: 04dd2c44 eorqv v4.2d, p3, z2.d
.*: 04dd3028 eorqv v8.2d, p4, z1.d
.*: 049d3c10 eorqv v16.4s, p7, z0.s
-.*: 056a27c0 extq z0.b, z0.b, z10.b\[15\]
-.*: 056f25c1 extq z1.b, z1.b, z15.b\[7\]
-.*: 056524c2 extq z2.b, z2.b, z5.b\[3\]
-.*: 056c2444 extq z4.b, z4.b, z12.b\[1\]
-.*: 05672508 extq z8.b, z8.b, z7.b\[4\]
-.*: 05612610 extq z16.b, z16.b, z1.b\[8\]
.*: 6450a501 faddqv v1.8h, p1, z8.h
.*: 6490a882 faddqv v2.4s, p2, z4.s
.*: 64d0ac44 faddqv v4.2d, p3, z2.d
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.s b/gas/testsuite/gas/aarch64/sve2p1-1.s
index 08c777b2c70..5484557fb98 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.s
@@ -46,12 +46,6 @@ eorqv v4.2d, p3, z2.d
eorqv v8.2d, p4, z1.d
eorqv v16.4s, p7, z0.s
-extq z0.b, z0.b, z10.b[15]
-extq z1.b, z1.b, z15.b[7]
-extq z2.b, z2.b, z5.b[3]
-extq z4.b, z4.b, z12.b[1]
-extq z8.b, z8.b, z7.b[4]
-extq z16.b, z16.b, z1.b[8]
faddqv v1.8h, p1, z8.h
faddqv v2.4s, p2, z4.s
faddqv v4.2d, p3, z2.d
diff --git a/gas/testsuite/gas/aarch64/sve2p1-3-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.d
new file mode 100644
index 00000000000..ff6ecb2027a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.d
@@ -0,0 +1,3 @@
+#name: Test of illegal SVE2.1 extq instructions.
+#as: -march=armv9.4-a
+#error_output: sve2p1-3-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-3-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.l
new file mode 100644
index 00000000000..ca8f4cda456
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.l
@@ -0,0 +1,17 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `extq z0.b,z0.h,z0.b,#0'
+.*: Info: did you mean this\?
+.*: Info: extq z0.b, z0.b, z0.b, #0
+.*: Error: operand 2 must be the same register as operand 1 -- `extq z31.b,z15.b,z0.b,#0'
+.*: Error: operand mismatch -- `extq z0.b,z0.b,z31.h,#0'
+.*: Info: did you mean this\?
+.*: Info: extq z0.b, z0.b, z31.b, #0
+.*: Error: immediate value out of range 0 to 15 at operand 4 -- `extq z0.b,z0.b,z0.b,#16'
+.*: Error: operand mismatch -- `extq z0.h,z0.h,z0.h,#15'
+.*: Info: did you mean this\?
+.*: Info: extq z0.b, z0.b, z0.b, #15
+.*: Warning: output register of preceding `movprfx' not used in current instruction at operand 1 -- `extq z3.b,z3.b,z0.b,#0'
+.*: Error: operand 2 must be the same register as operand 1 -- `extq z31.b,z2.b,z0.b,#15'
+.*: Warning: instruction opens new dependency sequence without ending previous one -- `movprfx z31.b,p1/m,z10.b'
+.*: Warning: predicated instruction expected after `movprfx' -- `extq z31.b,z31.b,z0.b,#15'
+.*: Warning: output register of preceding `movprfx' used as input at operand 3 -- `extq z0.b,z0.b,z0.b,#0'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-3-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.s
new file mode 100644
index 00000000000..a6211ee24a0
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.s
@@ -0,0 +1,16 @@
+extq z0.b, z0.h, z0.b, #0
+extq z31.b, z15.b, z0.b, #0
+extq z0.b, z0.b, z31.h, #0
+extq z0.b, z0.b, z0.b, #16
+extq z0.h, z0.h, z0.h, #15
+movprfx z1, z5
+extq z3.b, z3.b, z0.b, #0
+
+movprfx z31, z10
+extq z31.b, z2.b, z0.b, #15
+
+movprfx z31.b, p1/m, z10.b
+extq z31.b, z31.b, z0.b, #15
+
+movprfx z0, z2
+extq z0.b, z0.b, z0.b, #0
diff --git a/gas/testsuite/gas/aarch64/sve2p1-3.d b/gas/testsuite/gas/aarch64/sve2p1-3.d
new file mode 100644
index 00000000000..bacb1b65bbe
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3.d
@@ -0,0 +1,20 @@
+#name: Test of SVE2.1 extq instructions.
+#as: -march=armv9.4-a
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: 05602400 extq z0.b, z0.b, z0.b, #0
+.*: 0560241f extq z31.b, z31.b, z0.b, #0
+.*: 056027e0 extq z0.b, z0.b, z31.b, #0
+.*: 056f2400 extq z0.b, z0.b, z0.b, #15
+.*: 056f27ff extq z31.b, z31.b, z31.b, #15
+.*: 056727ef extq z15.b, z15.b, z31.b, #7
+.*: 0420bca3 movprfx z3, z5
+.*: 05602403 extq z3.b, z3.b, z0.b, #0
+.*: 0420bd5f movprfx z31, z10
+.*: 056f241f extq z31.b, z31.b, z0.b, #15
diff --git a/gas/testsuite/gas/aarch64/sve2p1-3.s b/gas/testsuite/gas/aarch64/sve2p1-3.s
new file mode 100644
index 00000000000..38864b791fa
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3.s
@@ -0,0 +1,12 @@
+extq z0.b, z0.b, z0.b, #0
+extq z31.b, z31.b, z0.b, #0
+extq z0.b, z0.b, z31.b, #0
+extq z0.b, z0.b, z0.b, #15
+extq z31.b, z31.b, z31.b, #15
+extq z15.b, z15.b, z31.b, #7
+
+movprfx z3, z5
+extq z3.b, z3.b, z0.b, #0
+
+movprfx z31, z10
+extq z31.b, z31.b, z0.b, #15
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index db4e99cc868..2d4b011db1b 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -721,6 +721,7 @@ enum aarch64_opnd
AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
+ AARCH64_OPND_SVE_UIMM4, /* SVE unsigned 4-bit immediate. */
AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index bbe6f09808b..ad9b132fb23 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2720,6 +2720,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_SVE_UIMM3:
case AARCH64_OPND_SVE_UIMM7:
case AARCH64_OPND_SVE_UIMM8:
+ case AARCH64_OPND_SVE_UIMM4:
case AARCH64_OPND_SVE_UIMM8_53:
case AARCH64_OPND_CSSC_UIMM8:
size = get_operand_fields_width (get_operand_from_code (type));
@@ -4394,6 +4395,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SVE_UIMM3:
case AARCH64_OPND_SVE_UIMM7:
case AARCH64_OPND_SVE_UIMM8:
+ case AARCH64_OPND_SVE_UIMM4:
case AARCH64_OPND_SVE_UIMM8_53:
case AARCH64_OPND_IMM_ROT1:
case AARCH64_OPND_IMM_ROT2:
@@ -5516,7 +5518,8 @@ verify_constraints (const struct aarch64_inst *inst,
instruction for better error messages. */
if (!opcode->avariant
|| (!AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE)
- && !AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE2)))
+ && !AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE2)
+ && !AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE2p1)))
{
mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
mismatch_detail->error = _("SVE instruction expected after "
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 0ae54bc1ef7..b524cbe0ec8 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6519,7 +6519,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SVE2p1_INSNC("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
- SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 1),
+ SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0),
SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
@@ -7047,6 +7047,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"an 8-bit unsigned immediate") \
Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3_10), \
"an 8-bit unsigned immediate") \
+ Y(IMMEDIATE, imm, "SVE_UIMM4", 0, F(FLD_SVE_imm4), \
+ "a 4-bit unsigned immediate") \
Y(SIMD_REG, regno, "SVE_VZn", 0, F(FLD_SVE_Zn), "a SIMD register") \
Y(SIMD_REG, regno, "SVE_Vd", 0, F(FLD_SVE_Vd), "a SIMD register") \
Y(SIMD_REG, regno, "SVE_Vm", 0, F(FLD_SVE_Vm), "a SIMD register") \
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v1 04/11] [Binutils] aarch64: Fix sve2p1 extq instruction operands.
2024-06-12 15:59 ` [PATCH v1 04/11] [Binutils] aarch64: Fix sve2p1 extq instruction operands srinath
@ 2024-06-13 6:24 ` Jan Beulich
0 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-06-13 6:24 UTC (permalink / raw)
To: srinath; +Cc: richard.earnshaw, nickc, binutils
On 12.06.2024 17:59, srinath wrote:
>
> Hi,
>
> This patch fixes the syntax of sve2p1 "extq" instruction by modifying the operands
> count to 4. A new operand AARCH64_OPND_SVE_UIMM4 is defined to handle the 4th
> argument an 4-bit unsigned immediate of extq instruction. The instruction encoding
> is updated to use constraint C_SCAN_MOVPRFX, to enable "extq" instruction to immediately
> precede in program order by a MOVPRFX instruction.
>
> This issues was reported here:
> https://sourceware.org/pipermail/binutils/2024-February/132408.html
>
> Regression testing for aarch64-none-elf target and found no regressions.
>
> Ok for binutils master?
>
> Regards,
> Srinath.
> ---
> gas/config/tc-aarch64.c | 1 +
> gas/testsuite/gas/aarch64/sve2p1-1-bad.l | 6 ------
> gas/testsuite/gas/aarch64/sve2p1-1.d | 6 ------
> gas/testsuite/gas/aarch64/sve2p1-1.s | 6 ------
> gas/testsuite/gas/aarch64/sve2p1-3-invalid.d | 3 +++
> gas/testsuite/gas/aarch64/sve2p1-3-invalid.l | 17 +++++++++++++++++
> gas/testsuite/gas/aarch64/sve2p1-3-invalid.s | 16 ++++++++++++++++
> gas/testsuite/gas/aarch64/sve2p1-3.d | 20 ++++++++++++++++++++
> gas/testsuite/gas/aarch64/sve2p1-3.s | 12 ++++++++++++
> include/opcode/aarch64.h | 1 +
> opcodes/aarch64-opc.c | 5 ++++-
> opcodes/aarch64-tbl.h | 4 +++-
Since here you remove the sole user of SVE_Zm_imm4, shouldn't that operand
type then also be purged (much like you did in patch 2)?
Jan
> 12 files changed, 77 insertions(+), 20 deletions(-)
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-invalid.d
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-invalid.l
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-invalid.s
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3.d
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3.s
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v1 05/11] [Binutils] aarch64: Fix sve2p1 extq instruction operands (regenerated files).
2024-06-12 15:58 [PATCH v2 0/11][Binutils] aarch64: Fix the FEAT_SVE2p1 related issues srinath
` (3 preceding siblings ...)
2024-06-12 15:59 ` [PATCH v1 04/11] [Binutils] aarch64: Fix sve2p1 extq instruction operands srinath
@ 2024-06-12 15:59 ` srinath
2024-06-12 15:59 ` [PATCH v2 06/11] [Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands srinath
` (5 subsequent siblings)
10 siblings, 0 replies; 18+ messages in thread
From: srinath @ 2024-06-12 15:59 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, srinath
[-- Attachment #1: Type: text/plain, Size: 362 bytes --]
Hi,
This patch includes the regenerated files for
[Binutils] aarch64: Fix sve2p1 extq instruction operands.
Regards,
Srinath.
---
opcodes/aarch64-asm-2.c | 91 +++++++++++++++++++++--------------------
opcodes/aarch64-dis-2.c | 91 +++++++++++++++++++++--------------------
opcodes/aarch64-opc-2.c | 1 +
3 files changed, 93 insertions(+), 90 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0005-Binutils-aarch64-Fix-sve2p1-extq-instruction-oper.patch --]
[-- Type: text/x-patch; name="v1-0005-Binutils-aarch64-Fix-sve2p1-extq-instruction-oper.patch", Size: 12347 bytes --]
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 78798049d34..f7c36d6f262 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -666,30 +666,30 @@ aarch64_insert_operand (const aarch64_operand *self,
case 191:
case 192:
case 193:
- case 208:
case 209:
case 210:
case 211:
- case 220:
+ case 212:
case 221:
case 222:
case 223:
case 224:
- case 235:
- case 239:
- case 243:
- case 250:
+ case 225:
+ case 236:
+ case 240:
+ case 244:
case 251:
- case 258:
+ case 252:
case 259:
case 260:
case 261:
+ case 262:
return aarch64_ins_regno (self, info, code, inst, errors);
case 6:
case 118:
case 119:
- case 293:
- case 295:
+ case 294:
+ case 296:
return aarch64_ins_none (self, info, code, inst, errors);
case 17:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -703,17 +703,16 @@ aarch64_insert_operand (const aarch64_operand *self,
case 36:
case 37:
case 38:
- case 297:
+ case 298:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 39:
case 40:
case 41:
- case 225:
case 226:
- case 229:
- case 262:
+ case 227:
+ case 230:
case 263:
- case 278:
+ case 264:
case 279:
case 280:
case 281:
@@ -726,6 +725,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 288:
case 289:
case 290:
+ case 291:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 42:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -773,13 +773,14 @@ aarch64_insert_operand (const aarch64_operand *self,
case 205:
case 206:
case 207:
- case 264:
- case 291:
+ case 208:
+ case 265:
case 292:
- case 294:
- case 296:
- case 301:
+ case 293:
+ case 295:
+ case 297:
case 302:
+ case 303:
return aarch64_ins_imm (self, info, code, inst, errors);
case 51:
case 52:
@@ -927,80 +928,80 @@ aarch64_insert_operand (const aarch64_operand *self,
case 197:
case 198:
case 199:
- case 277:
+ case 278:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
- case 212:
case 213:
case 214:
case 215:
- return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
case 216:
+ return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
case 217:
case 218:
case 219:
+ case 220:
return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors);
- case 227:
case 228:
- case 230:
+ case 229:
case 231:
case 232:
case 233:
case 234:
+ case 235:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
- case 236:
case 237:
- return aarch64_ins_sve_index (self, info, code, inst, errors);
case 238:
- case 240:
- case 257:
- case 303:
+ return aarch64_ins_sve_index (self, info, code, inst, errors);
+ case 239:
+ case 241:
+ case 258:
case 304:
case 305:
+ case 306:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
- case 241:
case 242:
- case 244:
+ case 243:
case 245:
case 246:
case 247:
- case 256:
- return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 248:
+ case 257:
+ return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 249:
+ case 250:
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
- case 252:
- case 254:
- case 265:
- return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 253:
case 255:
- return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 266:
+ return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
+ case 254:
+ case 256:
+ return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 267:
case 268:
case 269:
case 270:
case 271:
case 272:
- return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 273:
- return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+ return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 274:
- return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+ return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 275:
- return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 276:
+ return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 277:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
- case 298:
case 299:
case 300:
+ case 301:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
- case 306:
case 307:
case 308:
case 309:
- return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 310:
+ return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 311:
return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 7819c1091b1..a85b5c434f0 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -33663,30 +33663,30 @@ aarch64_extract_operand (const aarch64_operand *self,
case 191:
case 192:
case 193:
- case 208:
case 209:
case 210:
case 211:
- case 220:
+ case 212:
case 221:
case 222:
case 223:
case 224:
- case 235:
- case 239:
- case 243:
- case 250:
+ case 225:
+ case 236:
+ case 240:
+ case 244:
case 251:
- case 258:
+ case 252:
case 259:
case 260:
case 261:
+ case 262:
return aarch64_ext_regno (self, info, code, inst, errors);
case 6:
case 118:
case 119:
- case 293:
- case 295:
+ case 294:
+ case 296:
return aarch64_ext_none (self, info, code, inst, errors);
case 11:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -33705,17 +33705,16 @@ aarch64_extract_operand (const aarch64_operand *self,
case 36:
case 37:
case 38:
- case 297:
+ case 298:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 39:
case 40:
case 41:
- case 225:
case 226:
- case 229:
- case 262:
+ case 227:
+ case 230:
case 263:
- case 278:
+ case 264:
case 279:
case 280:
case 281:
@@ -33728,6 +33727,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 288:
case 289:
case 290:
+ case 291:
return aarch64_ext_simple_index (self, info, code, inst, errors);
case 42:
return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -33776,13 +33776,14 @@ aarch64_extract_operand (const aarch64_operand *self,
case 205:
case 206:
case 207:
- case 264:
- case 291:
+ case 208:
+ case 265:
case 292:
- case 294:
- case 296:
- case 301:
+ case 293:
+ case 295:
+ case 297:
case 302:
+ case 303:
return aarch64_ext_imm (self, info, code, inst, errors);
case 51:
case 52:
@@ -33932,81 +33933,81 @@ aarch64_extract_operand (const aarch64_operand *self,
case 197:
case 198:
case 199:
- case 277:
+ case 278:
return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
- case 212:
case 213:
case 214:
case 215:
- return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors);
case 216:
+ return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors);
case 217:
case 218:
case 219:
+ case 220:
return aarch64_ext_sme_za_vrs2 (self, info, code, inst, errors);
- case 227:
case 228:
- case 230:
+ case 229:
case 231:
case 232:
case 233:
case 234:
+ case 235:
return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
- case 236:
case 237:
- return aarch64_ext_sve_index (self, info, code, inst, errors);
case 238:
- case 240:
- case 257:
- return aarch64_ext_sve_reglist (self, info, code, inst, errors);
+ return aarch64_ext_sve_index (self, info, code, inst, errors);
+ case 239:
case 241:
+ case 258:
+ return aarch64_ext_sve_reglist (self, info, code, inst, errors);
case 242:
- case 244:
+ case 243:
case 245:
case 246:
case 247:
- case 256:
- return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
case 248:
+ case 257:
+ return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
case 249:
+ case 250:
return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors);
- case 252:
- case 254:
- case 265:
- return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
case 253:
case 255:
- return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 266:
+ return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
+ case 254:
+ case 256:
+ return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 267:
case 268:
case 269:
case 270:
case 271:
case 272:
- return aarch64_ext_sme_za_array (self, info, code, inst, errors);
case 273:
- return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+ return aarch64_ext_sme_za_array (self, info, code, inst, errors);
case 274:
- return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
+ return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 275:
- return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
case 276:
+ return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 277:
return aarch64_ext_plain_shrimm (self, info, code, inst, errors);
- case 298:
case 299:
case 300:
+ case 301:
return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
- case 303:
case 304:
case 305:
- return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors);
case 306:
+ return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors);
case 307:
case 308:
case 309:
- return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 310:
+ return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 311:
return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index ad77a36730c..b0a5ccb4a83 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -232,6 +232,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm7}, "a 7-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3_10}, "an 8-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm4}, "a 4-bit unsigned immediate"},
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a SIMD register"},
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vd}, "a SIMD register"},
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vm}, "a SIMD register"},
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH v2 06/11] [Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.
2024-06-12 15:58 [PATCH v2 0/11][Binutils] aarch64: Fix the FEAT_SVE2p1 related issues srinath
` (4 preceding siblings ...)
2024-06-12 15:59 ` [PATCH v1 05/11] [Binutils] aarch64: Fix sve2p1 extq instruction operands (regenerated files) srinath
@ 2024-06-12 15:59 ` srinath
2024-06-13 15:10 ` Richard Earnshaw (lists)
2024-06-12 15:59 ` [PATCH v1 07/11] [Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands (regenerated files) srinath
` (4 subsequent siblings)
10 siblings, 1 reply; 18+ messages in thread
From: srinath @ 2024-06-12 15:59 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 3132 bytes --]
Hi,
This patch fixes encoding and syntax for sve2p1 instructions ld[1-4]q/st[1-4]q
as mentioned below, for the issues reported here.
https://sourceware.org/pipermail/binutils/2024-February/132408.html
1) Previously all the ld[1-4]q/st[1-4]q instructions are wrongly added as
predicated instructions and this issue is fixed in this patch by replacing
"SVE2p1_INSNC" with "SVE2p1_INSN" macro.
2) Wrong first operand in all the ld[1-4]q/st[1-4]q instructions is fixed
by replacing "SVE_Zt" with "SVE_ZtxN".
3) Wrong operand qualifiers in ld1q and st1q instructions are also fixed in
this patch.
Fixing above mentioned issues helps with following:
1) ld1q and st1q first register operand accepts enclosed figure braces.
2) ld2q, ld3q, ld4q, st2q, st3q, and st4q instructions accepts wrapping
sequence of vector registers.
For the instructions ld[2-4]q/st[2-4]q, tests for wrapping sequence of vector
registers are added along with short-form of operands for non-wrapping sequence.
I have added test using following logic:
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL] //raw insn encoding (all zeroes)
ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, #0, MUL VL] // encoding of <Zt1>
ld2q {Z0.Q, Z1.Q}, p7/Z, [x0, #0, MUL VL] // encoding of <Pg>
ld2q {Z0.Q, Z1.Q}, p0/Z, [x30, #0, MUL VL] // encoding of <Xm>
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #-16, MUL VL] // encoding of <imm> (low value)
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #14, MUL VL] // encoding of <imm> (high value)
ld2q {Z31.Q, Z0.Q}, p7/Z, [x30, #-16, MUL VL] // encoding of all fields (all ones)
ld2q {Z30.Q, Z31.Q}, p1/Z, [x3, #-2, MUL VL] // random encoding.
For all the above form of instructions the hyphenated form is preferred for
disassembly if there are more than one register in the list, and the register
numbers are monotonically increasing in increments of one.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
---
gas/config/tc-aarch64.c | 3 -
gas/testsuite/gas/aarch64/sme-5-illegal.l | 8 +-
gas/testsuite/gas/aarch64/sme-6-illegal.l | 8 +-
gas/testsuite/gas/aarch64/sve2p1-1-bad.l | 14 --
gas/testsuite/gas/aarch64/sve2p1-1.d | 14 --
gas/testsuite/gas/aarch64/sve2p1-1.s | 15 --
gas/testsuite/gas/aarch64/sve2p1-4-invalid.d | 3 +
gas/testsuite/gas/aarch64/sve2p1-4-invalid.l | 116 +++++++++++++++
gas/testsuite/gas/aarch64/sve2p1-4-invalid.s | 119 +++++++++++++++
gas/testsuite/gas/aarch64/sve2p1-4.d | 144 ++++++++++++++++++
gas/testsuite/gas/aarch64/sve2p1-4.s | 147 +++++++++++++++++++
include/opcode/aarch64.h | 3 -
opcodes/aarch64-opc.c | 11 +-
opcodes/aarch64-tbl.h | 43 +++---
14 files changed, 556 insertions(+), 92 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4-invalid.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4-invalid.l
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4-invalid.s
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0006-Binutils-aarch64-Fix-sve2p1-ld-1-4-st-1-4-q-instr.patch --]
[-- Type: text/x-patch; name="v1-0006-Binutils-aarch64-Fix-sve2p1-ld-1-4-st-1-4-q-instr.patch", Size: 47539 bytes --]
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index b8bd5bceb07..d72c1153b6e 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6862,9 +6862,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_ZtxN:
case AARCH64_OPND_SME_Zdnx2:
case AARCH64_OPND_SME_Zdnx4:
- case AARCH64_OPND_SME_Zt2:
- case AARCH64_OPND_SME_Zt3:
- case AARCH64_OPND_SME_Zt4:
case AARCH64_OPND_SME_Zmx2:
case AARCH64_OPND_SME_Zmx4:
case AARCH64_OPND_SME_Znx2:
diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.l b/gas/testsuite/gas/aarch64/sme-5-illegal.l
index c4bfc1f8b5a..b0736e0fcd6 100644
--- a/gas/testsuite/gas/aarch64/sme-5-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-5-illegal.l
@@ -35,10 +35,10 @@
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x0,x17,lsl#3\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp,x17,lsl#3\]'
-[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]'
-[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]'
-[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]'
-[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]'
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x17\]'
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp\]'
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x0,x17,lsl#4\]'
diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.l b/gas/testsuite/gas/aarch64/sme-6-illegal.l
index b98b76faaed..10c2a51204b 100644
--- a/gas/testsuite/gas/aarch64/sme-6-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-6-illegal.l
@@ -35,10 +35,10 @@
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x0,x17,lsl#3\]'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp,x17,lsl#3\]'
-[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0\]'
-[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp\]'
-[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]'
-[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]'
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x17\]'
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp\]'
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x0,x17,lsl#4\]'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
index 718700e2ca2..1b6a9683b65 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
+++ b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
@@ -66,17 +66,3 @@
.*: Error: selected processor does not support `fminqv v4.2d,p3,z2.d'
.*: Error: selected processor does not support `fminqv v8.2d,p4,z1.d'
.*: Error: selected processor does not support `fminqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `ld1q Z0.Q,p4/Z,\[Z16.D,x0\]'
-.*: Error: selected processor does not support `ld2q {Z0.Q,Z1.Q},p4/Z,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `ld3q .*
-.*: Error: selected processor does not support `ld4q .*
-.*: Error: selected processor does not support `ld2q {Z0.Q,Z1.Q},p4/Z,\[x0,x2,lsl#4\]'
-.*: Error: selected processor does not support `ld3q {Z0.Q,Z1.Q,Z2.Q},p4/Z,\[x0,x4,lsl#4\]'
-.*: Error: selected processor does not support `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4/Z,\[x0,x6,lsl#4\]'
-.*: Error: selected processor does not support `st1q Z0.Q,p4,\[Z16.D,x0\]'
-.*: Error: selected processor does not support `st2q {Z0.Q,Z1.Q},p4,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `st3q .*
-.*: Error: selected processor does not support `st4q .*
-.*: Error: selected processor does not support `st2q {Z0.Q,Z1.Q},p4,\[x0,x2,lsl#4\]'
-.*: Error: selected processor does not support `st3q {Z0.Q,Z1.Q,Z2.Q},p4,\[x0,x4,lsl#4\]'
-.*: Error: selected processor does not support `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4,\[x0,x6,lsl#4\]'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d
index 1c2e928685c..8277a1386f2 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.d
@@ -75,17 +75,3 @@
.*: 64d7ac44 fminqv v4.2d, p3, z2.d
.*: 64d7b028 fminqv v8.2d, p4, z1.d
.*: 6497bc10 fminqv v16.4s, p7, z0.s
-.*: c400b200 ld1q z0.q, p4/z, \[z16.d, x0\]
-.*: a49ef000 ld2q {z0.q, z1.q}, p4/z, \[x0, #-4, mul vl\]
-.*: a51ef000 ld3q {z0.q, z1.q, z2.q}, p4/z, \[x0, #-6, mul vl\]
-.*: a59ef000 ld4q {z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, #-8, mul vl\]
-.*: a4a29000 ld2q {z0.q, z1.q}, p4/z, \[x0, x2, lsl #4\]
-.*: a5249000 ld3q {z0.q, z1.q, z2.q}, p4/z, \[x0, x4, lsl #4\]
-.*: a5a69000 ld4q {z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, x6, lsl #4\]
-.*: e4203200 st1q z0.q, p4, \[z16.d, x0\]
-.*: e44e1000 st2q {z0.q, z1.q}, p4, \[x0, #-4, mul vl\]
-.*: e48e1000 st3q {z0.q, z1.q, z2.q}, p4, \[x0, #-6, mul vl\]
-.*: e4ce1000 st4q {z0.q, z1.q, z2.q, z3.q}, p4, \[x0, #-8, mul vl\]
-.*: e4621000 st2q {z0.q, z1.q}, p4, \[x0, x2, lsl #4\]
-.*: e4a41000 st3q {z0.q, z1.q, z2.q}, p4, \[x0, x4, lsl #4\]
-.*: e4e61000 st4q {z0.q, z1.q, z2.q, z3.q}, p4, \[x0, x6, lsl #4\]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.s b/gas/testsuite/gas/aarch64/sve2p1-1.s
index 5484557fb98..1e7c2ceceba 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.s
@@ -75,18 +75,3 @@ fminqv v2.4s, p2, z4.s
fminqv v4.2d, p3, z2.d
fminqv v8.2d, p4, z1.d
fminqv v16.4s, p7, z0.s
-ld1q Z0.Q, p4/Z, [Z16.D, x0]
-ld2q {Z0.Q, Z1.Q}, p4/Z, [x0, #-4, MUL VL]
-ld3q {Z0.Q, Z1.Q, Z2.Q}, p4/Z, [x0, #-6, MUL VL]
-ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4/Z, [x0, #-8, MUL VL]
-ld2q {Z0.Q, Z1.Q}, p4/Z, [x0, x2, lsl #4]
-ld3q {Z0.Q, Z1.Q, Z2.Q}, p4/Z, [x0, x4, lsl #4]
-ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4/Z, [x0, x6, lsl #4]
-
-st1q Z0.Q, p4, [Z16.D, x0]
-st2q {Z0.Q, Z1.Q}, p4, [x0, #-4, MUL VL]
-st3q {Z0.Q, Z1.Q, Z2.Q}, p4, [x0, #-6, MUL VL]
-st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4, [x0, #-8, MUL VL]
-st2q {Z0.Q, Z1.Q}, p4, [x0, x2, lsl #4]
-st3q {Z0.Q, Z1.Q, Z2.Q}, p4, [x0, x4, lsl #4]
-st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4, [x0, x6, lsl #4]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-4-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.d
new file mode 100644
index 00000000000..2363a12484d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.d
@@ -0,0 +1,3 @@
+#name: Test of illegal SVE2.1 ld[1-4]q/st[1-4]q instructions.
+#as: -march=armv9.4-a
+#error_output: sve2p1-4-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-4-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.l
new file mode 100644
index 00000000000..1c713a1325f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.l
@@ -0,0 +1,116 @@
+.*: Assembler messages:
+.*: Error: p0-p7 expected at operand 2 -- `ld1q {Z0.Q},P8/Z,\[Z0.D,x0\]'
+.*: Error: invalid base register at operand 3 -- `ld1q {Z0.Q},P0/Z,\[Z31.Q,x0\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld1q {Z0.Q},P0/Z,\[Z0.D,x31\]'
+.*: Error: operand mismatch -- `ld1q {Z31.D},P7/Z,\[Z31.D,x30\]'
+.*: Info: did you mean this\?
+.*: Info: ld1q {z31.q}, p7/z, \[z31.d, x30\]
+.*: Error: invalid offset register at operand 3 -- `ld1q Z0.Q,P0/Z,\[Z0.D,sp\]'
+.*: Error: operand mismatch -- `ld1q Z0.Q,P0/Z,\[Z0.S,x15\]'
+.*: Info: did you mean this\?
+.*: Info: ld1q {z0.q}, p0/z, \[z0.d, x15\]
+.*: Error: invalid use of 32-bit register offset at operand 3 -- `ld1q Z0.Q,P0/Z,\[Z0.D,w10\]'
+.*: Error: the register list must have a stride of 1 at operand 1 -- `ld2q {Z0.Q,Z2.Q},p0/Z,\[x0,#-2,MUL VL\]'
+.*: Error: invalid register list at operand 1 -- `ld2q {Z31.Q,Z31.Q},p0/Z,\[x0,#-2,MUL VL\]'
+.*: Error: p0-p7 expected at operand 2 -- `ld2q {Z0.Q,Z1.Q},p8/Z,\[x0,#-2,MUL VL\]'
+.*: Error: invalid base register at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[x31,#-2,MUL VL\]'
+.*: Error: immediate value must be a multiple of 2 at operand 3 -- `ld2q {Z30.Q,Z31.Q},p7/Z,\[x30,#-3,MUL VL\]'
+.*: Error: invalid base register at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[x31,#-20,MUL VL\]'
+.*: Error: invalid base register at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[xzr,#-20,MUL VL\]'
+.*: Error: invalid register list at operand 1 -- `ld3q {Z0.Q,Z1.Q,Z3.Q},p0/Z,\[x0,#-3,MUL VL\]'
+.*: Error: operand mismatch -- `ld3q {Z29.Q,Z30.Q,Z31.Q},p8/M,\[x0,#-3,MUL VL\]'
+.*: Info: did you mean this\?
+.*: Info: ld3q {z29.q-z31.q}, p8/z, \[x0, #-3, mul vl\]
+.*: Error: immediate value must be a multiple of 3 at operand 3 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p7/Z,\[x0,#-2,MUL VL\]'
+.*: Error: invalid base register at operand 3 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p0/Z,\[x31,#-3,MUL VL\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `ld3q {Z29.Q,Z30.Q,Z31.D},p7/Z,\[x30,#-3,MUL VL\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `ld3q {Z29.Q,Z30.Q,Z31.D},p7/Z,\[x30,#-30,MUL VL\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `ld3q {Z29.Q,Z30.Q,Z31.D},p7/Z,\[xzr,#-30,MUL VL\]'
+.*: Error: expected a list of 4 registers at operand 1 -- `ld4q {Z0.Q,Z1.Q,Z2.Q},p0/Z,\[x0,#-4,MUL VL\]'
+.*: Error: p0-p7 expected at operand 2 -- `ld4q {Z28.Q,Z29.Q,Z30.Q,Z31.Q},p9/Z,\[x0,#-4,MUL VL\]'
+.*: Error: immediate value must be a multiple of 4 at operand 3 -- `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p7/Z,\[x0,#-3,MUL VL\]'
+.*: Error: invalid base register at operand 3 -- `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p0/Z,\[x31,#-4,MUL VL\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `ld4q {Z28.Q,Z29.Q,Z30.D,Z31.Q},p7/Z,\[x30,#-4,MUL VL\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `ld4q {Z28.Q,Z29.Q,Z30.D,Z31.Q},p7/Z,\[x30,#-100,MUL VL\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `ld4q {Z28.Q,Z29.Q,Z30.D,Z31.Q},p7/Z,\[xzr,#-100,MUL VL\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[x0,x0,LSL#3\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[sp,x0,LSL#3\]'
+.*: Error: invalid offset register at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[x0,sp,LSL#3\]'
+.*: Error: invalid register list at operand 1 -- `ld2q {Z31.Q,Z31.Q},p0/Z,\[x0,x0,LSL#4\]'
+.*: Error: p0-p7 expected at operand 2 -- `ld2q {Z0.Q,Z1.Q},p8/Z,\[x0,x0,LSL#4\]'
+.*: Error: invalid base register at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[x31,x0,LSL#4\]'
+.*: Error: only 'MUL VL' is permitted at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[x0,x31,LSL#4\]'
+.*: Error: invalid base register at operand 3 -- `ld2q {Z30.Q,Z31.Q},p7/Z,\[x31,x31,LSL#4\]'
+.*: Error: shift expression expected at operand 3 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p0/Z,\[x0,x0,#4\]'
+.*: Error: shift expression expected at operand 3 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p0/Z,\[sp,x0,#4\]'
+.*: Error: invalid offset register at operand 3 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p0/Z,\[x0,sp,#4\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld3q {Z29.Q,Z30.Q,Z31.Q},p0/Z,\[x0,x0,LSL#2\]'
+.*: Error: operand mismatch -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p7/M,\[x0,x0,LSL#4\]'
+.*: Info: did you mean this\?
+.*: Info: ld3q {z0.q-z2.q}, p7/z, \[x0, x0, lsl #4\]
+.*: Error: p0-p7 expected at operand 2 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p8/Z,\[x30,x0,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `ld3q {Z4.Q,Z1.Q,Z2.Q},p0/Z,\[x31,x30,LSL#4\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `ld3q {Z29.D,Z30.Q,Z31.Q},p7/Z,\[x31,x30,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `ld4q {Z1.Q,Z1.Q,Z2.Q,Z3.Q},p0/Z,\[x0,x0,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `ld4q {Z1.Q,Z1.Q,Z2.Q,Z3.Q},p0/Z,\[sp,x0,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `ld4q {Z1.Q,Z1.Q,Z2.Q,Z3.Q},p0/Z,\[x0,sp,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `ld4q {Z30.Q,Z29.Q,Z30.Q,Z31.Q},p8/Z,\[x0,x0,LSL#4\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p7/Z,\[x0,x0,LSL#2\]'
+.*: Error: invalid base register at operand 3 -- `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p0/Z,\[x31,x0,LSL#4\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `ld4q {Z0.Q,Z1.Q,Z2.D,Z3.Q},p0/Z,\[x1,x30,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `ld4q {Z2.Q,Z29.Q,Z30.Q,Z31.Q},p7/Z,\[x30,x30,LSL#4\]'
+.*: Error: p0-p7 expected at operand 2 -- `st1q {Z0.Q},P8,\[Z0.D,x0\]'
+.*: Error: invalid base register at operand 3 -- `st1q {Z0.Q},P0,\[Z31.Q,x0\]'
+.*: Error: invalid addressing mode at operand 3 -- `st1q {Z0.Q},P0,\[Z0.D,x31\]'
+.*: Error: operand mismatch -- `st1q {Z31.D},P7,\[Z31.D,x30\]'
+.*: Info: did you mean this\?
+.*: Info: st1q {z31.q}, p7, \[z31.d, x30\]
+.*: Error: invalid offset register at operand 3 -- `st1q Z0.Q,P0,\[Z0.D,sp\]'
+.*: Error: operand mismatch -- `st1q Z0.Q,P0,\[Z0.S,x15\]'
+.*: Info: did you mean this\?
+.*: Info: st1q {z0.q}, p0, \[z0.d, x15\]
+.*: Error: invalid use of 32-bit register offset at operand 3 -- `st1q Z0.Q,P0,\[Z0.D,w10\]'
+.*: Error: the register list must have a stride of 1 at operand 1 -- `st2q {Z0.Q,Z2.Q},p0,\[x0,#-2,MUL VL\]'
+.*: Error: invalid register list at operand 1 -- `st2q {Z31.Q,Z31.Q},p0,\[x0,#-2,MUL VL\]'
+.*: Error: p0-p7 expected at operand 2 -- `st2q {Z0.Q,Z1.Q},p8,\[x0,#-2,MUL VL\]'
+.*: Error: invalid base register at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x31,#-2,MUL VL\]'
+.*: Error: immediate value must be a multiple of 2 at operand 3 -- `st2q {Z30.Q,Z31.Q},p7,\[x30,#-3,MUL VL\]'
+.*: Error: invalid base register at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x31,#-20,MUL VL\]'
+.*: Error: invalid base register at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[xzr,#-20,MUL VL\]'
+.*: Error: invalid register list at operand 1 -- `st3q {Z0.Q,Z1.Q,Z3.Q},p0,\[x0,#-3,MUL VL\]'
+.*: Error: p0-p7 expected at operand 2 -- `st3q {Z29.Q,Z30.Q,Z31.Q},p8,\[x0,#-3,MUL VL\]'
+.*: Error: immediate value must be a multiple of 3 at operand 3 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p7,\[x0,#-2,MUL VL\]'
+.*: Error: invalid base register at operand 3 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p0,\[x31,#-3,MUL VL\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `st3q {Z29.Q,Z30.Q,Z31.D},p7,\[x30,#-3,MUL VL\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `st3q {Z29.Q,Z30.Q,Z31.D},p7,\[x30,#-30,MUL VL\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `st3q {Z29.Q,Z30.Q,Z31.D},p7,\[xzr,#-30,MUL VL\]'
+.*: Error: expected a list of 4 registers at operand 1 -- `st4q {Z0.Q,Z1.Q,Z2.Q},p0,\[x0,#-4,MUL VL\]'
+.*: Error: p0-p7 expected at operand 2 -- `st4q {Z28.Q,Z29.Q,Z30.Q,Z31.Q},p9,\[x0,#-4,MUL VL\]'
+.*: Error: immediate value must be a multiple of 4 at operand 3 -- `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p7,\[x0,#-3,MUL VL\]'
+.*: Error: invalid base register at operand 3 -- `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p0,\[x31,#-4,MUL VL\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `st4q {Z28.Q,Z29.Q,Z30.D,Z31.Q},p7,\[x30,#-4,MUL VL\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `st4q {Z28.Q,Z29.Q,Z30.D,Z31.Q},p7,\[x30,#-100,MUL VL\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `st4q {Z28.Q,Z29.Q,Z30.D,Z31.Q},p7,\[xzr,#-100,MUL VL\]'
+.*: Error: invalid addressing mode at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x0,x0,LSL#3\]'
+.*: Error: invalid addressing mode at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[sp,x0,LSL#3\]'
+.*: Error: invalid offset register at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x0,sp,LSL#3\]'
+.*: Error: invalid register list at operand 1 -- `st2q {Z31.Q,Z31.Q},p0,\[x0,x0,LSL#4\]'
+.*: Error: p0-p7 expected at operand 2 -- `st2q {Z0.Q,Z1.Q},p8,\[x0,x0,LSL#4\]'
+.*: Error: invalid base register at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x31,x0,LSL#4\]'
+.*: Error: only 'MUL VL' is permitted at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x0,x31,LSL#4\]'
+.*: Error: invalid base register at operand 3 -- `st2q {Z30.Q,Z31.Q},p7,\[x31,x31,LSL#4\]'
+.*: Error: shift expression expected at operand 3 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p0,\[x0,x0,#4\]'
+.*: Error: shift expression expected at operand 3 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p0,\[sp,x0,#4\]'
+.*: Error: invalid offset register at operand 3 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p0,\[x0,sp,#4\]'
+.*: Error: invalid addressing mode at operand 3 -- `st3q {Z29.Q,Z30.Q,Z31.Q},p0,\[x0,x0,LSL#2\]'
+.*: Error: p0-p7 expected at operand 2 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p8,\[x30,x0,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `st3q {Z4.Q,Z1.Q,Z2.Q},p0,\[x31,x30,LSL#4\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `st3q {Z29.D,Z30.Q,Z31.Q},p7,\[x31,x30,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `st4q {Z1.Q,Z1.Q,Z2.Q,Z3.Q},p0,\[x0,x0,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `st4q {Z1.Q,Z1.Q,Z2.Q,Z3.Q},p0,\[sp,x0,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `st4q {Z1.Q,Z1.Q,Z2.Q,Z3.Q},p0,\[x0,sp,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `st4q {Z30.Q,Z29.Q,Z30.Q,Z31.Q},p8,\[x0,x0,LSL#4\]'
+.*: Error: invalid addressing mode at operand 3 -- `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p7,\[x0,x0,LSL#2\]'
+.*: Error: invalid base register at operand 3 -- `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p0,\[x31,x0,LSL#4\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `st4q {Z0.Q,Z1.Q,Z2.D,Z3.Q},p0,\[x1,x30,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `st4q {Z2.Q,Z29.Q,Z30.Q,Z31.Q},p7,\[x30,x30,LSL#4\]'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-4-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.s
new file mode 100644
index 00000000000..a95c18e88ec
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.s
@@ -0,0 +1,119 @@
+ld1q Z0.Q , P0/Z, [Z0.D, x0]
+ld1q { Z0.Q }, P8/Z, [Z0.D, x0]
+ld1q { Z0.Q }, P0/Z, [Z31.Q, x0]
+ld1q { Z0.Q }, P0/Z, [Z0.D, x31]
+ld1q { Z31.D }, P7/Z, [Z31.D, x30]
+ld1q Z0.Q , P0/Z, [Z0.D, sp]
+ld1q Z0.Q , P0/Z, [Z0.S, x15]
+ld1q Z0.Q , P0/Z, [Z0.D, w10]
+
+ld2q {Z0.Q, Z2.Q}, p0/Z, [x0, #-2, MUL VL]
+ld2q {Z31.Q, Z31.Q}, p0/Z, [x0, #-2, MUL VL]
+ld2q {Z0.Q, Z1.Q}, p8/Z, [x0, #-2, MUL VL]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x31, #-2, MUL VL]
+ld2q {Z30.Q, Z31.Q}, p7/Z, [x30, #-3, MUL VL]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x31, #-20, MUL VL]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [xzr, #-20, MUL VL]
+
+ld3q {Z0.Q, Z1.Q, Z3.Q}, p0/Z, [x0, #-3, MUL VL]
+ld3q {Z29.Q, Z30.Q, Z31.Q}, p8/M, [x0, #-3, MUL VL]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x0, #-2, MUL VL]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x31, #-3, MUL VL]
+ld3q {Z29.Q, Z30.Q, Z31.D}, p7/Z, [x30, #-3, MUL VL]
+ld3q {Z29.Q, Z30.Q, Z31.D}, p7/Z, [x30, #-30, MUL VL]
+ld3q {Z29.Q, Z30.Q, Z31.D}, p7/Z, [xzr, #-30, MUL VL]
+
+ld4q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, #-4, MUL VL]
+ld4q {Z28.Q, Z29.Q, Z30.Q,Z31.Q}, p9/Z, [x0, #-4, MUL VL]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7/Z, [x0, #-3, MUL VL]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x31, #-4, MUL VL]
+ld4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7/Z, [x30, #-4, MUL VL]
+ld4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7/Z, [x30, #-100, MUL VL]
+ld4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7/Z, [xzr, #-100, MUL VL]
+
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, x0, LSL #3]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [sp, x0, LSL #3]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, sp, LSL #3]
+ld2q {Z31.Q, Z31.Q}, p0/Z, [x0, x0, LSL #4]
+ld2q {Z0.Q, Z1.Q}, p8/Z, [x0, x0, LSL #4]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x31, x0, LSL #4]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, x31, LSL #4]
+ld2q {Z30.Q, Z31.Q}, p7/Z, [x31, x31, LSL #4]
+
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, x0, #4]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [sp, x0, #4]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, sp, #4]
+ld3q {Z29.Q, Z30.Q, Z31.Q}, p0/Z, [x0, x0, LSL #2]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p7/M, [x0, x0, LSL #4]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p8/Z, [x30, x0, LSL #4]
+ld3q {Z4.Q, Z1.Q, Z2.Q}, p0/Z, [x31, x30, LSL #4]
+ld3q {Z29.D, Z30.Q, Z31.Q}, p7/Z, [x31, x30, LSL #4]
+
+ld4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, x0, LSL #4]
+ld4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [sp, x0, LSL #4]
+ld4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, sp, LSL #4]
+ld4q {Z30.Q, Z29.Q, Z30.Q,Z31.Q}, p8/Z, [x0, x0, LSL #4]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7/Z, [x0, x0, LSL #2]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x31, x0, LSL #4]
+ld4q {Z0.Q, Z1.Q, Z2.D, Z3.Q}, p0/Z, [x1, x30, LSL #4]
+ld4q {Z2.Q, Z29.Q, Z30.Q, Z31.Q}, p7/Z, [x30, x30, LSL #4]
+
+st1q Z0.Q , P0, [Z0.D, x0]
+st1q { Z0.Q }, P8, [Z0.D, x0]
+st1q { Z0.Q }, P0, [Z31.Q, x0]
+st1q { Z0.Q }, P0, [Z0.D, x31]
+st1q { Z31.D }, P7, [Z31.D, x30]
+st1q Z0.Q , P0, [Z0.D, sp]
+st1q Z0.Q , P0, [Z0.S, x15]
+st1q Z0.Q , P0, [Z0.D, w10]
+
+st2q {Z0.Q, Z2.Q}, p0, [x0, #-2, MUL VL]
+st2q {Z31.Q, Z31.Q}, p0, [x0, #-2, MUL VL]
+st2q {Z0.Q, Z1.Q}, p8, [x0, #-2, MUL VL]
+st2q {Z0.Q, Z1.Q}, p0, [x31, #-2, MUL VL]
+st2q {Z30.Q, Z31.Q}, p7, [x30, #-3, MUL VL]
+st2q {Z0.Q, Z1.Q}, p0, [x31, #-20, MUL VL]
+st2q {Z0.Q, Z1.Q}, p0, [xzr, #-20, MUL VL]
+
+st3q {Z0.Q, Z1.Q, Z3.Q}, p0, [x0, #-3, MUL VL]
+st3q {Z29.Q, Z30.Q, Z31.Q}, p8, [x0, #-3, MUL VL]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p7, [x0, #-2, MUL VL]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x31, #-3, MUL VL]
+st3q {Z29.Q, Z30.Q, Z31.D}, p7, [x30, #-3, MUL VL]
+st3q {Z29.Q, Z30.Q, Z31.D}, p7, [x30, #-30, MUL VL]
+st3q {Z29.Q, Z30.Q, Z31.D}, p7, [xzr, #-30, MUL VL]
+
+st4q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, #-4, MUL VL]
+st4q {Z28.Q, Z29.Q, Z30.Q,Z31.Q}, p9, [x0, #-4, MUL VL]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7, [x0, #-3, MUL VL]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x31, #-4, MUL VL]
+st4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7, [x30, #-4, MUL VL]
+st4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7, [x30, #-100, MUL VL]
+st4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7, [xzr, #-100, MUL VL]
+
+st2q {Z0.Q, Z1.Q}, p0, [x0, x0, LSL #3]
+st2q {Z0.Q, Z1.Q}, p0, [sp, x0, LSL #3]
+st2q {Z0.Q, Z1.Q}, p0, [x0, sp, LSL #3]
+st2q {Z31.Q, Z31.Q}, p0, [x0, x0, LSL #4]
+st2q {Z0.Q, Z1.Q}, p8, [x0, x0, LSL #4]
+st2q {Z0.Q, Z1.Q}, p0, [x31, x0, LSL #4]
+st2q {Z0.Q, Z1.Q}, p0, [x0, x31, LSL #4]
+st2q {Z30.Q, Z31.Q}, p7, [x31, x31, LSL #4]
+
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, x0, #4]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [sp, x0, #4]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, sp, #4]
+st3q {Z29.Q, Z30.Q, Z31.Q}, p0, [x0, x0, LSL #2]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p7, [x0, x0, LSL #4]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p8, [x30, x0, LSL #4]
+st3q {Z4.Q, Z1.Q, Z2.Q}, p0, [x31, x30, LSL #4]
+st3q {Z29.D, Z30.Q, Z31.Q}, p7, [x31, x30, LSL #4]
+
+st4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, x0, LSL #4]
+st4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [sp, x0, LSL #4]
+st4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, sp, LSL #4]
+st4q {Z30.Q, Z29.Q, Z30.Q,Z31.Q}, p8, [x0, x0, LSL #4]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7, [x0, x0, LSL #2]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x31, x0, LSL #4]
+st4q {Z0.Q, Z1.Q, Z2.D, Z3.Q}, p0, [x1, x30, LSL #4]
+st4q {Z2.Q, Z29.Q, Z30.Q, Z31.Q}, p7, [x30, x30, LSL #4]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-4.d b/gas/testsuite/gas/aarch64/sve2p1-4.d
new file mode 100644
index 00000000000..e166b2d8240
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-4.d
@@ -0,0 +1,144 @@
+#name: Test of SVE2.1 ld[1-4]q/st[1-4]q instructions.
+#as: -march=armv9.4-a
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: c400a000 ld1q {z0.q}, p0/z, \[z0.d, x0\]
+.*: c400a01f ld1q {z31.q}, p0/z, \[z0.d, x0\]
+.*: c400bc00 ld1q {z0.q}, p7/z, \[z0.d, x0\]
+.*: c400a3e0 ld1q {z0.q}, p0/z, \[z31.d, x0\]
+.*: c41ea000 ld1q {z0.q}, p0/z, \[z0.d, x30\]
+.*: c41fa000 ld1q {z0.q}, p0/z, \[z0.d, xzr\]
+.*: c41ebfff ld1q {z31.q}, p7/z, \[z31.d, x30\]
+.*: c404acef ld1q {z15.q}, p3/z, \[z7.d, x4\]
+.*: a490e000 ld2q {z0.q-z1.q}, p0/z, \[x0\]
+.*: a490e01f ld2q {z31.q-z0.q}, p0/z, \[x0\]
+.*: a490fc00 ld2q {z0.q-z1.q}, p7/z, \[x0\]
+.*: a490e3c0 ld2q {z0.q-z1.q}, p0/z, \[x30\]
+.*: a498e000 ld2q {z0.q-z1.q}, p0/z, \[x0, #-16, mul vl\]
+.*: a497e000 ld2q {z0.q-z1.q}, p0/z, \[x0, #14, mul vl\]
+.*: a498ffdf ld2q {z31.q-z0.q}, p7/z, \[x30, #-16, mul vl\]
+.*: a49be7e1 ld2q {z1.q-z2.q}, p1/z, \[sp, #-10, mul vl\]
+.*: a49fe47e ld2q {z30.q-z31.q}, p1/z, \[x3, #-2, mul vl\]
+.*: a510e000 ld3q {z0.q-z2.q}, p0/z, \[x0\]
+.*: a510e01f ld3q {z31.q-z1.q}, p0/z, \[x0\]
+.*: a510fc00 ld3q {z0.q-z2.q}, p7/z, \[x0\]
+.*: a510e3c0 ld3q {z0.q-z2.q}, p0/z, \[x30\]
+.*: a518e000 ld3q {z0.q-z2.q}, p0/z, \[x0, #-24, mul vl\]
+.*: a517e000 ld3q {z0.q-z2.q}, p0/z, \[x0, #21, mul vl\]
+.*: a518ffdf ld3q {z31.q-z1.q}, p7/z, \[x30, #-24, mul vl\]
+.*: a51fffdd ld3q {z29.q-z31.q}, p7/z, \[x30, #-3, mul vl\]
+.*: a51fffdd ld3q {z29.q-z31.q}, p7/z, \[x30, #-3, mul vl\]
+.*: a51ce7e1 ld3q {z1.q-z3.q}, p1/z, \[sp, #-12, mul vl\]
+.*: a51fffdd ld3q {z29.q-z31.q}, p7/z, \[x30, #-3, mul vl\]
+.*: a590e000 ld4q {z0.q-z3.q}, p0/z, \[x0\]
+.*: a590e01f ld4q {z31.q-z2.q}, p0/z, \[x0\]
+.*: a590fc00 ld4q {z0.q-z3.q}, p7/z, \[x0\]
+.*: a590e3c0 ld4q {z0.q-z3.q}, p0/z, \[x30\]
+.*: a598e000 ld4q {z0.q-z3.q}, p0/z, \[x0, #-32, mul vl\]
+.*: a597e000 ld4q {z0.q-z3.q}, p0/z, \[x0, #28, mul vl\]
+.*: a598ffdf ld4q {z31.q-z2.q}, p7/z, \[x30, #-32, mul vl\]
+.*: a59fffdc ld4q {z28.q-z31.q}, p7/z, \[x30, #-4, mul vl\]
+.*: a59fffdc ld4q {z28.q-z31.q}, p7/z, \[x30, #-4, mul vl\]
+.*: a59cf3e1 ld4q {z1.q-z4.q}, p4/z, \[sp, #-16, mul vl\]
+.*: a59fffdc ld4q {z28.q-z31.q}, p7/z, \[x30, #-4, mul vl\]
+.*: a4a08000 ld2q {z0.q-z1.q}, p0/z, \[x0, x0, lsl #4\]
+.*: a4a0801f ld2q {z31.q-z0.q}, p0/z, \[x0, x0, lsl #4\]
+.*: a4a09c00 ld2q {z0.q-z1.q}, p7/z, \[x0, x0, lsl #4\]
+.*: a4a083c0 ld2q {z0.q-z1.q}, p0/z, \[x30, x0, lsl #4\]
+.*: a4be8000 ld2q {z0.q-z1.q}, p0/z, \[x0, x30, lsl #4\]
+.*: a4be9fdf ld2q {z31.q-z0.q}, p7/z, \[x30, x30, lsl #4\]
+.*: a4b4914f ld2q {z15.q-z16.q}, p4/z, \[x10, x20, lsl #4\]
+.*: a4b48ff4 ld2q {z20.q-z21.q}, p3/z, \[sp, x20, lsl #4\]
+.*: a5208000 ld3q {z0.q-z2.q}, p0/z, \[x0, x0, lsl #4\]
+.*: a520801f ld3q {z31.q-z1.q}, p0/z, \[x0, x0, lsl #4\]
+.*: a5209c00 ld3q {z0.q-z2.q}, p7/z, \[x0, x0, lsl #4\]
+.*: a52083c0 ld3q {z0.q-z2.q}, p0/z, \[x30, x0, lsl #4\]
+.*: a53e8000 ld3q {z0.q-z2.q}, p0/z, \[x0, x30, lsl #4\]
+.*: a53e9fdf ld3q {z31.q-z1.q}, p7/z, \[x30, x30, lsl #4\]
+.*: a534894a ld3q {z10.q-z12.q}, p2/z, \[x10, x20, lsl #4\]
+.*: a534894a ld3q {z10.q-z12.q}, p2/z, \[x10, x20, lsl #4\]
+.*: a534894a ld3q {z10.q-z12.q}, p2/z, \[x10, x20, lsl #4\]
+.*: a53497ef ld3q {z15.q-z17.q}, p5/z, \[sp, x20, lsl #4\]
+.*: a5a08000 ld4q {z0.q-z3.q}, p0/z, \[x0, x0, lsl #4\]
+.*: a5a0801f ld4q {z31.q-z2.q}, p0/z, \[x0, x0, lsl #4\]
+.*: a5a09c00 ld4q {z0.q-z3.q}, p7/z, \[x0, x0, lsl #4\]
+.*: a5a083c0 ld4q {z0.q-z3.q}, p0/z, \[x30, x0, lsl #4\]
+.*: a5be8000 ld4q {z0.q-z3.q}, p0/z, \[x0, x30, lsl #4\]
+.*: a5be9fdf ld4q {z31.q-z2.q}, p7/z, \[x30, x30, lsl #4\]
+.*: a5a4886a ld4q {z10.q-z13.q}, p2/z, \[x3, x4, lsl #4\]
+.*: a5a4886a ld4q {z10.q-z13.q}, p2/z, \[x3, x4, lsl #4\]
+.*: a5a4886a ld4q {z10.q-z13.q}, p2/z, \[x3, x4, lsl #4\]
+.*: a5a48bea ld4q {z10.q-z13.q}, p2/z, \[sp, x4, lsl #4\]
+.*: e4202000 st1q {z0.q}, p0, \[z0.d, x0\]
+.*: e420201f st1q {z31.q}, p0, \[z0.d, x0\]
+.*: e4203c00 st1q {z0.q}, p7, \[z0.d, x0\]
+.*: e42023e0 st1q {z0.q}, p0, \[z31.d, x0\]
+.*: e43e2000 st1q {z0.q}, p0, \[z0.d, x30\]
+.*: e43f2000 st1q {z0.q}, p0, \[z0.d, xzr\]
+.*: e43e3fff st1q {z31.q}, p7, \[z31.d, x30\]
+.*: e4242cef st1q {z15.q}, p3, \[z7.d, x4\]
+.*: e4400000 st2q {z0.q-z1.q}, p0, \[x0\]
+.*: e440001f st2q {z31.q-z0.q}, p0, \[x0\]
+.*: e4401c00 st2q {z0.q-z1.q}, p7, \[x0\]
+.*: e44003c0 st2q {z0.q-z1.q}, p0, \[x30\]
+.*: e4480000 st2q {z0.q-z1.q}, p0, \[x0, #-16, mul vl\]
+.*: e4470000 st2q {z0.q-z1.q}, p0, \[x0, #14, mul vl\]
+.*: e4481fdf st2q {z31.q-z0.q}, p7, \[x30, #-16, mul vl\]
+.*: e44b07e1 st2q {z1.q-z2.q}, p1, \[sp, #-10, mul vl\]
+.*: e44f047e st2q {z30.q-z31.q}, p1, \[x3, #-2, mul vl\]
+.*: e4800000 st3q {z0.q-z2.q}, p0, \[x0\]
+.*: e480001f st3q {z31.q-z1.q}, p0, \[x0\]
+.*: e4801c00 st3q {z0.q-z2.q}, p7, \[x0\]
+.*: e48003c0 st3q {z0.q-z2.q}, p0, \[x30\]
+.*: e4880000 st3q {z0.q-z2.q}, p0, \[x0, #-24, mul vl\]
+.*: e4870000 st3q {z0.q-z2.q}, p0, \[x0, #21, mul vl\]
+.*: e4881fdf st3q {z31.q-z1.q}, p7, \[x30, #-24, mul vl\]
+.*: e48f1fdd st3q {z29.q-z31.q}, p7, \[x30, #-3, mul vl\]
+.*: e48f1fdd st3q {z29.q-z31.q}, p7, \[x30, #-3, mul vl\]
+.*: e48c07e1 st3q {z1.q-z3.q}, p1, \[sp, #-12, mul vl\]
+.*: e48f1fdd st3q {z29.q-z31.q}, p7, \[x30, #-3, mul vl\]
+.*: e4c00000 st4q {z0.q-z3.q}, p0, \[x0\]
+.*: e4c0001f st4q {z31.q-z2.q}, p0, \[x0\]
+.*: e4c01c00 st4q {z0.q-z3.q}, p7, \[x0\]
+.*: e4c003c0 st4q {z0.q-z3.q}, p0, \[x30\]
+.*: e4c80000 st4q {z0.q-z3.q}, p0, \[x0, #-32, mul vl\]
+.*: e4c70000 st4q {z0.q-z3.q}, p0, \[x0, #28, mul vl\]
+.*: e4c81fdf st4q {z31.q-z2.q}, p7, \[x30, #-32, mul vl\]
+.*: e4cf1fdc st4q {z28.q-z31.q}, p7, \[x30, #-4, mul vl\]
+.*: e4cf1fdc st4q {z28.q-z31.q}, p7, \[x30, #-4, mul vl\]
+.*: e4cc13e1 st4q {z1.q-z4.q}, p4, \[sp, #-16, mul vl\]
+.*: e4cf1fdc st4q {z28.q-z31.q}, p7, \[x30, #-4, mul vl\]
+.*: e4600000 st2q {z0.q-z1.q}, p0, \[x0, x0, lsl #4\]
+.*: e460001f st2q {z31.q-z0.q}, p0, \[x0, x0, lsl #4\]
+.*: e4601c00 st2q {z0.q-z1.q}, p7, \[x0, x0, lsl #4\]
+.*: e46003c0 st2q {z0.q-z1.q}, p0, \[x30, x0, lsl #4\]
+.*: e47e0000 st2q {z0.q-z1.q}, p0, \[x0, x30, lsl #4\]
+.*: e47e1fdf st2q {z31.q-z0.q}, p7, \[x30, x30, lsl #4\]
+.*: e474114f st2q {z15.q-z16.q}, p4, \[x10, x20, lsl #4\]
+.*: e4740ff4 st2q {z20.q-z21.q}, p3, \[sp, x20, lsl #4\]
+.*: e4a00000 st3q {z0.q-z2.q}, p0, \[x0, x0, lsl #4\]
+.*: e4a0001f st3q {z31.q-z1.q}, p0, \[x0, x0, lsl #4\]
+.*: e4a01c00 st3q {z0.q-z2.q}, p7, \[x0, x0, lsl #4\]
+.*: e4a003c0 st3q {z0.q-z2.q}, p0, \[x30, x0, lsl #4\]
+.*: e4be0000 st3q {z0.q-z2.q}, p0, \[x0, x30, lsl #4\]
+.*: e4be1fdf st3q {z31.q-z1.q}, p7, \[x30, x30, lsl #4\]
+.*: e4b4094a st3q {z10.q-z12.q}, p2, \[x10, x20, lsl #4\]
+.*: e4b4094a st3q {z10.q-z12.q}, p2, \[x10, x20, lsl #4\]
+.*: e4b4094a st3q {z10.q-z12.q}, p2, \[x10, x20, lsl #4\]
+.*: e4b417ef st3q {z15.q-z17.q}, p5, \[sp, x20, lsl #4\]
+.*: e4e00000 st4q {z0.q-z3.q}, p0, \[x0, x0, lsl #4\]
+.*: e4e0001f st4q {z31.q-z2.q}, p0, \[x0, x0, lsl #4\]
+.*: e4e01c00 st4q {z0.q-z3.q}, p7, \[x0, x0, lsl #4\]
+.*: e4e003c0 st4q {z0.q-z3.q}, p0, \[x30, x0, lsl #4\]
+.*: e4fe0000 st4q {z0.q-z3.q}, p0, \[x0, x30, lsl #4\]
+.*: e4fe1fdf st4q {z31.q-z2.q}, p7, \[x30, x30, lsl #4\]
+.*: e4e4086a st4q {z10.q-z13.q}, p2, \[x3, x4, lsl #4\]
+.*: e4e4086a st4q {z10.q-z13.q}, p2, \[x3, x4, lsl #4\]
+.*: e4e4086a st4q {z10.q-z13.q}, p2, \[x3, x4, lsl #4\]
+.*: e4e40bea st4q {z10.q-z13.q}, p2, \[sp, x4, lsl #4\]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-4.s b/gas/testsuite/gas/aarch64/sve2p1-4.s
new file mode 100644
index 00000000000..000544625e9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-4.s
@@ -0,0 +1,147 @@
+ld1q { Z0.Q }, P0/Z, [Z0.D, x0]
+ld1q { Z31.Q }, P0/Z, [Z0.D, x0]
+ld1q { Z0.Q }, P7/Z, [Z0.D, x0]
+ld1q { Z0.Q }, P0/Z, [Z31.D, x0]
+ld1q { Z0.Q }, P0/Z, [Z0.D, x30]
+ld1q { Z0.Q }, P0/Z, [Z0.D, xzr]
+ld1q { Z31.Q }, P7/Z, [Z31.D, x30]
+ld1q { Z15.Q }, P3/Z, [Z7.D, x4]
+
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL]
+ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, #0, MUL VL]
+ld2q {Z0.Q, Z1.Q}, p7/Z, [x0, #0, MUL VL]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x30, #0, MUL VL]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #-16, MUL VL]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #14, MUL VL]
+ld2q {Z31.Q, Z0.Q}, p7/Z, [x30, #-16, MUL VL]
+ld2q {Z1.Q, Z2.Q}, p1/Z, [sp, #-10, MUL VL]
+ld2q {Z30.Q, Z31.Q}, p1/Z, [x3, #-2, MUL VL]
+
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, #0, MUL VL]
+ld3q {Z31.Q, Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x0, #0, MUL VL]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x30, #0, MUL VL]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, #-24, MUL VL]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, #21, MUL VL]
+ld3q {Z31.Q, Z0.Q, Z1.Q}, p7/Z, [x30, #-24, MUL VL]
+ld3q {Z29.Q, Z30.Q, Z31.Q}, p7/Z, [x30, #-3, MUL VL]
+ld3q {Z29.Q - Z30.Q - Z31.Q}, p7/Z, [x30, #-3, MUL VL]
+ld3q {Z1.Q, Z2.Q, z3.Q}, p1/Z, [sp, #-12, MUL VL]
+ld3q {Z29.Q - Z31.Q}, p7/Z, [x30, #-3, MUL VL]
+
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, #0, MUL VL]
+ld4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, #0, MUL VL]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7/Z, [x0, #0, MUL VL]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x30, #0, MUL VL]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, #-32, MUL VL]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, #28, MUL VL]
+ld4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x30, #-32, MUL VL]
+ld4q {Z28.Q, Z29.Q, Z30.Q, Z31.Q}, p7/Z, [x30, #-4, MUL VL]
+ld4q {Z28.Q - Z29.Q - Z30.Q - Z31.Q}, p7/Z, [x30, #-4, MUL VL]
+ld4q {Z1.Q, Z2.Q, z3.Q, Z4.Q}, p4/Z, [sp, #-16, MUL VL]
+ld4q {Z28.Q - Z31.Q}, p7/Z, [x30, #-4, MUL VL]
+
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, x0, LSL #4]
+ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, x0, LSL #4]
+ld2q {Z0.Q, Z1.Q}, p7/Z, [x0, x0, LSL #4]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x30, x0, LSL #4]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, x30, LSL #4]
+ld2q {Z31.Q, Z0.Q}, p7/Z, [x30, x30, LSL #4]
+ld2q {Z15.Q, Z16.Q}, p4/Z, [x10, x20, LSL #4]
+ld2q {Z20.Q, Z21.Q}, p3/Z, [sp, x20, LSL #4]
+
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, x0, LSL #4]
+ld3q {Z31.Q, Z0.Q, Z1.Q}, p0/Z, [x0, x0, LSL #4]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x0, x0, LSL #4]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x30, x0, LSL #4]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, x30, LSL #4]
+ld3q {Z31.Q, Z0.Q, Z1.Q}, p7/Z, [x30, x30, LSL #4]
+ld3q {Z10.Q, Z11.Q, Z12.Q}, p2/Z, [x10, x20, LSL #4]
+ld3q {Z10.Q - Z11.Q - Z12.Q}, p2/Z, [x10, x20, LSL #4]
+ld3q {Z10.Q - Z12.Q}, p2/Z, [x10, x20, LSL #4]
+ld3q {Z15.Q - Z17.Q}, p5/Z, [sp, x20, LSL #4]
+
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, x0, LSL #4]
+ld4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, x0, LSL #4]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7/Z, [x0, x0, LSL #4]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x30, x0, LSL #4]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, x30, LSL #4]
+ld4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x30, x30, LSL #4]
+ld4q {Z10.Q, Z11.Q, Z12.Q, Z13.Q}, p2/Z, [x3, x4, LSL #4]
+ld4q {Z10.Q - Z11.Q - Z12.Q - Z13.Q}, p2/Z, [x3, x4, LSL #4]
+ld4q {Z10.Q - Z13.Q}, p2/Z, [x3, x4, LSL #4]
+ld4q {Z10.Q, Z11.Q, Z12.Q, Z13.Q}, p2/Z, [sp, x4, LSL #4]
+
+st1q { Z0.Q }, P0, [Z0.D, x0]
+st1q { Z31.Q }, P0, [Z0.D, x0]
+st1q { Z0.Q }, P7, [Z0.D, x0]
+st1q { Z0.Q }, P0, [Z31.D, x0]
+st1q { Z0.Q }, P0, [Z0.D, x30]
+st1q { Z0.Q }, P0, [Z0.D, xzr]
+st1q { Z31.Q }, P7, [Z31.D, x30]
+st1q { Z15.Q }, P3, [Z7.D, x4]
+
+st2q {Z0.Q, Z1.Q}, p0, [x0, #0, MUL VL]
+st2q {Z31.Q, Z0.Q}, p0, [x0, #0, MUL VL]
+st2q {Z0.Q, Z1.Q}, p7, [x0, #0, MUL VL]
+st2q {Z0.Q, Z1.Q}, p0, [x30, #0, MUL VL]
+st2q {Z0.Q, Z1.Q}, p0, [x0, #-16, MUL VL]
+st2q {Z0.Q, Z1.Q}, p0, [x0, #14, MUL VL]
+st2q {Z31.Q, Z0.Q}, p7, [x30, #-16, MUL VL]
+st2q {Z1.Q, Z2.Q}, p1, [sp, #-10, MUL VL]
+st2q {Z30.Q, Z31.Q}, p1, [x3, #-2, MUL VL]
+
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, #0, MUL VL]
+st3q {Z31.Q, Z0.Q, Z1.Q}, p0, [x0, #0, MUL VL]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p7, [x0, #0, MUL VL]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x30, #0, MUL VL]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, #-24, MUL VL]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, #21, MUL VL]
+st3q {Z31.Q, Z0.Q, Z1.Q}, p7, [x30, #-24, MUL VL]
+st3q {Z29.Q, Z30.Q, Z31.Q}, p7, [x30, #-3, MUL VL]
+st3q {Z29.Q - Z30.Q - Z31.Q}, p7, [x30, #-3, MUL VL]
+st3q {Z1.Q, Z2.Q, z3.Q}, p1, [sp, #-12, MUL VL]
+st3q {Z29.Q - Z31.Q}, p7, [x30, #-3, MUL VL]
+
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, #0, MUL VL]
+st4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p0, [x0, #0, MUL VL]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7, [x0, #0, MUL VL]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x30, #0, MUL VL]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, #-32, MUL VL]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, #28, MUL VL]
+st4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p7, [x30, #-32, MUL VL]
+st4q {Z28.Q, Z29.Q, Z30.Q, Z31.Q}, p7, [x30, #-4, MUL VL]
+st4q {Z28.Q - Z29.Q - Z30.Q - Z31.Q}, p7, [x30, #-4, MUL VL]
+st4q {Z1.Q, Z2.Q, z3.Q, Z4.Q}, p4, [sp, #-16, MUL VL]
+st4q {Z28.Q - Z31.Q}, p7, [x30, #-4, MUL VL]
+
+st2q {Z0.Q, Z1.Q}, p0, [x0, x0, LSL #4]
+st2q {Z31.Q, Z0.Q}, p0, [x0, x0, LSL #4]
+st2q {Z0.Q, Z1.Q}, p7, [x0, x0, LSL #4]
+st2q {Z0.Q, Z1.Q}, p0, [x30, x0, LSL #4]
+st2q {Z0.Q, Z1.Q}, p0, [x0, x30, LSL #4]
+st2q {Z31.Q, Z0.Q}, p7, [x30, x30, LSL #4]
+st2q {Z15.Q, Z16.Q}, p4, [x10, x20, LSL #4]
+st2q {Z20.Q, Z21.Q}, p3, [sp, x20, LSL #4]
+
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, x0, LSL #4]
+st3q {Z31.Q, Z0.Q, Z1.Q}, p0, [x0, x0, LSL #4]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p7, [x0, x0, LSL #4]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x30, x0, LSL #4]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, x30, LSL #4]
+st3q {Z31.Q, Z0.Q, Z1.Q}, p7, [x30, x30, LSL #4]
+st3q {Z10.Q, Z11.Q, Z12.Q}, p2, [x10, x20, LSL #4]
+st3q {Z10.Q - Z11.Q - Z12.Q}, p2, [x10, x20, LSL #4]
+st3q {Z10.Q - Z12.Q}, p2, [x10, x20, LSL #4]
+st3q {Z15.Q - Z17.Q}, p5, [sp, x20, LSL #4]
+
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, x0, LSL #4]
+st4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p0, [x0, x0, LSL #4]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7, [x0, x0, LSL #4]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x30, x0, LSL #4]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, x30, LSL #4]
+st4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p7, [x30, x30, LSL #4]
+st4q {Z10.Q, Z11.Q, Z12.Q, Z13.Q}, p2, [x3, x4, LSL #4]
+st4q {Z10.Q - Z11.Q - Z12.Q - Z13.Q}, p2, [x3, x4, LSL #4]
+st4q {Z10.Q - Z13.Q}, p2, [x3, x4, LSL #4]
+st4q {Z10.Q, Z11.Q, Z12.Q, Z13.Q}, p2, [sp, x4, LSL #4]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 2d4b011db1b..967158247d3 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -817,9 +817,6 @@ enum aarch64_opnd
AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */
AARCH64_OPND_CSSC_SIMM8, /* CSSC signed 8-bit immediate. */
AARCH64_OPND_CSSC_UIMM8, /* CSSC unsigned 8-bit immediate. */
- AARCH64_OPND_SME_Zt2, /* Qobule SVE vector register list. */
- AARCH64_OPND_SME_Zt3, /* Trible SVE vector register list. */
- AARCH64_OPND_SME_Zt4, /* Quad SVE vector register list. */
AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND, /* [<Xn|SP>]{, #<imm>}. */
AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB, /* [<Xn|SP>] or [<Xn|SP>, #<imm>]!. */
AARCH64_OPND_RCPC3_ADDR_POSTIND, /* [<Xn|SP>], #<imm>. */
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index ad9b132fb23..cf4df9b27e4 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1913,9 +1913,6 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_SME_Zmx4:
case AARCH64_OPND_SME_Znx2:
case AARCH64_OPND_SME_Znx4:
- case AARCH64_OPND_SME_Zt2:
- case AARCH64_OPND_SME_Zt3:
- case AARCH64_OPND_SME_Zt4:
num = get_operand_specific_data (&aarch64_operands[type]);
if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
return 0;
@@ -3735,10 +3732,7 @@ print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
/* The hyphenated form is preferred for disassembly if there is
more than one register in the list, and the register numbers
are monotonically increasing in increments of one. */
- if (stride == 1 && num_regs > 1
- && ((opnd->type != AARCH64_OPND_SME_Zt2)
- && (opnd->type != AARCH64_OPND_SME_Zt3)
- && (opnd->type != AARCH64_OPND_SME_Zt4)))
+ if (stride == 1 && num_regs > 1)
snprintf (buf, size, "{%s-%s}%s",
style_reg (styler, "%s%d.%s", prefix, first_reg, qlf_name),
style_reg (styler, "%s%d.%s", prefix, last_reg, qlf_name), tb);
@@ -4206,9 +4200,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SME_Znx4:
case AARCH64_OPND_SME_Ztx2_STRIDED:
case AARCH64_OPND_SME_Ztx4_STRIDED:
- case AARCH64_OPND_SME_Zt2:
- case AARCH64_OPND_SME_Zt3:
- case AARCH64_OPND_SME_Zt4:
print_register_list (buf, size, opnd, "z", styler);
break;
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index b524cbe0ec8..8ab7c1315a1 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1825,11 +1825,11 @@
{ \
QLF3(S_S,P_Z,S_S), \
}
-#define OP_SVE_SZS_QD \
+#define OP_SVE_QZD \
{ \
QLF3(S_Q,P_Z,S_D), \
}
-#define OP_SVE_SUS_QD \
+#define OP_SVE_QUD \
{ \
QLF3(S_Q,NIL,S_D), \
}
@@ -6520,21 +6520,23 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
- SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("ld4q",0xa590e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("ld2q",0xa4a08000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("ld3q",0xa5208000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("ld4q",0xa5a08000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("st1q",0xe4202000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SUS_QD, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("st2q",0xe4400000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("st3q",0xe4800000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("st4q",0xe4c00000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("st2q",0xe4600000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p1_INSN("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QZD, F_OD (1), 0),
+ SVE2p1_INSN("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, F_OD (2), 0),
+ SVE2p1_INSN("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, F_OD (3), 0),
+ SVE2p1_INSN("ld4q",0xa590e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QZU, F_OD (4), 0),
+ SVE2p1_INSN("ld2q",0xa4a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, F_OD (2), 0),
+ SVE2p1_INSN("ld3q",0xa5208000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, F_OD (3), 0),
+ SVE2p1_INSN("ld4q",0xa5a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, F_OD (4), 0),
+
+ SVE2p1_INSN("st1q",0xe4202000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QUD, F_OD (1), 0),
+ SVE2p1_INSN("st2q",0xe4400000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, F_OD (2), 0),
+ SVE2p1_INSN("st3q",0xe4800000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QUU, F_OD (3), 0),
+ SVE2p1_INSN("st4q",0xe4c00000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QUU, F_OD (4), 0),
+ SVE2p1_INSN("st2q",0xe4600000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, F_OD (2), 0),
+ SVE2p1_INSN("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, F_OD (3), 0),
+ SVE2p1_INSN("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, F_OD (4), 0),
+
FP8_INSN("bf1cvtl", 0x2ea17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2FP8B8H, 0),
FP8_INSN("bf1cvtl2", 0x6ea17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V28H16B, 0),
FP8_INSN("bf2cvtl", 0x2ee17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2FP8B8H, 0),
@@ -7262,15 +7264,6 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"an 8-bit signed immediate") \
Y(IMMEDIATE, imm, "CSSC_UIMM8", 0, F(FLD_CSSC_imm8), \
"an 8-bit unsigned immediate") \
- X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SME_Zt2", \
- 2 << OPD_F_OD_LSB, F(FLD_SVE_Zt), \
- "a list of 2 SVE vector registers") \
- X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SME_Zt3", \
- 3 << OPD_F_OD_LSB, F(FLD_SVE_Zt), \
- "a list of 3 SVE vector registers") \
- X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SME_Zt4", \
- 4 << OPD_F_OD_LSB, F(FLD_SVE_Zt), \
- "a list of 4 SVE vector registers") \
X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \
"RCPC3_ADDR_OPT_POSTIND", 0, F(FLD_opc2), \
"an address with post-incrementing by ammount of loaded bytes") \
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v2 06/11] [Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.
2024-06-12 15:59 ` [PATCH v2 06/11] [Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands srinath
@ 2024-06-13 15:10 ` Richard Earnshaw (lists)
0 siblings, 0 replies; 18+ messages in thread
From: Richard Earnshaw (lists) @ 2024-06-13 15:10 UTC (permalink / raw)
To: srinath, binutils; +Cc: nickc
On 12/06/2024 16:59, srinath wrote:
>
> Hi,
>
> This patch fixes encoding and syntax for sve2p1 instructions ld[1-4]q/st[1-4]q
> as mentioned below, for the issues reported here.
> https://sourceware.org/pipermail/binutils/2024-February/132408.html
>
> 1) Previously all the ld[1-4]q/st[1-4]q instructions are wrongly added as
> predicated instructions and this issue is fixed in this patch by replacing
> "SVE2p1_INSNC" with "SVE2p1_INSN" macro.
> 2) Wrong first operand in all the ld[1-4]q/st[1-4]q instructions is fixed
> by replacing "SVE_Zt" with "SVE_ZtxN".
> 3) Wrong operand qualifiers in ld1q and st1q instructions are also fixed in
> this patch.
>
> Fixing above mentioned issues helps with following:
> 1) ld1q and st1q first register operand accepts enclosed figure braces.
> 2) ld2q, ld3q, ld4q, st2q, st3q, and st4q instructions accepts wrapping
> sequence of vector registers.
>
> For the instructions ld[2-4]q/st[2-4]q, tests for wrapping sequence of vector
> registers are added along with short-form of operands for non-wrapping sequence.
>
> I have added test using following logic:
> ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL] //raw insn encoding (all zeroes)
> ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, #0, MUL VL] // encoding of <Zt1>
> ld2q {Z0.Q, Z1.Q}, p7/Z, [x0, #0, MUL VL] // encoding of <Pg>
> ld2q {Z0.Q, Z1.Q}, p0/Z, [x30, #0, MUL VL] // encoding of <Xm>
> ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #-16, MUL VL] // encoding of <imm> (low value)
> ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #14, MUL VL] // encoding of <imm> (high value)
> ld2q {Z31.Q, Z0.Q}, p7/Z, [x30, #-16, MUL VL] // encoding of all fields (all ones)
> ld2q {Z30.Q, Z31.Q}, p1/Z, [x3, #-2, MUL VL] // random encoding.
>
> For all the above form of instructions the hyphenated form is preferred for
> disassembly if there are more than one register in the list, and the register
> numbers are monotonically increasing in increments of one.
>
> Regression testing for aarch64-none-elf target and found no regressions.
>
> Ok for binutils-master?
>
> Regards,
> Srinath.
> ---
> gas/config/tc-aarch64.c | 3 -
> gas/testsuite/gas/aarch64/sme-5-illegal.l | 8 +-
> gas/testsuite/gas/aarch64/sme-6-illegal.l | 8 +-
> gas/testsuite/gas/aarch64/sve2p1-1-bad.l | 14 --
> gas/testsuite/gas/aarch64/sve2p1-1.d | 14 --
> gas/testsuite/gas/aarch64/sve2p1-1.s | 15 --
> gas/testsuite/gas/aarch64/sve2p1-4-invalid.d | 3 +
> gas/testsuite/gas/aarch64/sve2p1-4-invalid.l | 116 +++++++++++++++
> gas/testsuite/gas/aarch64/sve2p1-4-invalid.s | 119 +++++++++++++++
> gas/testsuite/gas/aarch64/sve2p1-4.d | 144 ++++++++++++++++++
> gas/testsuite/gas/aarch64/sve2p1-4.s | 147 +++++++++++++++++++
> include/opcode/aarch64.h | 3 -
> opcodes/aarch64-opc.c | 11 +-
> opcodes/aarch64-tbl.h | 43 +++---
> 14 files changed, 556 insertions(+), 92 deletions(-)
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4-invalid.d
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4-invalid.l
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4-invalid.s
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4.d
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4.s
>
+.*: c41fa000 ld1q {z0.q}, p0/z, \[z0.d, xzr\]
The specification for this says
LD1Q { <Zt>.Q }, <Pg>/Z, [<Zn>.D{, <Xm>}]
and further says that Xm defaults to Xzr when omitted. So I would have thought the preferred disassembly for this case would be to omit the zero register, giving
ld1q {z0.q}, p0/z, [z0.d]
as the output.
----
On a related note, I think we need a parsing test for the omitted argument as well, so:
+ld1q { Z0.Q }, P0/Z, [Z0.D, xzr]
+ld1q { Z0.Q }, P0/Z, [Z0.D]
----
A similar issue for disassembly with this case:
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL]
and the other (ld3q/ld4q) cases. When the immediate is 0, we should also test
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x0]
(we do disassemble to this form, I see)
----
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, x30, LSL #4]
I think it would be better to test for
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, xzr, LSL #4]
Here as that tests all the bits of the Rm field.
----
And similarly for the store, of course.
R.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v1 07/11] [Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands (regenerated files).
2024-06-12 15:58 [PATCH v2 0/11][Binutils] aarch64: Fix the FEAT_SVE2p1 related issues srinath
` (5 preceding siblings ...)
2024-06-12 15:59 ` [PATCH v2 06/11] [Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands srinath
@ 2024-06-12 15:59 ` srinath
2024-06-12 15:59 ` [PATCH v1 08/11] [BINUTILS] aarch64: Fix the wrong constraint used for sve2p1 instructions srinath
` (3 subsequent siblings)
10 siblings, 0 replies; 18+ messages in thread
From: srinath @ 2024-06-12 15:59 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, srinath
[-- Attachment #1: Type: text/plain, Size: 310 bytes --]
Hi,
This patch includes the regenerated files for
[Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.
Regards,
Srinath.
---
opcodes/aarch64-asm-2.c | 11 ++++-------
opcodes/aarch64-dis-2.c | 6 +-----
opcodes/aarch64-opc-2.c | 3 ---
3 files changed, 5 insertions(+), 15 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0007-Binutils-aarch64-Fix-sve2p1-ld-1-4-st-1-4-q-instr.patch --]
[-- Type: text/x-patch; name="v1-0007-Binutils-aarch64-Fix-sve2p1-ld-1-4-st-1-4-q-instr.patch", Size: 3265 bytes --]
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index f7c36d6f262..3b2b68b57db 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -954,9 +954,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 239:
case 241:
case 258:
- case 304:
- case 305:
- case 306:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 242:
case 243:
@@ -996,12 +993,12 @@ aarch64_insert_operand (const aarch64_operand *self,
case 300:
case 301:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
+ case 304:
+ case 305:
+ case 306:
case 307:
- case 308:
- case 309:
- case 310:
return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
- case 311:
+ case 308:
return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index a85b5c434f0..477cd6feb22 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -34001,13 +34001,9 @@ aarch64_extract_operand (const aarch64_operand *self,
case 304:
case 305:
case 306:
- return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors);
case 307:
- case 308:
- case 309:
- case 310:
return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
- case 311:
+ case 308:
return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index b0a5ccb4a83..5eb96d5ec4a 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -328,9 +328,6 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"},
{AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit signed immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 2 SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 3 SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 4 SVE vector registers"},
{AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_opc2}, "an address with post-incrementing by ammount of loaded bytes"},
{AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_PREIND_WB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_opc2}, "an address with pre-incrementing with write-back by ammount of stored bytes"},
{AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with post-incrementing by ammount of loaded bytes"},
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH v1 08/11] [BINUTILS] aarch64: Fix the wrong constraint used for sve2p1 instructions.
2024-06-12 15:58 [PATCH v2 0/11][Binutils] aarch64: Fix the FEAT_SVE2p1 related issues srinath
` (6 preceding siblings ...)
2024-06-12 15:59 ` [PATCH v1 07/11] [Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands (regenerated files) srinath
@ 2024-06-12 15:59 ` srinath
2024-06-12 15:59 ` [PATCH v1 09/11] [Binutils] aarch64: Add extra tests for sve2p1 min max instructions srinath
` (2 subsequent siblings)
10 siblings, 0 replies; 18+ messages in thread
From: srinath @ 2024-06-12 15:59 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 1248 bytes --]
HI,
The current implementation for the following SVE2p1 instructions add a constraint in aarch64_opcode_table[]
array, so that these instruction might be immediately preceded in program order by a MOVPRFX instruction.
As per the spec these instruction does not immediately preceded in program order by a MOVPRFX instruction
and to fix this issue, SVE2p1_INSNC macro is replaced with SVE2p1_INSN macro for the entries of these
instructions in aarch64_opcode_table[] array.
List of instructions updated: addqv, andqv, smaxqv, sminqv, umaxqv, uminqv, eorqv, faddqv, fmaxnmqv,
fmaxqv, fminnmqv and fminqv
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
---
gas/testsuite/gas/aarch64/sve2p1-1-invalid.d | 4 +
gas/testsuite/gas/aarch64/sve2p1-1-invalid.l | 101 +++++++++++++++++++
gas/testsuite/gas/aarch64/sve2p1-1-invalid.s | 26 +++++
opcodes/aarch64-tbl.h | 25 +++--
4 files changed, 143 insertions(+), 13 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-1-invalid.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-1-invalid.l
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-1-invalid.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0008-BINUTILS-aarch64-Fix-the-wrong-constraint-used-fo.patch --]
[-- Type: text/x-patch; name="v1-0008-BINUTILS-aarch64-Fix-the-wrong-constraint-used-fo.patch", Size: 14173 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-1-invalid.d
new file mode 100644
index 00000000000..91066f751ac
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-1-invalid.d
@@ -0,0 +1,4 @@
+#name: Illegal test of SVE2.1 min max instructions with movprfx.
+#as: -march=armv9.4-a
+#source: sve2p1-1-invalid.s
+#warning_output: sve2p1-1-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-1-invalid.l
new file mode 100644
index 00000000000..ecece134cf8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-1-invalid.l
@@ -0,0 +1,101 @@
+.*: Assembler messages:
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.16b,p0,z0.b'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.16b,p0,z0.b'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.16b,p0,z0.b'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.16b,p0,z0.b'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.16b,p0,z0.b'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.16b,p0,z0.b'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.16b,p0,z0.b'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `faddqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `faddqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `faddqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxnmqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxnmqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxnmqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminnmqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminnmqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminnmqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `faddqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `faddqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `faddqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxnmqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxnmqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxnmqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminnmqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminnmqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminnmqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminqv v0.2d,p0,z0.d'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-1-invalid.s
new file mode 100644
index 00000000000..1808027b56e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-1-invalid.s
@@ -0,0 +1,26 @@
+ .irp op1 addqv, andqv, smaxqv, sminqv, umaxqv, uminqv, eorqv
+ movprfx z3, z5
+ \op1 v0.16b, p0, z0.b
+ movprfx z3, z5
+ \op1 v0.8h, p0, z0.h
+ movprfx z3, z5
+ \op1 v0.4s, p0, z0.s
+ movprfx z3, z5
+ \op1 v0.2d, p0, z0.d
+ .endr
+ .irp op1 addqv, andqv, smaxqv, sminqv, umaxqv, uminqv, eorqv, faddqv, fmaxnmqv, fmaxqv, fminnmqv, fminqv
+ movprfx z0.d, p0/m, z31.d
+ \op1 v0.8h, p0, z0.h
+ movprfx z0.d, p0/m, z31.d
+ \op1 v0.4s, p0, z0.s
+ movprfx z0.d, p0/m, z31.d
+ \op1 v0.2d, p0, z0.d
+ .endr
+ .irp op1 addqv, andqv, smaxqv, sminqv, umaxqv, uminqv, eorqv, faddqv, fmaxnmqv, fmaxqv, fminnmqv, fminqv
+ movprfx z0.d, p0/z, z31.d
+ \op1 v0.8h, p0, z0.h
+ movprfx z0.d, p0/z, z31.d
+ \op1 v0.4s, p0, z0.s
+ movprfx z0.d, p0/z, z31.d
+ \op1 v0.2d, p0, z0.d
+ .endr
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 8ab7c1315a1..5172515adde 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6504,19 +6504,18 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2p1_INSN ("movaz", 0xc0c60200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsd_1), OP_SVE_DD, 0, 0),
/* SVE2p1 Instructions. */
- SVE2p1_INSNC("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("smaxqv",0x040c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("sminqv",0x040e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("umaxqv",0x040d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("uminqv",0x040f2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("eorqv",0x041d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
-
- SVE2p1_INSNC("faddqv",0x6410a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("fmaxnmqv",0x6414a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("fmaxqv",0x6416a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("fminnmqv",0x6415a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
+ SVE2p1_INSN("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("smaxqv",0x040c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("sminqv",0x040e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("umaxqv",0x040d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("uminqv",0x040f2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("eorqv",0x041d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("faddqv",0x6410a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("fmaxnmqv",0x6414a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("fmaxqv",0x6416a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("fminnmqv",0x6415a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH v1 09/11] [Binutils] aarch64: Add extra tests for sve2p1 min max instructions.
2024-06-12 15:58 [PATCH v2 0/11][Binutils] aarch64: Fix the FEAT_SVE2p1 related issues srinath
` (7 preceding siblings ...)
2024-06-12 15:59 ` [PATCH v1 08/11] [BINUTILS] aarch64: Fix the wrong constraint used for sve2p1 instructions srinath
@ 2024-06-12 15:59 ` srinath
2024-06-12 15:59 ` [PATCH v1 10/11] [Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints srinath
2024-06-12 15:59 ` [PATCH v1 11/11] [Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints (regenerated files) srinath
10 siblings, 0 replies; 18+ messages in thread
From: srinath @ 2024-06-12 15:59 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 1076 bytes --]
Hi,
This patch adds some extra tests for the sve2p1 "addqv, andqv, smaxqv,
sminqv, umaxqv, uminqv, eorqv, faddqv, fmaxnmqv, fmaxqv, fminnmqv and
fminqv" instructions.
The patch also adds couple of negative testcases, sve2p1-1-bad.d testcase
without "+sve2p1" option and sve2p1-2-bad.d testcase with wrong operands
for sve2p1 instructions.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
---
gas/testsuite/gas/aarch64/sve2p1-1-bad.l | 151 ++++++++--------
gas/testsuite/gas/aarch64/sve2p1-1.d | 151 ++++++++--------
gas/testsuite/gas/aarch64/sve2p1-1.s | 152 +++++++++--------
gas/testsuite/gas/aarch64/sve2p1-3-bad.d | 3 +
gas/testsuite/gas/aarch64/sve2p1-3-bad.l | 208 +++++++++++++++++++++++
gas/testsuite/gas/aarch64/sve2p1-3-bad.s | 59 +++++++
6 files changed, 523 insertions(+), 201 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-bad.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-bad.l
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-bad.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0009-Binutils-aarch64-Add-extra-tests-for-sve2p1-min-m.patch --]
[-- Type: text/x-patch; name="v1-0009-Binutils-aarch64-Add-extra-tests-for-sve2p1-min-m.patch", Size: 32050 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
index 1b6a9683b65..24c8793a4cd 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
+++ b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
@@ -1,68 +1,85 @@
.*: Assembler messages:
-.*: Error: selected processor does not support `addqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `addqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `addqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `addqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `addqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `addqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `andqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `andqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `andqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `andqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `andqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `andqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `smaxqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `smaxqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `smaxqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `smaxqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `smaxqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `smaxqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `umaxqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `umaxqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `umaxqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `umaxqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `umaxqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `umaxqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `sminqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `sminqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `sminqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `sminqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `sminqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `sminqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `uminqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `uminqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `uminqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `uminqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `uminqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `uminqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `eorqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `eorqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `eorqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `eorqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `eorqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `eorqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `faddqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `faddqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `faddqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `faddqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `faddqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `fmaxnmqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `fmaxnmqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `fmaxnmqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `fmaxnmqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `fmaxnmqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `fmaxqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `fmaxqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `fmaxqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `fmaxqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `fmaxqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `fminnmqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `fminnmqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `fminnmqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `fminnmqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `fminnmqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `fminqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `fminqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `fminqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `fminqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `fminqv v16.4s,p7,z0.s'
+.*: selected processor does not support `addqv v0.16b,p0,z0.b'
+.*: selected processor does not support `addqv v31.16b,p0,z0.b'
+.*: selected processor does not support `addqv v0.2d,p0,z0.d'
+.*: selected processor does not support `addqv v0.16b,p7,z0.b'
+.*: selected processor does not support `addqv v0.16b,p0,z31.b'
+.*: selected processor does not support `addqv v31.2d,p7,z31.d'
+.*: selected processor does not support `addqv v10.4s,p3,z20.s'
+.*: selected processor does not support `andqv v0.16b,p0,z0.b'
+.*: selected processor does not support `andqv v31.16b,p0,z0.b'
+.*: selected processor does not support `andqv v0.2d,p0,z0.d'
+.*: selected processor does not support `andqv v0.16b,p7,z0.b'
+.*: selected processor does not support `andqv v0.16b,p0,z31.b'
+.*: selected processor does not support `andqv v31.2d,p7,z31.d'
+.*: selected processor does not support `andqv v10.4s,p3,z20.s'
+.*: selected processor does not support `smaxqv v0.16b,p0,z0.b'
+.*: selected processor does not support `smaxqv v31.16b,p0,z0.b'
+.*: selected processor does not support `smaxqv v0.2d,p0,z0.d'
+.*: selected processor does not support `smaxqv v0.16b,p7,z0.b'
+.*: selected processor does not support `smaxqv v0.16b,p0,z31.b'
+.*: selected processor does not support `smaxqv v31.2d,p7,z31.d'
+.*: selected processor does not support `smaxqv v10.4s,p3,z20.s'
+.*: selected processor does not support `umaxqv v0.16b,p0,z0.b'
+.*: selected processor does not support `umaxqv v31.16b,p0,z0.b'
+.*: selected processor does not support `umaxqv v0.2d,p0,z0.d'
+.*: selected processor does not support `umaxqv v0.16b,p7,z0.b'
+.*: selected processor does not support `umaxqv v0.16b,p0,z31.b'
+.*: selected processor does not support `umaxqv v31.2d,p7,z31.d'
+.*: selected processor does not support `umaxqv v10.4s,p3,z20.s'
+.*: selected processor does not support `sminqv v0.16b,p0,z0.b'
+.*: selected processor does not support `sminqv v31.16b,p0,z0.b'
+.*: selected processor does not support `sminqv v0.2d,p0,z0.d'
+.*: selected processor does not support `sminqv v0.16b,p7,z0.b'
+.*: selected processor does not support `sminqv v0.16b,p0,z31.b'
+.*: selected processor does not support `sminqv v31.2d,p7,z31.d'
+.*: selected processor does not support `sminqv v10.4s,p3,z20.s'
+.*: selected processor does not support `uminqv v0.16b,p0,z0.b'
+.*: selected processor does not support `uminqv v31.16b,p0,z0.b'
+.*: selected processor does not support `uminqv v0.2d,p0,z0.d'
+.*: selected processor does not support `uminqv v0.16b,p7,z0.b'
+.*: selected processor does not support `uminqv v0.16b,p0,z31.b'
+.*: selected processor does not support `uminqv v31.2d,p7,z31.d'
+.*: selected processor does not support `uminqv v10.4s,p3,z20.s'
+.*: selected processor does not support `eorqv v0.16b,p0,z0.b'
+.*: selected processor does not support `eorqv v31.16b,p0,z0.b'
+.*: selected processor does not support `eorqv v0.2d,p0,z0.d'
+.*: selected processor does not support `eorqv v0.16b,p7,z0.b'
+.*: selected processor does not support `eorqv v0.16b,p0,z31.b'
+.*: selected processor does not support `eorqv v31.2d,p7,z31.d'
+.*: selected processor does not support `eorqv v10.4s,p3,z20.s'
+.*: selected processor does not support `faddqv v0.8h,p0,z0.h'
+.*: selected processor does not support `faddqv v31.8h,p0,z0.h'
+.*: selected processor does not support `faddqv v0.2d,p0,z0.d'
+.*: selected processor does not support `faddqv v0.8h,p7,z0.h'
+.*: selected processor does not support `faddqv v0.8h,p0,z31.h'
+.*: selected processor does not support `faddqv v31.2d,p7,z31.d'
+.*: selected processor does not support `faddqv v10.4s,p3,z20.s'
+.*: selected processor does not support `fmaxnmqv v0.8h,p0,z0.h'
+.*: selected processor does not support `fmaxnmqv v31.8h,p0,z0.h'
+.*: selected processor does not support `fmaxnmqv v0.2d,p0,z0.d'
+.*: selected processor does not support `fmaxnmqv v0.8h,p7,z0.h'
+.*: selected processor does not support `fmaxnmqv v0.8h,p0,z31.h'
+.*: selected processor does not support `fmaxnmqv v31.2d,p7,z31.d'
+.*: selected processor does not support `fmaxnmqv v10.4s,p3,z20.s'
+.*: selected processor does not support `fmaxqv v0.8h,p0,z0.h'
+.*: selected processor does not support `fmaxqv v31.8h,p0,z0.h'
+.*: selected processor does not support `fmaxqv v0.2d,p0,z0.d'
+.*: selected processor does not support `fmaxqv v0.8h,p7,z0.h'
+.*: selected processor does not support `fmaxqv v0.8h,p0,z31.h'
+.*: selected processor does not support `fmaxqv v31.2d,p7,z31.d'
+.*: selected processor does not support `fmaxqv v10.4s,p3,z20.s'
+.*: selected processor does not support `fminnmqv v0.8h,p0,z0.h'
+.*: selected processor does not support `fminnmqv v31.8h,p0,z0.h'
+.*: selected processor does not support `fminnmqv v0.2d,p0,z0.d'
+.*: selected processor does not support `fminnmqv v0.8h,p7,z0.h'
+.*: selected processor does not support `fminnmqv v0.8h,p0,z31.h'
+.*: selected processor does not support `fminnmqv v31.2d,p7,z31.d'
+.*: selected processor does not support `fminnmqv v10.4s,p3,z20.s'
+.*: selected processor does not support `fminqv v0.8h,p0,z0.h'
+.*: selected processor does not support `fminqv v31.8h,p0,z0.h'
+.*: selected processor does not support `fminqv v0.2d,p0,z0.d'
+.*: selected processor does not support `fminqv v0.8h,p7,z0.h'
+.*: selected processor does not support `fminqv v0.8h,p0,z31.h'
+.*: selected processor does not support `fminqv v31.2d,p7,z31.d'
+.*: selected processor does not support `fminqv v10.4s,p3,z20.s'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d
index 8277a1386f2..1f52e3c7f84 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.d
@@ -8,70 +8,87 @@
[^:]+:
[^:]+:
-.*: 04052200 addqv v0.16b, p0, z16.b
-.*: 04452501 addqv v1.8h, p1, z8.h
-.*: 04852882 addqv v2.4s, p2, z4.s
-.*: 04c52c44 addqv v4.2d, p3, z2.d
-.*: 04c53028 addqv v8.2d, p4, z1.d
-.*: 04853c10 addqv v16.4s, p7, z0.s
-.*: 041e2200 andqv v0.16b, p0, z16.b
-.*: 045e2501 andqv v1.8h, p1, z8.h
-.*: 049e2882 andqv v2.4s, p2, z4.s
-.*: 04de2c44 andqv v4.2d, p3, z2.d
-.*: 04de3028 andqv v8.2d, p4, z1.d
-.*: 049e3c10 andqv v16.4s, p7, z0.s
-.*: 040c2200 smaxqv v0.16b, p0, z16.b
-.*: 044c2501 smaxqv v1.8h, p1, z8.h
-.*: 048c2882 smaxqv v2.4s, p2, z4.s
-.*: 04cc2c44 smaxqv v4.2d, p3, z2.d
-.*: 04cc3028 smaxqv v8.2d, p4, z1.d
-.*: 048c3c10 smaxqv v16.4s, p7, z0.s
-.*: 040d2200 umaxqv v0.16b, p0, z16.b
-.*: 044d2501 umaxqv v1.8h, p1, z8.h
-.*: 048d2882 umaxqv v2.4s, p2, z4.s
-.*: 04cd2c44 umaxqv v4.2d, p3, z2.d
-.*: 04cd3028 umaxqv v8.2d, p4, z1.d
-.*: 048d3c10 umaxqv v16.4s, p7, z0.s
-.*: 040e2200 sminqv v0.16b, p0, z16.b
-.*: 044e2501 sminqv v1.8h, p1, z8.h
-.*: 048e2882 sminqv v2.4s, p2, z4.s
-.*: 04ce2c44 sminqv v4.2d, p3, z2.d
-.*: 04ce3028 sminqv v8.2d, p4, z1.d
-.*: 048e3c10 sminqv v16.4s, p7, z0.s
-.*: 040f2200 uminqv v0.16b, p0, z16.b
-.*: 044f2501 uminqv v1.8h, p1, z8.h
-.*: 048f2882 uminqv v2.4s, p2, z4.s
-.*: 04cf2c44 uminqv v4.2d, p3, z2.d
-.*: 04cf3028 uminqv v8.2d, p4, z1.d
-.*: 048f3c10 uminqv v16.4s, p7, z0.s
-.*: 041d2200 eorqv v0.16b, p0, z16.b
-.*: 045d2501 eorqv v1.8h, p1, z8.h
-.*: 049d2882 eorqv v2.4s, p2, z4.s
-.*: 04dd2c44 eorqv v4.2d, p3, z2.d
-.*: 04dd3028 eorqv v8.2d, p4, z1.d
-.*: 049d3c10 eorqv v16.4s, p7, z0.s
-.*: 6450a501 faddqv v1.8h, p1, z8.h
-.*: 6490a882 faddqv v2.4s, p2, z4.s
-.*: 64d0ac44 faddqv v4.2d, p3, z2.d
-.*: 64d0b028 faddqv v8.2d, p4, z1.d
-.*: 6490bc10 faddqv v16.4s, p7, z0.s
-.*: 6454a501 fmaxnmqv v1.8h, p1, z8.h
-.*: 6494a882 fmaxnmqv v2.4s, p2, z4.s
-.*: 64d4ac44 fmaxnmqv v4.2d, p3, z2.d
-.*: 64d4b028 fmaxnmqv v8.2d, p4, z1.d
-.*: 6494bc10 fmaxnmqv v16.4s, p7, z0.s
-.*: 6456a501 fmaxqv v1.8h, p1, z8.h
-.*: 6496a882 fmaxqv v2.4s, p2, z4.s
-.*: 64d6ac44 fmaxqv v4.2d, p3, z2.d
-.*: 64d6b028 fmaxqv v8.2d, p4, z1.d
-.*: 6496bc10 fmaxqv v16.4s, p7, z0.s
-.*: 6455a501 fminnmqv v1.8h, p1, z8.h
-.*: 6495a882 fminnmqv v2.4s, p2, z4.s
-.*: 64d5ac44 fminnmqv v4.2d, p3, z2.d
-.*: 64d5b028 fminnmqv v8.2d, p4, z1.d
-.*: 6495bc10 fminnmqv v16.4s, p7, z0.s
-.*: 6457a501 fminqv v1.8h, p1, z8.h
-.*: 6497a882 fminqv v2.4s, p2, z4.s
-.*: 64d7ac44 fminqv v4.2d, p3, z2.d
-.*: 64d7b028 fminqv v8.2d, p4, z1.d
-.*: 6497bc10 fminqv v16.4s, p7, z0.s
+.*: 04052000 addqv v0.16b, p0, z0.b
+.*: 0405201f addqv v31.16b, p0, z0.b
+.*: 04c52000 addqv v0.2d, p0, z0.d
+.*: 04053c00 addqv v0.16b, p7, z0.b
+.*: 040523e0 addqv v0.16b, p0, z31.b
+.*: 04c53fff addqv v31.2d, p7, z31.d
+.*: 04852e8a addqv v10.4s, p3, z20.s
+.*: 041e2000 andqv v0.16b, p0, z0.b
+.*: 041e201f andqv v31.16b, p0, z0.b
+.*: 04de2000 andqv v0.2d, p0, z0.d
+.*: 041e3c00 andqv v0.16b, p7, z0.b
+.*: 041e23e0 andqv v0.16b, p0, z31.b
+.*: 04de3fff andqv v31.2d, p7, z31.d
+.*: 049e2e8a andqv v10.4s, p3, z20.s
+.*: 040c2000 smaxqv v0.16b, p0, z0.b
+.*: 040c201f smaxqv v31.16b, p0, z0.b
+.*: 04cc2000 smaxqv v0.2d, p0, z0.d
+.*: 040c3c00 smaxqv v0.16b, p7, z0.b
+.*: 040c23e0 smaxqv v0.16b, p0, z31.b
+.*: 04cc3fff smaxqv v31.2d, p7, z31.d
+.*: 048c2e8a smaxqv v10.4s, p3, z20.s
+.*: 040d2000 umaxqv v0.16b, p0, z0.b
+.*: 040d201f umaxqv v31.16b, p0, z0.b
+.*: 04cd2000 umaxqv v0.2d, p0, z0.d
+.*: 040d3c00 umaxqv v0.16b, p7, z0.b
+.*: 040d23e0 umaxqv v0.16b, p0, z31.b
+.*: 04cd3fff umaxqv v31.2d, p7, z31.d
+.*: 048d2e8a umaxqv v10.4s, p3, z20.s
+.*: 040e2000 sminqv v0.16b, p0, z0.b
+.*: 040e201f sminqv v31.16b, p0, z0.b
+.*: 04ce2000 sminqv v0.2d, p0, z0.d
+.*: 040e3c00 sminqv v0.16b, p7, z0.b
+.*: 040e23e0 sminqv v0.16b, p0, z31.b
+.*: 04ce3fff sminqv v31.2d, p7, z31.d
+.*: 048e2e8a sminqv v10.4s, p3, z20.s
+.*: 040f2000 uminqv v0.16b, p0, z0.b
+.*: 040f201f uminqv v31.16b, p0, z0.b
+.*: 04cf2000 uminqv v0.2d, p0, z0.d
+.*: 040f3c00 uminqv v0.16b, p7, z0.b
+.*: 040f23e0 uminqv v0.16b, p0, z31.b
+.*: 04cf3fff uminqv v31.2d, p7, z31.d
+.*: 048f2e8a uminqv v10.4s, p3, z20.s
+.*: 041d2000 eorqv v0.16b, p0, z0.b
+.*: 041d201f eorqv v31.16b, p0, z0.b
+.*: 04dd2000 eorqv v0.2d, p0, z0.d
+.*: 041d3c00 eorqv v0.16b, p7, z0.b
+.*: 041d23e0 eorqv v0.16b, p0, z31.b
+.*: 04dd3fff eorqv v31.2d, p7, z31.d
+.*: 049d2e8a eorqv v10.4s, p3, z20.s
+.*: 6450a000 faddqv v0.8h, p0, z0.h
+.*: 6450a01f faddqv v31.8h, p0, z0.h
+.*: 64d0a000 faddqv v0.2d, p0, z0.d
+.*: 6450bc00 faddqv v0.8h, p7, z0.h
+.*: 6450a3e0 faddqv v0.8h, p0, z31.h
+.*: 64d0bfff faddqv v31.2d, p7, z31.d
+.*: 6490ae8a faddqv v10.4s, p3, z20.s
+.*: 6454a000 fmaxnmqv v0.8h, p0, z0.h
+.*: 6454a01f fmaxnmqv v31.8h, p0, z0.h
+.*: 64d4a000 fmaxnmqv v0.2d, p0, z0.d
+.*: 6454bc00 fmaxnmqv v0.8h, p7, z0.h
+.*: 6454a3e0 fmaxnmqv v0.8h, p0, z31.h
+.*: 64d4bfff fmaxnmqv v31.2d, p7, z31.d
+.*: 6494ae8a fmaxnmqv v10.4s, p3, z20.s
+.*: 6456a000 fmaxqv v0.8h, p0, z0.h
+.*: 6456a01f fmaxqv v31.8h, p0, z0.h
+.*: 64d6a000 fmaxqv v0.2d, p0, z0.d
+.*: 6456bc00 fmaxqv v0.8h, p7, z0.h
+.*: 6456a3e0 fmaxqv v0.8h, p0, z31.h
+.*: 64d6bfff fmaxqv v31.2d, p7, z31.d
+.*: 6496ae8a fmaxqv v10.4s, p3, z20.s
+.*: 6455a000 fminnmqv v0.8h, p0, z0.h
+.*: 6455a01f fminnmqv v31.8h, p0, z0.h
+.*: 64d5a000 fminnmqv v0.2d, p0, z0.d
+.*: 6455bc00 fminnmqv v0.8h, p7, z0.h
+.*: 6455a3e0 fminnmqv v0.8h, p0, z31.h
+.*: 64d5bfff fminnmqv v31.2d, p7, z31.d
+.*: 6495ae8a fminnmqv v10.4s, p3, z20.s
+.*: 6457a000 fminqv v0.8h, p0, z0.h
+.*: 6457a01f fminqv v31.8h, p0, z0.h
+.*: 64d7a000 fminqv v0.2d, p0, z0.d
+.*: 6457bc00 fminqv v0.8h, p7, z0.h
+.*: 6457a3e0 fminqv v0.8h, p0, z31.h
+.*: 64d7bfff fminqv v31.2d, p7, z31.d
+.*: 6497ae8a fminqv v10.4s, p3, z20.s
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.s b/gas/testsuite/gas/aarch64/sve2p1-1.s
index 1e7c2ceceba..3dd35b84a45 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.s
@@ -1,77 +1,95 @@
-addqv v0.16b, p0, z16.b
-addqv v1.8h, p1, z8.h
-addqv v2.4s, p2, z4.s
-addqv v4.2d, p3, z2.d
-addqv v8.2d, p4, z1.d
-addqv v16.4s, p7, z0.s
+addqv v0.16b, p0, z0.b
+addqv v31.16b, p0, z0.b
+addqv v0.2d, p0, z0.d
+addqv v0.16b, p7, z0.b
+addqv v0.16b, p0, z31.b
+addqv v31.2d, p7, z31.d
+addqv v10.4s, p3, z20.s
-andqv v0.16b, p0, z16.b
-andqv v1.8h, p1, z8.h
-andqv v2.4s, p2, z4.s
-andqv v4.2d, p3, z2.d
-andqv v8.2d, p4, z1.d
-andqv v16.4s, p7, z0.s
+andqv v0.16b, p0, z0.b
+andqv v31.16b, p0, z0.b
+andqv v0.2d, p0, z0.d
+andqv v0.16b, p7, z0.b
+andqv v0.16b, p0, z31.b
+andqv v31.2d, p7, z31.d
+andqv v10.4s, p3, z20.s
-smaxqv v0.16b, p0, z16.b
-smaxqv v1.8h, p1, z8.h
-smaxqv v2.4s, p2, z4.s
-smaxqv v4.2d, p3, z2.d
-smaxqv v8.2d, p4, z1.d
-smaxqv v16.4s, p7, z0.s
+smaxqv v0.16b, p0, z0.b
+smaxqv v31.16b, p0, z0.b
+smaxqv v0.2d, p0, z0.d
+smaxqv v0.16b, p7, z0.b
+smaxqv v0.16b, p0, z31.b
+smaxqv v31.2d, p7, z31.d
+smaxqv v10.4s, p3, z20.s
-umaxqv v0.16b, p0, z16.b
-umaxqv v1.8h, p1, z8.h
-umaxqv v2.4s, p2, z4.s
-umaxqv v4.2d, p3, z2.d
-umaxqv v8.2d, p4, z1.d
-umaxqv v16.4s, p7, z0.s
+umaxqv v0.16b, p0, z0.b
+umaxqv v31.16b, p0, z0.b
+umaxqv v0.2d, p0, z0.d
+umaxqv v0.16b, p7, z0.b
+umaxqv v0.16b, p0, z31.b
+umaxqv v31.2d, p7, z31.d
+umaxqv v10.4s, p3, z20.s
-sminqv v0.16b, p0, z16.b
-sminqv v1.8h, p1, z8.h
-sminqv v2.4s, p2, z4.s
-sminqv v4.2d, p3, z2.d
-sminqv v8.2d, p4, z1.d
-sminqv v16.4s, p7, z0.s
+sminqv v0.16b, p0, z0.b
+sminqv v31.16b, p0, z0.b
+sminqv v0.2d, p0, z0.d
+sminqv v0.16b, p7, z0.b
+sminqv v0.16b, p0, z31.b
+sminqv v31.2d, p7, z31.d
+sminqv v10.4s, p3, z20.s
-uminqv v0.16b, p0, z16.b
-uminqv v1.8h, p1, z8.h
-uminqv v2.4s, p2, z4.s
-uminqv v4.2d, p3, z2.d
-uminqv v8.2d, p4, z1.d
-uminqv v16.4s, p7, z0.s
-eorqv v0.16b, p0, z16.b
-eorqv v1.8h, p1, z8.h
-eorqv v2.4s, p2, z4.s
-eorqv v4.2d, p3, z2.d
-eorqv v8.2d, p4, z1.d
-eorqv v16.4s, p7, z0.s
+uminqv v0.16b, p0, z0.b
+uminqv v31.16b, p0, z0.b
+uminqv v0.2d, p0, z0.d
+uminqv v0.16b, p7, z0.b
+uminqv v0.16b, p0, z31.b
+uminqv v31.2d, p7, z31.d
+uminqv v10.4s, p3, z20.s
-faddqv v1.8h, p1, z8.h
-faddqv v2.4s, p2, z4.s
-faddqv v4.2d, p3, z2.d
-faddqv v8.2d, p4, z1.d
-faddqv v16.4s, p7, z0.s
+eorqv v0.16b, p0, z0.b
+eorqv v31.16b, p0, z0.b
+eorqv v0.2d, p0, z0.d
+eorqv v0.16b, p7, z0.b
+eorqv v0.16b, p0, z31.b
+eorqv v31.2d, p7, z31.d
+eorqv v10.4s, p3, z20.s
-fmaxnmqv v1.8h, p1, z8.h
-fmaxnmqv v2.4s, p2, z4.s
-fmaxnmqv v4.2d, p3, z2.d
-fmaxnmqv v8.2d, p4, z1.d
-fmaxnmqv v16.4s, p7, z0.s
+faddqv v0.8h, p0, z0.h
+faddqv v31.8h, p0, z0.h
+faddqv v0.2d, p0, z0.d
+faddqv v0.8h, p7, z0.h
+faddqv v0.8h, p0, z31.h
+faddqv v31.2d, p7, z31.d
+faddqv v10.4s, p3, z20.s
-fmaxqv v1.8h, p1, z8.h
-fmaxqv v2.4s, p2, z4.s
-fmaxqv v4.2d, p3, z2.d
-fmaxqv v8.2d, p4, z1.d
-fmaxqv v16.4s, p7, z0.s
+fmaxnmqv v0.8h, p0, z0.h
+fmaxnmqv v31.8h, p0, z0.h
+fmaxnmqv v0.2d, p0, z0.d
+fmaxnmqv v0.8h, p7, z0.h
+fmaxnmqv v0.8h, p0, z31.h
+fmaxnmqv v31.2d, p7, z31.d
+fmaxnmqv v10.4s, p3, z20.s
-fminnmqv v1.8h, p1, z8.h
-fminnmqv v2.4s, p2, z4.s
-fminnmqv v4.2d, p3, z2.d
-fminnmqv v8.2d, p4, z1.d
-fminnmqv v16.4s, p7, z0.s
+fmaxqv v0.8h, p0, z0.h
+fmaxqv v31.8h, p0, z0.h
+fmaxqv v0.2d, p0, z0.d
+fmaxqv v0.8h, p7, z0.h
+fmaxqv v0.8h, p0, z31.h
+fmaxqv v31.2d, p7, z31.d
+fmaxqv v10.4s, p3, z20.s
-fminqv v1.8h, p1, z8.h
-fminqv v2.4s, p2, z4.s
-fminqv v4.2d, p3, z2.d
-fminqv v8.2d, p4, z1.d
-fminqv v16.4s, p7, z0.s
+fminnmqv v0.8h, p0, z0.h
+fminnmqv v31.8h, p0, z0.h
+fminnmqv v0.2d, p0, z0.d
+fminnmqv v0.8h, p7, z0.h
+fminnmqv v0.8h, p0, z31.h
+fminnmqv v31.2d, p7, z31.d
+fminnmqv v10.4s, p3, z20.s
+
+fminqv v0.8h, p0, z0.h
+fminqv v31.8h, p0, z0.h
+fminqv v0.2d, p0, z0.d
+fminqv v0.8h, p7, z0.h
+fminqv v0.8h, p0, z31.h
+fminqv v31.2d, p7, z31.d
+fminqv v10.4s, p3, z20.s
diff --git a/gas/testsuite/gas/aarch64/sve2p1-3-bad.d b/gas/testsuite/gas/aarch64/sve2p1-3-bad.d
new file mode 100644
index 00000000000..e14c382511f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3-bad.d
@@ -0,0 +1,3 @@
+#name: Test of illegal SVE2.1 min and max instruction.
+#as: -march=armv9.4-a
+#error_output: sve2p1-3-bad.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-3-bad.l b/gas/testsuite/gas/aarch64/sve2p1-3-bad.l
new file mode 100644
index 00000000000..a1fbdc6cbdf
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3-bad.l
@@ -0,0 +1,208 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `addqv v0.8h,p0,z0.b'
+.*: Info: did you mean this\?
+.*: Info: addqv v0.16b, p0, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: addqv v0.8h, p0, z0.h
+.*: Info: addqv v0.4s, p0, z0.s
+.*: Info: addqv v0.2d, p0, z0.d
+.*: Error: p0-p7 expected at operand 2 -- `addqv v31.16b,p8,z0.b'
+.*: Error: operand mismatch -- `addqv v0.2d,p7,z0.b'
+.*: Info: did you mean this\?
+.*: Info: addqv v0.16b, p7, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: addqv v0.8h, p7, z0.h
+.*: Info: addqv v0.4s, p7, z0.s
+.*: Info: addqv v0.2d, p7, z0.d
+.*: Error: invalid element size 2 and vector size combination b at operand 1 -- `addqv v0.2b,p7,z0.b'
+.*: Error: operand mismatch -- `smaxqv v0.8h,p0,z0.b'
+.*: Info: did you mean this\?
+.*: Info: smaxqv v0.16b, p0, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: smaxqv v0.8h, p0, z0.h
+.*: Info: smaxqv v0.4s, p0, z0.s
+.*: Info: smaxqv v0.2d, p0, z0.d
+.*: Error: p0-p7 expected at operand 2 -- `smaxqv v31.16b,p8,z0.b'
+.*: Error: operand mismatch -- `smaxqv v0.2d,p7,z0.b'
+.*: Info: did you mean this\?
+.*: Info: smaxqv v0.16b, p7, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: smaxqv v0.8h, p7, z0.h
+.*: Info: smaxqv v0.4s, p7, z0.s
+.*: Info: smaxqv v0.2d, p7, z0.d
+.*: Error: invalid element size 2 and vector size combination b at operand 1 -- `smaxqv v0.2b,p7,z0.b'
+.*: Error: operand mismatch -- `andqv v0.8h,p0,z0.b'
+.*: Info: did you mean this\?
+.*: Info: andqv v0.16b, p0, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: andqv v0.8h, p0, z0.h
+.*: Info: andqv v0.4s, p0, z0.s
+.*: Info: andqv v0.2d, p0, z0.d
+.*: Error: p0-p7 expected at operand 2 -- `andqv v31.16b,p8,z0.b'
+.*: Error: operand mismatch -- `andqv v0.2d,p7,z0.b'
+.*: Info: did you mean this\?
+.*: Info: andqv v0.16b, p7, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: andqv v0.8h, p7, z0.h
+.*: Info: andqv v0.4s, p7, z0.s
+.*: Info: andqv v0.2d, p7, z0.d
+.*: Error: invalid element size 2 and vector size combination b at operand 1 -- `andqv v0.2b,p7,z0.b'
+.*: Error: operand mismatch -- `umaxqv v0.8h,p0,z0.b'
+.*: Info: did you mean this\?
+.*: Info: umaxqv v0.16b, p0, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: umaxqv v0.8h, p0, z0.h
+.*: Info: umaxqv v0.4s, p0, z0.s
+.*: Info: umaxqv v0.2d, p0, z0.d
+.*: Error: p0-p7 expected at operand 2 -- `umaxqv v31.16b,p8,z0.b'
+.*: Error: operand mismatch -- `umaxqv v0.2d,p7,z0.b'
+.*: Info: did you mean this\?
+.*: Info: umaxqv v0.16b, p7, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: umaxqv v0.8h, p7, z0.h
+.*: Info: umaxqv v0.4s, p7, z0.s
+.*: Info: umaxqv v0.2d, p7, z0.d
+.*: Error: invalid element size 2 and vector size combination b at operand 1 -- `umaxqv v0.2b,p7,z0.b'
+.*: Error: operand mismatch -- `sminqv v0.8h,p0,z0.b'
+.*: Info: did you mean this\?
+.*: Info: sminqv v0.16b, p0, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: sminqv v0.8h, p0, z0.h
+.*: Info: sminqv v0.4s, p0, z0.s
+.*: Info: sminqv v0.2d, p0, z0.d
+.*: Error: p0-p7 expected at operand 2 -- `sminqv v31.16b,p8,z0.b'
+.*: Error: operand mismatch -- `sminqv v0.2d,p7,z0.b'
+.*: Info: did you mean this\?
+.*: Info: sminqv v0.16b, p7, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: sminqv v0.8h, p7, z0.h
+.*: Info: sminqv v0.4s, p7, z0.s
+.*: Info: sminqv v0.2d, p7, z0.d
+.*: Error: invalid element size 2 and vector size combination b at operand 1 -- `sminqv v0.2b,p7,z0.b'
+.*: Error: operand mismatch -- `uminqv v0.8h,p0,z0.b'
+.*: Info: did you mean this\?
+.*: Info: uminqv v0.16b, p0, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: uminqv v0.8h, p0, z0.h
+.*: Info: uminqv v0.4s, p0, z0.s
+.*: Info: uminqv v0.2d, p0, z0.d
+.*: Error: p0-p7 expected at operand 2 -- `uminqv v31.16b,p8,z0.b'
+.*: Error: operand mismatch -- `uminqv v0.2d,p7,z0.b'
+.*: Info: did you mean this\?
+.*: Info: uminqv v0.16b, p7, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: uminqv v0.8h, p7, z0.h
+.*: Info: uminqv v0.4s, p7, z0.s
+.*: Info: uminqv v0.2d, p7, z0.d
+.*: Error: invalid element size 2 and vector size combination b at operand 1 -- `uminqv v0.2b,p7,z0.b'
+.*: Error: operand mismatch -- `eorqv v0.8h,p0,z0.b'
+.*: Info: did you mean this\?
+.*: Info: eorqv v0.16b, p0, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: eorqv v0.8h, p0, z0.h
+.*: Info: eorqv v0.4s, p0, z0.s
+.*: Info: eorqv v0.2d, p0, z0.d
+.*: Error: p0-p7 expected at operand 2 -- `eorqv v31.16b,p8,z0.b'
+.*: Error: operand mismatch -- `eorqv v0.2d,p7,z0.b'
+.*: Info: did you mean this\?
+.*: Info: eorqv v0.16b, p7, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: eorqv v0.8h, p7, z0.h
+.*: Info: eorqv v0.4s, p7, z0.s
+.*: Info: eorqv v0.2d, p7, z0.d
+.*: Error: invalid element size 2 and vector size combination b at operand 1 -- `eorqv v0.2b,p7,z0.b'
+.*: Error: operand mismatch -- `faddqv v0.8h,p0,z0.b'
+.*: Info: did you mean this\?
+.*: Info: faddqv v0.8h, p0, z0.h
+.*: Info: other valid variant\(s\):
+.*: Info: faddqv v0.4s, p0, z0.s
+.*: Info: faddqv v0.2d, p0, z0.d
+.*: Error: operand mismatch -- `faddqv v31.16b,p8,z0.b'
+.*: Info: did you mean this\?
+.*: Info: faddqv v31.8h, p8, z0.h
+.*: Info: other valid variant\(s\):
+.*: Info: faddqv v31.4s, p8, z0.s
+.*: Info: faddqv v31.2d, p8, z0.d
+.*: Error: operand mismatch -- `faddqv v0.2d,p7,z0.b'
+.*: Info: did you mean this\?
+.*: Info: faddqv v0.2d, p7, z0.d
+.*: Info: other valid variant\(s\):
+.*: Info: faddqv v0.8h, p7, z0.h
+.*: Info: faddqv v0.4s, p7, z0.s
+.*: Error: invalid element size 2 and vector size combination b at operand 1 -- `faddqv v0.2b,p7,z0.b'
+.*: Error: operand mismatch -- `fmaxnmqv v0.8h,p0,z0.b'
+.*: Info: did you mean this\?
+.*: Info: fmaxnmqv v0.8h, p0, z0.h
+.*: Info: other valid variant\(s\):
+.*: Info: fmaxnmqv v0.4s, p0, z0.s
+.*: Info: fmaxnmqv v0.2d, p0, z0.d
+.*: Error: operand mismatch -- `fmaxnmqv v31.16b,p8,z0.b'
+.*: Info: did you mean this\?
+.*: Info: fmaxnmqv v31.8h, p8, z0.h
+.*: Info: other valid variant\(s\):
+.*: Info: fmaxnmqv v31.4s, p8, z0.s
+.*: Info: fmaxnmqv v31.2d, p8, z0.d
+.*: Error: operand mismatch -- `fmaxnmqv v0.2d,p7,z0.b'
+.*: Info: did you mean this\?
+.*: Info: fmaxnmqv v0.2d, p7, z0.d
+.*: Info: other valid variant\(s\):
+.*: Info: fmaxnmqv v0.8h, p7, z0.h
+.*: Info: fmaxnmqv v0.4s, p7, z0.s
+.*: Error: invalid element size 2 and vector size combination b at operand 1 -- `fmaxnmqv v0.2b,p7,z0.b'
+.*: Error: operand mismatch -- `fmaxqv v0.8h,p0,z0.b'
+.*: Info: did you mean this\?
+.*: Info: fmaxqv v0.8h, p0, z0.h
+.*: Info: other valid variant\(s\):
+.*: Info: fmaxqv v0.4s, p0, z0.s
+.*: Info: fmaxqv v0.2d, p0, z0.d
+.*: Error: operand mismatch -- `fmaxqv v31.16b,p8,z0.b'
+.*: Info: did you mean this\?
+.*: Info: fmaxqv v31.8h, p8, z0.h
+.*: Info: other valid variant\(s\):
+.*: Info: fmaxqv v31.4s, p8, z0.s
+.*: Info: fmaxqv v31.2d, p8, z0.d
+.*: Error: operand mismatch -- `fmaxqv v0.2d,p7,z0.b'
+.*: Info: did you mean this\?
+.*: Info: fmaxqv v0.2d, p7, z0.d
+.*: Info: other valid variant\(s\):
+.*: Info: fmaxqv v0.8h, p7, z0.h
+.*: Info: fmaxqv v0.4s, p7, z0.s
+.*: Error: invalid element size 2 and vector size combination b at operand 1 -- `fmaxqv v0.2b,p7,z0.b'
+.*: Error: operand mismatch -- `fminnmqv v0.8h,p0,z0.b'
+.*: Info: did you mean this\?
+.*: Info: fminnmqv v0.8h, p0, z0.h
+.*: Info: other valid variant\(s\):
+.*: Info: fminnmqv v0.4s, p0, z0.s
+.*: Info: fminnmqv v0.2d, p0, z0.d
+.*: Error: operand mismatch -- `fminnmqv v31.16b,p8,z0.b'
+.*: Info: did you mean this\?
+.*: Info: fminnmqv v31.8h, p8, z0.h
+.*: Info: other valid variant\(s\):
+.*: Info: fminnmqv v31.4s, p8, z0.s
+.*: Info: fminnmqv v31.2d, p8, z0.d
+.*: Error: operand mismatch -- `fminnmqv v0.2d,p7,z0.b'
+.*: Info: did you mean this\?
+.*: Info: fminnmqv v0.2d, p7, z0.d
+.*: Info: other valid variant\(s\):
+.*: Info: fminnmqv v0.8h, p7, z0.h
+.*: Info: fminnmqv v0.4s, p7, z0.s
+.*: Error: invalid element size 2 and vector size combination b at operand 1 -- `fminnmqv v0.2b,p7,z0.b'
+.*: Error: operand mismatch -- `fminqv v0.8h,p0,z0.b'
+.*: Info: did you mean this\?
+.*: Info: fminqv v0.8h, p0, z0.h
+.*: Info: other valid variant\(s\):
+.*: Info: fminqv v0.4s, p0, z0.s
+.*: Info: fminqv v0.2d, p0, z0.d
+.*: Error: operand mismatch -- `fminqv v31.16b,p8,z0.b'
+.*: Info: did you mean this\?
+.*: Info: fminqv v31.8h, p8, z0.h
+.*: Info: other valid variant\(s\):
+.*: Info: fminqv v31.4s, p8, z0.s
+.*: Info: fminqv v31.2d, p8, z0.d
+.*: Error: operand mismatch -- `fminqv v0.2d,p7,z0.b'
+.*: Info: did you mean this\?
+.*: Info: fminqv v0.2d, p7, z0.d
+.*: Info: other valid variant\(s\):
+.*: Info: fminqv v0.8h, p7, z0.h
+.*: Info: fminqv v0.4s, p7, z0.s
+.*: Error: invalid element size 2 and vector size combination b at operand 1 -- `fminqv v0.2b,p7,z0.b'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-3-bad.s b/gas/testsuite/gas/aarch64/sve2p1-3-bad.s
new file mode 100644
index 00000000000..5e56786bad1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3-bad.s
@@ -0,0 +1,59 @@
+addqv v0.8h, p0, z0.b
+addqv v31.16b, p8, z0.b
+addqv v0.2d, p7, z0.b
+addqv v0.2b, p7, z0.b
+
+smaxqv v0.8h, p0, z0.b
+smaxqv v31.16b, p8, z0.b
+smaxqv v0.2d, p7, z0.b
+smaxqv v0.2b, p7, z0.b
+
+andqv v0.8h, p0, z0.b
+andqv v31.16b, p8, z0.b
+andqv v0.2d, p7, z0.b
+andqv v0.2b, p7, z0.b
+
+umaxqv v0.8h, p0, z0.b
+umaxqv v31.16b, p8, z0.b
+umaxqv v0.2d, p7, z0.b
+umaxqv v0.2b, p7, z0.b
+
+sminqv v0.8h, p0, z0.b
+sminqv v31.16b, p8, z0.b
+sminqv v0.2d, p7, z0.b
+sminqv v0.2b, p7, z0.b
+
+uminqv v0.8h, p0, z0.b
+uminqv v31.16b, p8, z0.b
+uminqv v0.2d, p7, z0.b
+uminqv v0.2b, p7, z0.b
+
+eorqv v0.8h, p0, z0.b
+eorqv v31.16b, p8, z0.b
+eorqv v0.2d, p7, z0.b
+eorqv v0.2b, p7, z0.b
+
+faddqv v0.8h, p0, z0.b
+faddqv v31.16b, p8, z0.b
+faddqv v0.2d, p7, z0.b
+faddqv v0.2b, p7, z0.b
+
+fmaxnmqv v0.8h, p0, z0.b
+fmaxnmqv v31.16b, p8, z0.b
+fmaxnmqv v0.2d, p7, z0.b
+fmaxnmqv v0.2b, p7, z0.b
+
+fmaxqv v0.8h, p0, z0.b
+fmaxqv v31.16b, p8, z0.b
+fmaxqv v0.2d, p7, z0.b
+fmaxqv v0.2b, p7, z0.b
+
+fminnmqv v0.8h, p0, z0.b
+fminnmqv v31.16b, p8, z0.b
+fminnmqv v0.2d, p7, z0.b
+fminnmqv v0.2b, p7, z0.b
+
+fminqv v0.8h, p0, z0.b
+fminqv v31.16b, p8, z0.b
+fminqv v0.2d, p7, z0.b
+fminqv v0.2b, p7, z0.b
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH v1 10/11] [Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints.
2024-06-12 15:58 [PATCH v2 0/11][Binutils] aarch64: Fix the FEAT_SVE2p1 related issues srinath
` (8 preceding siblings ...)
2024-06-12 15:59 ` [PATCH v1 09/11] [Binutils] aarch64: Add extra tests for sve2p1 min max instructions srinath
@ 2024-06-12 15:59 ` srinath
2024-06-13 15:44 ` Richard Earnshaw (lists)
2024-06-12 15:59 ` [PATCH v1 11/11] [Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints (regenerated files) srinath
10 siblings, 1 reply; 18+ messages in thread
From: srinath @ 2024-06-12 15:59 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 1114 bytes --]
Hi,
This patch adds missing contraints to FEAT_B16B16 sve2 instructions
bfclamp, bfmla and bfmls and add negative tests for all the bfloat
instructions.
Regression tested for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
---
gas/testsuite/gas/aarch64/bfloat16-1.d | 6 +
gas/testsuite/gas/aarch64/bfloat16-1.s | 7 +-
.../gas/aarch64/bfloat16-2-invalid.d | 4 +
.../gas/aarch64/bfloat16-2-invalid.l | 265 ++++++++++++++++++
.../gas/aarch64/bfloat16-2-invalid.s | 147 ++++++++++
gas/testsuite/gas/aarch64/bfloat16-bad.l | 3 +
gas/testsuite/gas/aarch64/bfloat16-invalid.d | 2 +-
gas/testsuite/gas/aarch64/bfloat16-invalid.l | 17 +-
gas/testsuite/gas/aarch64/bfloat16-invalid.s | 9 +-
opcodes/aarch64-tbl.h | 46 +--
10 files changed, 468 insertions(+), 38 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.d
create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0010-Binutils-aarch64-Fix-FEAT_B16B16-sve2-instruction.patch --]
[-- Type: text/x-patch; name="v1-0010-Binutils-aarch64-Fix-FEAT_B16B16-sve2-instruction.patch", Size: 29691 bytes --]
diff --git a/gas/testsuite/gas/aarch64/bfloat16-1.d b/gas/testsuite/gas/aarch64/bfloat16-1.d
index 4f1df804d64..51f7e6cab20 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-1.d
+++ b/gas/testsuite/gas/aarch64/bfloat16-1.d
@@ -104,3 +104,9 @@
.*: 65020604 bfsub z4.h, z16.h, z2.h
.*: 65010688 bfsub z8.h, z20.h, z1.h
.*: 65000710 bfsub z16.h, z24.h, z0.h
+.*: 0420bca3 movprfx z3, z5
+.*: 64302483 bfclamp z3.h, z4.h, z16.h
+.*: 0420bca3 movprfx z3, z5
+.*: 647e0a03 bfmla z3.h, z16.h, z6.h\[7\]
+.*: 0420bca3 movprfx z3, z5
+.*: 647e0e03 bfmls z3.h, z16.h, z6.h\[7\]
diff --git a/gas/testsuite/gas/aarch64/bfloat16-1.s b/gas/testsuite/gas/aarch64/bfloat16-1.s
index b8969139145..be8fee9fcc8 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-1.s
+++ b/gas/testsuite/gas/aarch64/bfloat16-1.s
@@ -110,4 +110,9 @@ bfsub z4.h, z16.h, z2.h
bfsub z8.h, z20.h, z1.h
bfsub z16.h, z24.h, z0.h
-
+movprfx z3, z5
+bfclamp z3.h, z4.h, z16.h
+movprfx z3, z5
+bfmla z3.h, z16.h, z6.h[7]
+movprfx z3, z5
+bfmls z3.h, z16.h, z6.h[7]
diff --git a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.d b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.d
new file mode 100644
index 00000000000..1cd27454d42
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.d
@@ -0,0 +1,4 @@
+#name: Test Bfloat16 instructions with wrong operand combinations
+#as: -march=armv9.4-a+b16b16
+#source: bfloat16-2-invalid.s
+#error_output: bfloat16-2-invalid.l
diff --git a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
new file mode 100644
index 00000000000..5da96c72ae5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
@@ -0,0 +1,265 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `bfadd z0.s,p0/m,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfadd z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfadd z0.h,p0/z,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfadd z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfadd z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand 3 must be the same register as operand 1 -- `bfadd z31.h,p0/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfadd z0.h,p0/z,z0.s,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfadd z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfadd z0.h,p0/z,z0.h,z16.d'
+.*: Info: did you mean this\?
+.*: Info: bfadd z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfadd z31.d,p7/m,z31.d,z31.d'
+.*: Info: did you mean this\?
+.*: Info: bfadd z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfmax z0.s,p0/m,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmax z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmax z0.h,p0/z,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmax z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfmax z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmax z31.h,p0/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfmax z0.h,p0/z,z0.s,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmax z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmax z0.h,p0/z,z0.h,z16.d'
+.*: Info: did you mean this\?
+.*: Info: bfmax z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmax z31.d,p7/m,z31.d,z31.d'
+.*: Info: did you mean this\?
+.*: Info: bfmax z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfmaxnm z0.s,p0/m,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmaxnm z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmaxnm z0.h,p0/z,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmaxnm z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfmaxnm z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmaxnm z31.h,p0/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfmaxnm z0.h,p0/z,z0.s,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmaxnm z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmaxnm z0.h,p0/z,z0.h,z16.d'
+.*: Info: did you mean this\?
+.*: Info: bfmaxnm z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmaxnm z31.d,p7/m,z31.d,z31.d'
+.*: Info: did you mean this\?
+.*: Info: bfmaxnm z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfmin z0.s,p0/m,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmin z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmin z0.h,p0/z,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmin z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfmin z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmin z31.h,p0/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfmin z0.h,p0/z,z0.s,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmin z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmin z0.h,p0/z,z0.h,z16.d'
+.*: Info: did you mean this\?
+.*: Info: bfmin z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmin z31.d,p7/m,z31.d,z31.d'
+.*: Info: did you mean this\?
+.*: Info: bfmin z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfminnm z0.s,p0/m,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfminnm z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfminnm z0.h,p0/z,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfminnm z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfminnm z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand 3 must be the same register as operand 1 -- `bfminnm z31.h,p0/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfminnm z0.h,p0/z,z0.s,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfminnm z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfminnm z0.h,p0/z,z0.h,z16.d'
+.*: Info: did you mean this\?
+.*: Info: bfminnm z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfminnm z31.d,p7/m,z31.d,z31.d'
+.*: Info: did you mean this\?
+.*: Info: bfminnm z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfmla z0.s,p0/m,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmla z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmla z0.h,p0/z,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmla z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfmla z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfmla z0.h,p0/z,z0.s,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmla z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmla z0.h,p0/z,z0.h,z16.d'
+.*: Info: did you mean this\?
+.*: Info: bfmla z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmla z31.d,p7/m,z31.d,z31.d'
+.*: Info: did you mean this\?
+.*: Info: bfmla z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfmls z0.s,p0/m,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmls z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmls z0.h,p0/z,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmls z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfmls z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfmls z0.h,p0/z,z0.s,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmls z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmls z0.h,p0/z,z0.h,z16.d'
+.*: Info: did you mean this\?
+.*: Info: bfmls z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmls z31.d,p7/m,z31.d,z31.d'
+.*: Info: did you mean this\?
+.*: Info: bfmls z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfmul z0.s,p0/m,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmul z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmul z0.h,p0/z,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmul z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfmul z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmul z31.h,p0/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfmul z0.h,p0/z,z0.s,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfmul z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmul z0.h,p0/z,z0.h,z16.d'
+.*: Info: did you mean this\?
+.*: Info: bfmul z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmul z31.d,p7/m,z31.d,z31.d'
+.*: Info: did you mean this\?
+.*: Info: bfmul z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfsub z0.s,p0/m,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfsub z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfsub z0.h,p0/z,z0.h,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfsub z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfsub z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand 3 must be the same register as operand 1 -- `bfsub z31.h,p0/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfsub z0.h,p0/z,z0.s,z16.h'
+.*: Info: did you mean this\?
+.*: Info: bfsub z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfsub z0.h,p0/z,z0.h,z16.d'
+.*: Info: did you mean this\?
+.*: Info: bfsub z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfsub z31.d,p7/m,z31.d,z31.d'
+.*: Info: did you mean this\?
+.*: Info: bfsub z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfadd z0.b,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfadd z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfadd z0.s,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfadd z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfadd z0.h,z0.d,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfadd z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfadd z0.h,z0.h,z0.b'
+.*: Info: did you mean this\?
+.*: Info: bfadd z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfadd z31.b,z31.s,z31.d'
+.*: Info: did you mean this\?
+.*: Info: bfadd z31.h, z31.h, z31.h
+.*: Error: expected an SVE vector register at operand 1 -- `bfadd {z0.h},z0.h,z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `bfadd {z0.h-z0.h},z0.h'
+.*: Error: comma expected between operands at operand 3 -- `bfadd z0.h,z0.h'
+.*: Error: operand mismatch -- `bfclamp z0.b,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfclamp z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfclamp z0.s,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfclamp z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfclamp z0.h,z0.d,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfclamp z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfclamp z0.h,z0.h,z0.b'
+.*: Info: did you mean this\?
+.*: Info: bfclamp z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfclamp z31.b,z31.s,z31.d'
+.*: Info: did you mean this\?
+.*: Info: bfclamp z31.h, z31.h, z31.h
+.*: Error: expected an SVE vector register at operand 1 -- `bfclamp {z0.h},z0.h,z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `bfclamp {z0.h-z0.h},z0.h'
+.*: Error: comma expected between operands at operand 3 -- `bfclamp z0.h,z0.h'
+.*: Error: operand mismatch -- `bfmla z0.b,z0.h,z0.h\[0\]'
+.*: Info: did you mean this\?
+.*: Info: bfmla z0.h, z0.h, z0.h\[0\]
+.*: Error: operand mismatch -- `bfmla z0.s,z0.h,z0.h\[6\]'
+.*: Info: did you mean this\?
+.*: Info: bfmla z0.h, z0.h, z0.h\[6\]
+.*: Error: operand mismatch -- `bfmla z0.h,z0.d,z0.h\[8\]'
+.*: Info: did you mean this\?
+.*: Info: bfmla z0.h, z0.h, z0.h\[8\]
+.*: Error: operand mismatch -- `bfmla z0.h,z0.h,z0.b\[2\]'
+.*: Info: did you mean this\?
+.*: Info: bfmla z0.h, z0.h, z0.h\[2\]
+.*: Error: operand mismatch -- `bfmla z31.b,z31.s,z31.d\[8\]'
+.*: Info: did you mean this\?
+.*: Info: bfmla z31.h, z31.h, z31.h\[8\]
+.*: Error: expected an SVE vector register at operand 1 -- `bfmla {z0.h},z0.h,z0.h\[1\]'
+.*: Error: expected an SVE vector register at operand 1 -- `bfmla {z0.h-z0.h},z0.h\[2\]'
+.*: Error: expected an SVE predicate register at operand 2 -- `bfmla z0.h,z0.h\[3\]'
+.*: Error: operand mismatch -- `bfmls z0.b,z0.h,z0.h\[0\]'
+.*: Info: did you mean this\?
+.*: Info: bfmls z0.h, z0.h, z0.h\[0\]
+.*: Error: operand mismatch -- `bfmls z0.s,z0.h,z0.h\[6\]'
+.*: Info: did you mean this\?
+.*: Info: bfmls z0.h, z0.h, z0.h\[6\]
+.*: Error: operand mismatch -- `bfmls z0.h,z0.d,z0.h\[8\]'
+.*: Info: did you mean this\?
+.*: Info: bfmls z0.h, z0.h, z0.h\[8\]
+.*: Error: operand mismatch -- `bfmls z0.h,z0.h,z0.b\[2\]'
+.*: Info: did you mean this\?
+.*: Info: bfmls z0.h, z0.h, z0.h\[2\]
+.*: Error: operand mismatch -- `bfmls z31.b,z31.s,z31.d\[8\]'
+.*: Info: did you mean this\?
+.*: Info: bfmls z31.h, z31.h, z31.h\[8\]
+.*: Error: expected an SVE vector register at operand 1 -- `bfmls {z0.h},z0.h,z0.h\[1\]'
+.*: Error: expected an SVE vector register at operand 1 -- `bfmls {z0.h-z0.h},z0.h\[2\]'
+.*: Error: expected an SVE predicate register at operand 2 -- `bfmls z0.h,z0.h\[3\]'
+.*: Error: operand mismatch -- `bfmul z0.b,z0.h,z0.h\[0\]'
+.*: Info: did you mean this\?
+.*: Info: bfmul z0.h, z0.h, z0.h\[0\]
+.*: Error: operand mismatch -- `bfmul z0.s,z0.h,z0.h\[6\]'
+.*: Info: did you mean this\?
+.*: Info: bfmul z0.h, z0.h, z0.h\[6\]
+.*: Error: operand mismatch -- `bfmul z0.h,z0.d,z0.h\[8\]'
+.*: Info: did you mean this\?
+.*: Info: bfmul z0.h, z0.h, z0.h\[8\]
+.*: Error: operand mismatch -- `bfmul z0.h,z0.h,z0.b\[2\]'
+.*: Info: did you mean this\?
+.*: Info: bfmul z0.h, z0.h, z0.h\[2\]
+.*: Error: operand mismatch -- `bfmul z31.b,z31.s,z31.d\[8\]'
+.*: Info: did you mean this\?
+.*: Info: bfmul z31.h, z31.h, z31.h\[8\]
+.*: Error: expected an SVE vector register at operand 1 -- `bfmul {z0.h},z0.h,z0.h\[1\]'
+.*: Error: expected an SVE vector register at operand 1 -- `bfmul {z0.h-z0.h},z0.h\[2\]'
+.*: Error: expected an SVE predicate register at operand 2 -- `bfmul z0.h,z0.h\[3\]'
+.*: Error: operand mismatch -- `bfsub z0.b,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfsub z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfsub z0.s,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfsub z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfsub z0.h,z0.d,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfsub z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfsub z0.h,z0.h,z0.b'
+.*: Info: did you mean this\?
+.*: Info: bfsub z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfsub z31.b,z31.s,z31.d'
+.*: Info: did you mean this\?
+.*: Info: bfsub z31.h, z31.h, z31.h
+.*: Error: expected an SVE vector register at operand 1 -- `bfsub {z0.h},z0.h,z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `bfsub {z0.h-z0.h},z0.h'
+.*: Error: comma expected between operands at operand 3 -- `bfsub z0.h,z0.h'
+.*: Warning: output register of preceding `movprfx' expected as output at operand 1 -- `bfclamp z1.h,z3.h,z16.h'
+.*: Warning: output register of preceding `movprfx' not used in current instruction at operand 1 -- `bfmla z10.h,z16.h,z3.h\[7\]'
+.*: Warning: output register of preceding `movprfx' expected as output at operand 1 -- `bfmls z1.h,z3.h,z3.h\[7\]'
+.*: Warning: instruction opens new dependency sequence without ending previous one -- `movprfx z4,z5'
+.*: Warning: output register of preceding `movprfx' expected as output at operand 1 -- `bfclamp z2.h,z3.h,z4.h'
diff --git a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.s b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.s
new file mode 100644
index 00000000000..d690f121bdf
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.s
@@ -0,0 +1,147 @@
+bfadd z0.s, p0/m, z0.h, z16.h
+bfadd z0.h, p0/z, z0.h, z16.h
+bfadd z0.h, p8/m, z0.h, z16.h
+bfadd z31.h, p0/m, z0.h, z16.h
+bfadd z0.h, p0/z, z0.s, z16.h
+bfadd z0.h, p0/z, z0.h, z16.d
+bfadd z31.d, p7/m, z31.d, z31.d
+
+bfmax z0.s, p0/m, z0.h, z16.h
+bfmax z0.h, p0/z, z0.h, z16.h
+bfmax z0.h, p8/m, z0.h, z16.h
+bfmax z31.h, p0/m, z0.h, z16.h
+bfmax z0.h, p0/z, z0.s, z16.h
+bfmax z0.h, p0/z, z0.h, z16.d
+bfmax z31.d, p7/m, z31.d, z31.d
+
+bfmaxnm z0.s, p0/m, z0.h, z16.h
+bfmaxnm z0.h, p0/z, z0.h, z16.h
+bfmaxnm z0.h, p8/m, z0.h, z16.h
+bfmaxnm z31.h, p0/m, z0.h, z16.h
+bfmaxnm z0.h, p0/z, z0.s, z16.h
+bfmaxnm z0.h, p0/z, z0.h, z16.d
+bfmaxnm z31.d, p7/m, z31.d, z31.d
+
+bfmin z0.s, p0/m, z0.h, z16.h
+bfmin z0.h, p0/z, z0.h, z16.h
+bfmin z0.h, p8/m, z0.h, z16.h
+bfmin z31.h, p0/m, z0.h, z16.h
+bfmin z0.h, p0/z, z0.s, z16.h
+bfmin z0.h, p0/z, z0.h, z16.d
+bfmin z31.d, p7/m, z31.d, z31.d
+
+bfminnm z0.s, p0/m, z0.h, z16.h
+bfminnm z0.h, p0/z, z0.h, z16.h
+bfminnm z0.h, p8/m, z0.h, z16.h
+bfminnm z31.h, p0/m, z0.h, z16.h
+bfminnm z0.h, p0/z, z0.s, z16.h
+bfminnm z0.h, p0/z, z0.h, z16.d
+bfminnm z31.d, p7/m, z31.d, z31.d
+
+bfmla z0.s, p0/m, z0.h, z16.h
+bfmla z0.h, p0/z, z0.h, z16.h
+bfmla z0.h, p8/m, z0.h, z16.h
+bfmla z31.h, p0/m, z0.h, z16.h
+bfmla z0.h, p0/z, z0.s, z16.h
+bfmla z0.h, p0/z, z0.h, z16.d
+bfmla z31.d, p7/m, z31.d, z31.d
+
+bfmls z0.s, p0/m, z0.h, z16.h
+bfmls z0.h, p0/z, z0.h, z16.h
+bfmls z0.h, p8/m, z0.h, z16.h
+bfmls z31.h, p0/m, z0.h, z16.h
+bfmls z0.h, p0/z, z0.s, z16.h
+bfmls z0.h, p0/z, z0.h, z16.d
+bfmls z31.d, p7/m, z31.d, z31.d
+
+bfmul z0.s, p0/m, z0.h, z16.h
+bfmul z0.h, p0/z, z0.h, z16.h
+bfmul z0.h, p8/m, z0.h, z16.h
+bfmul z31.h, p0/m, z0.h, z16.h
+bfmul z0.h, p0/z, z0.s, z16.h
+bfmul z0.h, p0/z, z0.h, z16.d
+bfmul z31.d, p7/m, z31.d, z31.d
+
+bfsub z0.s, p0/m, z0.h, z16.h
+bfsub z0.h, p0/z, z0.h, z16.h
+bfsub z0.h, p8/m, z0.h, z16.h
+bfsub z31.h, p0/m, z0.h, z16.h
+bfsub z0.h, p0/z, z0.s, z16.h
+bfsub z0.h, p0/z, z0.h, z16.d
+bfsub z31.d, p7/m, z31.d, z31.d
+
+bfadd z0.b, z0.h, z0.h
+bfadd z31.h, z0.h, z0.h
+bfadd z0.s, z0.h, z0.h
+bfadd z0.h, z0.d, z0.h
+bfadd z0.h, z0.h, z0.b
+bfadd z31.b, z31.s, z31.d
+bfadd {z0.h}, z0.h, z0.h
+bfadd {z0.h - z0.h}, z0.h
+bfadd z0.h, z0.h
+
+bfclamp z0.b, z0.h, z0.h
+bfclamp z31.h, z0.h, z0.h
+bfclamp z0.s, z0.h, z0.h
+bfclamp z0.h, z0.d, z0.h
+bfclamp z0.h, z0.h, z0.b
+bfclamp z31.b, z31.s, z31.d
+bfclamp {z0.h}, z0.h, z0.h
+bfclamp {z0.h - z0.h}, z0.h
+bfclamp z0.h, z0.h
+
+bfmla z0.b, z0.h, z0.h[0]
+bfmla z31.h, z0.h, z0.h[3]
+bfmla z0.s, z0.h, z0.h[6]
+bfmla z0.h, z0.d, z0.h[8]
+bfmla z0.h, z0.h, z0.b[2]
+bfmla z31.b, z31.s, z31.d[8]
+bfmla {z0.h}, z0.h, z0.h[1]
+bfmla {z0.h - z0.h}, z0.h[2]
+bfmla z0.h, z0.h[3]
+
+bfmls z0.b, z0.h, z0.h[0]
+bfmls z31.h, z0.h, z0.h[3]
+bfmls z0.s, z0.h, z0.h[6]
+bfmls z0.h, z0.d, z0.h[8]
+bfmls z0.h, z0.h, z0.b[2]
+bfmls z31.b, z31.s, z31.d[8]
+bfmls {z0.h}, z0.h, z0.h[1]
+bfmls {z0.h - z0.h}, z0.h[2]
+bfmls z0.h, z0.h[3]
+
+bfmul z0.b, z0.h, z0.h[0]
+bfmul z31.h, z0.h, z0.h[3]
+bfmul z0.s, z0.h, z0.h[6]
+bfmul z0.h, z0.d, z0.h[8]
+bfmul z0.h, z0.h, z0.b[2]
+bfmul z31.b, z31.s, z31.d[8]
+bfmul {z0.h}, z0.h, z0.h[1]
+bfmul {z0.h - z0.h}, z0.h[2]
+bfmul z0.h, z0.h[3]
+
+bfsub z0.b, z0.h, z0.h
+bfsub z31.h, z0.h, z0.h
+bfsub z0.s, z0.h, z0.h
+bfsub z0.h, z0.d, z0.h
+bfsub z0.h, z0.h, z0.b
+bfsub z31.b, z31.s, z31.d
+bfsub {z0.h}, z0.h, z0.h
+bfsub {z0.h - z0.h}, z0.h
+bfsub z0.h, z0.h
+
+bfmla z0.h, p0/m, z4.h, z16.h
+movprfx z3, z5
+bfclamp z1.h, z3.h, z16.h
+
+movprfx z3, z5
+bfmla z10.h, z16.h, z3.h[7]
+
+movprfx z3, z5
+bfmls z1.h, z3.h, z3.h[7]
+
+movprfx z2, z3
+movprfx z4, z5
+bfclamp z2.h, z3.h, z4.h
+bfmla z4.h, z5.h, z6.h[7]
+bfmls z3.h, z1.h, z4.h[7]
diff --git a/gas/testsuite/gas/aarch64/bfloat16-bad.l b/gas/testsuite/gas/aarch64/bfloat16-bad.l
index 1519a2921f3..d4098bf7e8d 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-bad.l
+++ b/gas/testsuite/gas/aarch64/bfloat16-bad.l
@@ -95,3 +95,6 @@
.*: Error: selected processor does not support `bfsub z4.h,z16.h,z2.h'
.*: Error: selected processor does not support `bfsub z8.h,z20.h,z1.h'
.*: Error: selected processor does not support `bfsub z16.h,z24.h,z0.h'
+.*: Error: selected processor does not support `bfclamp z3.h,z4.h,z16.h'
+.*: Error: selected processor does not support `bfmla z3.h,z16.h,z6.h\[7\]'
+.*: Error: selected processor does not support `bfmls z3.h,z16.h,z6.h\[7\]'
diff --git a/gas/testsuite/gas/aarch64/bfloat16-invalid.d b/gas/testsuite/gas/aarch64/bfloat16-invalid.d
index 8f24dc62083..02e3e8d8e3d 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-invalid.d
+++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.d
@@ -1,4 +1,4 @@
-#name: Test Bfloat16 instructions with wrong operand combinations
+#name: Negative test with missing +b16b16 bfloat16 flag.
#as: -march=armv9.4-a
#source: bfloat16-invalid.s
#error_output: bfloat16-invalid.l
diff --git a/gas/testsuite/gas/aarch64/bfloat16-invalid.l b/gas/testsuite/gas/aarch64/bfloat16-invalid.l
index 0b1354a899e..87e5125e19a 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-invalid.l
+++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.l
@@ -1,8 +1,11 @@
.*: Assembler messages:
-[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfadd .*
-[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmax .*
-[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmaxnm .*
-[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmin .*
-[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfminnm .*
-[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmul .*
-[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfsub .*
+.*: Error: operand 3 must be the same register as operand 1 -- `bfadd .*
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmax .*
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmaxnm .*
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmin .*
+.*: Error: operand 3 must be the same register as operand 1 -- `bfminnm .*
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmul .*
+.*: Error: operand 3 must be the same register as operand 1 -- `bfsub .*
+.*: Error: selected processor does not support `bfclamp z3.h,z4.h,z16.h'
+.*: Error: selected processor does not support `bfmla z3.h,z16.h,z6.h\[7\]'
+.*: Error: selected processor does not support `bfmls z3.h,z16.h,z6.h\[7\]'
diff --git a/gas/testsuite/gas/aarch64/bfloat16-invalid.s b/gas/testsuite/gas/aarch64/bfloat16-invalid.s
index a5bdfc81a91..aa66fe6f4ee 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-invalid.s
+++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.s
@@ -1,13 +1,10 @@
bfadd z0.h, p0/m, z1.h, z0.h
-
bfmax z0.h, p0/m, z1.h, z0.h
-
bfmaxnm z0.h, p0/m, z1.h, z0.h
-
bfmin z0.h, p0/m, z1.h, z0.h
-
bfminnm z0.h, p0/m, z1.h, z0.h
-
bfmul z0.h, p0/m, z1.h, z0.h
-
bfsub z0.h, p0/m, z1.h, z0.h
+bfclamp z3.h,z4.h,z16.h
+bfmla z3.h,z16.h,z6.h[7]
+bfmls z3.h,z16.h,z6.h[7]
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 5172515adde..1ed7032697d 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2717,8 +2717,8 @@ static const aarch64_feature_set aarch64_feature_the =
AARCH64_FEATURE (THE);
static const aarch64_feature_set aarch64_feature_d128_the =
AARCH64_FEATURES (2, D128, THE);
-static const aarch64_feature_set aarch64_feature_b16b16 =
- AARCH64_FEATURE (B16B16);
+static const aarch64_feature_set aarch64_feature_b16b16_sve2 =
+ AARCH64_FEATURES (2, B16B16, SVE2);
static const aarch64_feature_set aarch64_feature_sme2p1 =
AARCH64_FEATURE (SME2p1);
static const aarch64_feature_set aarch64_feature_sve2p1 =
@@ -2807,7 +2807,7 @@ static const aarch64_feature_set aarch64_feature_lut_sve2 =
#define D128 &aarch64_feature_d128
#define THE &aarch64_feature_the
#define D128_THE &aarch64_feature_d128_the
-#define B16B16 &aarch64_feature_b16b16
+#define B16B16_SVE2 &aarch64_feature_b16b16_sve2
#define SME2p1 &aarch64_feature_sme2p1
#define SVE2p1 &aarch64_feature_sve2p1
#define RCPC3 &aarch64_feature_rcpc3
@@ -2893,11 +2893,11 @@ static const aarch64_feature_set aarch64_feature_lut_sve2 =
#define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
-#define B16B16_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
- { NAME, OPCODE, MASK, CLASS, OP, B16B16, OPS, QUALS, \
+#define B16B16_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, B16B16_SVE2, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
-#define B16B16_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
- { NAME, OPCODE, MASK, CLASS, OP, B16B16, OPS, QUALS, \
+#define B16B16_SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, B16B16_SVE2, OPS, QUALS, \
FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
#define SVE2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \
@@ -6475,22 +6475,22 @@ const struct aarch64_opcode aarch64_opcode_table[] =
D128_THE_INSN("rcwsswppl", 0x5960a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0),
/* BFloat16 SVE Instructions. */
- B16B16_INSNC("bfadd", 0x65008000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
- B16B16_INSNC("bfmax", 0x65068000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
- B16B16_INSNC("bfmaxnm", 0x65048000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
- B16B16_INSNC("bfmin", 0x65078000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
- B16B16_INSNC("bfminnm", 0x65058000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
- B16B16_INSNC("bfmla", 0x65200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
- B16B16_INSNC("bfmls", 0x65202000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
- B16B16_INSNC("bfmul", 0x65028000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
- B16B16_INSNC("bfsub", 0x65018000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
- B16B16_INSN("bfadd", 0x65000000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
- B16B16_INSN("bfclamp", 0x64202400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
- B16B16_INSN("bfmul", 0x65000800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
- B16B16_INSN("bfsub", 0x65000400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
- B16B16_INSN("bfmla", 0x64200800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
- B16B16_INSN("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
- B16B16_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
+ B16B16_SVE2_INSNC("bfadd", 0x65008000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+ B16B16_SVE2_INSNC("bfmax", 0x65068000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+ B16B16_SVE2_INSNC("bfmaxnm", 0x65048000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+ B16B16_SVE2_INSNC("bfmin", 0x65078000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+ B16B16_SVE2_INSNC("bfminnm", 0x65058000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+ B16B16_SVE2_INSNC("bfmla", 0x65200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
+ B16B16_SVE2_INSNC("bfmls", 0x65202000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
+ B16B16_SVE2_INSNC("bfmul", 0x65028000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+ B16B16_SVE2_INSNC("bfsub", 0x65018000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+ B16B16_SVE2_INSNC("bfclamp", 0x64202400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, C_SCAN_MOVPRFX, 0),
+ B16B16_SVE2_INSNC("bfmla", 0x64200800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0),
+ B16B16_SVE2_INSNC("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0),
+ B16B16_SVE2_INSN("bfadd", 0x65000000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
+ B16B16_SVE2_INSN("bfmul", 0x65000800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
+ B16B16_SVE2_INSN("bfsub", 0x65000400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
+ B16B16_SVE2_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
/* SME2.1 movaz instructions. */
SME2p1_INSN ("movaz", 0xc0060600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsb_2), OP_SVE_BB, 0, 0),
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v1 10/11] [Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints.
2024-06-12 15:59 ` [PATCH v1 10/11] [Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints srinath
@ 2024-06-13 15:44 ` Richard Earnshaw (lists)
2024-06-14 15:44 ` Andre Vieira (lists)
0 siblings, 1 reply; 18+ messages in thread
From: Richard Earnshaw (lists) @ 2024-06-13 15:44 UTC (permalink / raw)
To: srinath, binutils; +Cc: nickc
On 12/06/2024 16:59, srinath wrote:
>
> Hi,
>
> This patch adds missing contraints to FEAT_B16B16 sve2 instructions
> bfclamp, bfmla and bfmls and add negative tests for all the bfloat
> instructions.
>
> Regression tested for aarch64-none-elf target and found no regressions.
>
> Ok for binutils-master?
>
> Regards,
> Srinath.
> ---
> gas/testsuite/gas/aarch64/bfloat16-1.d | 6 +
> gas/testsuite/gas/aarch64/bfloat16-1.s | 7 +-
> .../gas/aarch64/bfloat16-2-invalid.d | 4 +
> .../gas/aarch64/bfloat16-2-invalid.l | 265 ++++++++++++++++++
> .../gas/aarch64/bfloat16-2-invalid.s | 147 ++++++++++
> gas/testsuite/gas/aarch64/bfloat16-bad.l | 3 +
> gas/testsuite/gas/aarch64/bfloat16-invalid.d | 2 +-
> gas/testsuite/gas/aarch64/bfloat16-invalid.l | 17 +-
> gas/testsuite/gas/aarch64/bfloat16-invalid.s | 9 +-
> opcodes/aarch64-tbl.h | 46 +--
> 10 files changed, 468 insertions(+), 38 deletions(-)
> create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.d
> create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
> create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.s
>
--- a/gas/testsuite/gas/aarch64/bfloat16-invalid.l
+++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.l
...
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmul .*
+.*: Error: operand 3 must be the same register as operand 1 -- `bfsub .*
+.*: Error: selected processor does not support `bfclamp z3.h,z4.h,z16.h'
+.*: Error: selected processor does not support `bfmla z3.h,z16.h,z6.h\[7\]'
+.*: Error: selected processor does not support `bfmls z3.h,z16.h,z6.h\[7\]'
It doesn't seem right to me that a test that is supposedly checking for invalid operand combinations would be reporting unsupported instructions. Perhaps these should be in a separate test with different command-line options?
R.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v1 10/11] [Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints.
2024-06-13 15:44 ` Richard Earnshaw (lists)
@ 2024-06-14 15:44 ` Andre Vieira (lists)
2024-06-14 16:20 ` Richard Earnshaw (lists)
0 siblings, 1 reply; 18+ messages in thread
From: Andre Vieira (lists) @ 2024-06-14 15:44 UTC (permalink / raw)
To: Richard Earnshaw (lists), srinath, binutils; +Cc: nickc
On 13/06/2024 16:44, Richard Earnshaw (lists) wrote:
> On 12/06/2024 16:59, srinath wrote:
>>
>> Hi,
>>
>> This patch adds missing contraints to FEAT_B16B16 sve2 instructions
>> bfclamp, bfmla and bfmls and add negative tests for all the bfloat
>> instructions.
>>
>> Regression tested for aarch64-none-elf target and found no regressions.
>>
>> Ok for binutils-master?
>>
>> Regards,
>> Srinath.
>> ---
>> gas/testsuite/gas/aarch64/bfloat16-1.d | 6 +
>> gas/testsuite/gas/aarch64/bfloat16-1.s | 7 +-
>> .../gas/aarch64/bfloat16-2-invalid.d | 4 +
>> .../gas/aarch64/bfloat16-2-invalid.l | 265 ++++++++++++++++++
>> .../gas/aarch64/bfloat16-2-invalid.s | 147 ++++++++++
>> gas/testsuite/gas/aarch64/bfloat16-bad.l | 3 +
>> gas/testsuite/gas/aarch64/bfloat16-invalid.d | 2 +-
>> gas/testsuite/gas/aarch64/bfloat16-invalid.l | 17 +-
>> gas/testsuite/gas/aarch64/bfloat16-invalid.s | 9 +-
>> opcodes/aarch64-tbl.h | 46 +--
>> 10 files changed, 468 insertions(+), 38 deletions(-)
>> create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.d
>> create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
>> create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.s
>>
> --- a/gas/testsuite/gas/aarch64/bfloat16-invalid.l
> +++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.l
> ...
> +.*: Error: operand 3 must be the same register as operand 1 -- `bfmul .*
> +.*: Error: operand 3 must be the same register as operand 1 -- `bfsub .*
> +.*: Error: selected processor does not support `bfclamp z3.h,z4.h,z16.h'
> +.*: Error: selected processor does not support `bfmla z3.h,z16.h,z6.h\[7\]'
> +.*: Error: selected processor does not support `bfmls z3.h,z16.h,z6.h\[7\]'
>
> It doesn't seem right to me that a test that is supposedly checking for invalid operand combinations would be reporting unsupported instructions. Perhaps these should be in a separate test with different command-line options?
I think you misunderstood here Richard, Srinath turned this test into a
'wrong command-line option/unsupported test' see:
diff --git a/gas/testsuite/gas/aarch64/bfloat16-invalid.d
b/gas/testsuite/gas/aarch64/bfloat16-invalid.d
index 8f24dc62083..02e3e8d8e3d 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-invalid.d
+++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.d
@@ -1,4 +1,4 @@
-#name: Test Bfloat16 instructions with wrong operand combinations
+#name: Negative test with missing +b16b16 bfloat16 flag.
The reason you got confused I think is because it also has wrong operand
errors, which is because gas reports these before it reports missing
support. It does so for other features too mind you, so we are
consistent here AFAICT.
I do think however, that this test should have at least one of each of
the new instructions with proper operands, so that we can make sure the
test checks these are unsupported. For instance bfadd is only in here
with wrong operands. So it's not actually testing that we don't support
bfadd with -march=armv9.4-a
Whether we should also include wrong operands here, testing that gas
checks those before support for the actual instruction is a decision
that I'll leave to you Richard. On one side if we decide to change the
behavior we'd have to go back and change these files, but that itself
may be a benefit to having the tests... we could make sure the behavior
doesn't change unnoticed.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v1 10/11] [Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints.
2024-06-14 15:44 ` Andre Vieira (lists)
@ 2024-06-14 16:20 ` Richard Earnshaw (lists)
0 siblings, 0 replies; 18+ messages in thread
From: Richard Earnshaw (lists) @ 2024-06-14 16:20 UTC (permalink / raw)
To: Andre Vieira (lists), srinath, binutils; +Cc: nickc
On 14/06/2024 16:44, Andre Vieira (lists) wrote:
>
>
> On 13/06/2024 16:44, Richard Earnshaw (lists) wrote:
>> On 12/06/2024 16:59, srinath wrote:
>>>
>>> Hi,
>>>
>>> This patch adds missing contraints to FEAT_B16B16 sve2 instructions
>>> bfclamp, bfmla and bfmls and add negative tests for all the bfloat
>>> instructions.
>>>
>>> Regression tested for aarch64-none-elf target and found no regressions.
>>>
>>> Ok for binutils-master?
>>>
>>> Regards,
>>> Srinath.
>>> ---
>>> gas/testsuite/gas/aarch64/bfloat16-1.d | 6 +
>>> gas/testsuite/gas/aarch64/bfloat16-1.s | 7 +-
>>> .../gas/aarch64/bfloat16-2-invalid.d | 4 +
>>> .../gas/aarch64/bfloat16-2-invalid.l | 265 ++++++++++++++++++
>>> .../gas/aarch64/bfloat16-2-invalid.s | 147 ++++++++++
>>> gas/testsuite/gas/aarch64/bfloat16-bad.l | 3 +
>>> gas/testsuite/gas/aarch64/bfloat16-invalid.d | 2 +-
>>> gas/testsuite/gas/aarch64/bfloat16-invalid.l | 17 +-
>>> gas/testsuite/gas/aarch64/bfloat16-invalid.s | 9 +-
>>> opcodes/aarch64-tbl.h | 46 +--
>>> 10 files changed, 468 insertions(+), 38 deletions(-)
>>> create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.d
>>> create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
>>> create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.s
>>>
>> --- a/gas/testsuite/gas/aarch64/bfloat16-invalid.l
>> +++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.l
>> ...
>> +.*: Error: operand 3 must be the same register as operand 1 -- `bfmul .*
>> +.*: Error: operand 3 must be the same register as operand 1 -- `bfsub .*
>> +.*: Error: selected processor does not support `bfclamp z3.h,z4.h,z16.h'
>> +.*: Error: selected processor does not support `bfmla z3.h,z16.h,z6.h\[7\]'
>> +.*: Error: selected processor does not support `bfmls z3.h,z16.h,z6.h\[7\]'
>>
>> It doesn't seem right to me that a test that is supposedly checking for invalid operand combinations would be reporting unsupported instructions. Perhaps these should be in a separate test with different command-line options?
>
> I think you misunderstood here Richard, Srinath turned this test into a 'wrong command-line option/unsupported test' see:
> diff --git a/gas/testsuite/gas/aarch64/bfloat16-invalid.d b/gas/testsuite/gas/aarch64/bfloat16-invalid.d
> index 8f24dc62083..02e3e8d8e3d 100644
> --- a/gas/testsuite/gas/aarch64/bfloat16-invalid.d
> +++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.d
> @@ -1,4 +1,4 @@
> -#name: Test Bfloat16 instructions with wrong operand combinations
> +#name: Negative test with missing +b16b16 bfloat16 flag.
That doesn't make sense to me. Why change an existing test for one thing into a different test that does something else? The existing test entries in the file now no-longer match the test summary.
This sort of change should be highlighted in the patch summary; patch review for complex patches is difficult enough as it is, without explanations as to why certain changes are made it's nearly impossible to intuit the reasoning behind the changes.
>
> The reason you got confused I think is because it also has wrong operand errors, which is because gas reports these before it reports missing support. It does so for other features too mind you, so we are consistent here AFAICT.
Everything in the existing bfloat16-invalid.l is an operand test, so why conflate this with something else? That doesn't look consistent to me.
Perhaps this could be addressed by writing it in the style of mops_invalid.[sdl] where we change the architecture features on the fly to test different errors. It would also help if the assembler source had some comments about the expected failures.
>
> I do think however, that this test should have at least one of each of the new instructions with proper operands, so that we can make sure the test checks these are unsupported. For instance bfadd is only in here with wrong operands. So it's not actually testing that we don't support bfadd with -march=armv9.4-a
>
> Whether we should also include wrong operands here, testing that gas checks those before support for the actual instruction is a decision that I'll leave to you Richard. On one side if we decide to change the behavior we'd have to go back and change these files, but that itself may be a benefit to having the tests... we could make sure the behavior doesn't change unnoticed.
R.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v1 11/11] [Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints (regenerated files).
2024-06-12 15:58 [PATCH v2 0/11][Binutils] aarch64: Fix the FEAT_SVE2p1 related issues srinath
` (9 preceding siblings ...)
2024-06-12 15:59 ` [PATCH v1 10/11] [Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints srinath
@ 2024-06-12 15:59 ` srinath
10 siblings, 0 replies; 18+ messages in thread
From: srinath @ 2024-06-12 15:59 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, srinath
[-- Attachment #1: Type: text/plain, Size: 244 bytes --]
Hi,
This patch includes the regenerated files for
[Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints.
Regards,
Srinath.
---
opcodes/aarch64-dis-2.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0011-Binutils-aarch64-Fix-FEAT_B16B16-sve2-instruction.patch --]
[-- Type: text/x-patch; name="v1-0011-Binutils-aarch64-Fix-FEAT_B16B16-sve2-instruction.patch", Size: 2885 bytes --]
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 477cd6feb22..b8894ac9fe0 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -17126,7 +17126,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x00x1xxxxx000x10xxxxxxxxxx
bfmla. */
- return 3294;
+ return 3291;
}
}
else
@@ -17145,7 +17145,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x00x1xxxxx000x11xxxxxxxxxx
bfmls. */
- return 3295;
+ return 3292;
}
}
}
@@ -32990,16 +32990,16 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode)
case 1696: return NULL; /* ldff1b --> NULL. */
case 1714: value = 1715; break; /* ldff1h --> ldff1h. */
case 1715: return NULL; /* ldff1h --> NULL. */
- case 2474: value = 3291; break; /* fclamp --> bfclamp. */
- case 3291: return NULL; /* bfclamp --> NULL. */
+ case 2474: value = 3290; break; /* fclamp --> bfclamp. */
+ case 3290: return NULL; /* bfclamp --> NULL. */
case 1788: value = 1789; break; /* ldr --> ldr. */
case 1789: return NULL; /* ldr --> NULL. */
- case 1444: value = 3290; break; /* fadd --> bfadd. */
- case 3290: return NULL; /* bfadd --> NULL. */
- case 1511: value = 3292; break; /* fmul --> bfmul. */
- case 3292: return NULL; /* bfmul --> NULL. */
- case 1537: value = 3293; break; /* fsub --> bfsub. */
- case 3293: return NULL; /* bfsub --> NULL. */
+ case 1444: value = 3293; break; /* fadd --> bfadd. */
+ case 3293: return NULL; /* bfadd --> NULL. */
+ case 1511: value = 3294; break; /* fmul --> bfmul. */
+ case 3294: return NULL; /* bfmul --> NULL. */
+ case 1537: value = 3295; break; /* fsub --> bfsub. */
+ case 3295: return NULL; /* bfsub --> NULL. */
case 1502: value = 3286; break; /* fmla --> bfmla. */
case 3286: return NULL; /* bfmla --> NULL. */
case 2007: value = 2008; break; /* str --> str. */
^ permalink raw reply [flat|nested] 18+ messages in thread