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charset="UTF-8"; format=fixed Content-Transfer-Encoding: 8bit Hi, This patch fixes the syntax of sve2p1 "dupq" instruction by modifying the way 2nd operand does the encoding and decoding using the [] value. dupq makes use of already existing aarch64_ins_sve_index and aarch64_ext_sve_index inserter and extractor functions. The definitions of aarch64_ins_sve_index_imm (inserter) and aarch64_ext_sve_index_imm (extractor) is removed in this patch. This issues was reported here: https://sourceware.org/pipermail/binutils/2024-February/132408.html Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils master? Regards, Srinath. --- gas/testsuite/gas/aarch64/sve2p1-1.d | 14 +++--- gas/testsuite/gas/aarch64/sve2p1-2-invalid.d | 3 ++ gas/testsuite/gas/aarch64/sve2p1-2-invalid.l | 47 ++++++++++++++++++++ gas/testsuite/gas/aarch64/sve2p1-2-invalid.s | 10 +++++ gas/testsuite/gas/aarch64/sve2p1-2.d | 34 ++++++++++++++ gas/testsuite/gas/aarch64/sve2p1-2.s | 28 ++++++++++++ include/opcode/aarch64.h | 2 +- opcodes/aarch64-asm.c | 19 +------- opcodes/aarch64-asm.h | 1 - opcodes/aarch64-dis.c | 36 ++------------- opcodes/aarch64-dis.h | 1 - opcodes/aarch64-tbl.h | 11 ++--- 12 files changed, 141 insertions(+), 65 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2.d create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2.s --------------2.25.1 Content-Type: text/x-patch; name="v3-0002-Binutils-aarch64-Fix-sve2p1-dupq-instruction-oper.patch" Content-Transfer-Encoding: 8bit Content-Disposition: attachment; filename="v3-0002-Binutils-aarch64-Fix-sve2p1-dupq-instruction-oper.patch" diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d index f562985b569..c61c0438b0a 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-1.d +++ b/gas/testsuite/gas/aarch64/sve2p1-1.d @@ -44,14 +44,14 @@ .*: 04cf2c44 uminqv v4.2d, p3, z2.d .*: 04cf3028 uminqv v8.2d, p4, z1.d .*: 048f3c10 uminqv v16.4s, p7, z0.s -.*: 0530268a dupq z10.b, z20.b\[0\] +.*: 0521268a dupq z10.b, z20.b\[0\] .*: 053f268a dupq z10.b, z20.b\[15\] -.*: 0521268a dupq z10.h, z20.h\[0\] -.*: 052f268a dupq z10.h, z20.h\[7\] -.*: 0522268a dupq z10.s, z20.s\[0\] -.*: 052e268a dupq z10.s, z20.s\[3\] -.*: 0524268a dupq z10.d, z20.d\[0\] -.*: 052c268a dupq z10.d, z20.d\[1\] +.*: 0522268a dupq z10.h, z20.h\[0\] +.*: 053e268a dupq z10.h, z20.h\[7\] +.*: 0524268a dupq z10.s, z20.s\[0\] +.*: 053c268a dupq z10.s, z20.s\[3\] +.*: 0528268a dupq z10.d, z20.d\[0\] +.*: 0538268a dupq z10.d, z20.d\[1\] .*: 041d2200 eorqv v0.16b, p0, z16.b .*: 045d2501 eorqv v1.8h, p1, z8.h .*: 049d2882 eorqv v2.4s, p2, z4.s diff --git a/gas/testsuite/gas/aarch64/sve2p1-2-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.d new file mode 100644 index 00000000000..3953ca57ac8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.d @@ -0,0 +1,3 @@ +#name: Test of illegal SVE2.1 dupq instructions. +#as: -march=armv9.4-a +#error_output: sve2p1-2-invalid.l diff --git a/gas/testsuite/gas/aarch64/sve2p1-2-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.l new file mode 100644 index 00000000000..26c24885d0b --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.l @@ -0,0 +1,47 @@ +.*: Assembler messages: +.*: Error: register element index out of range 0 to 15 at operand 2 -- `dupq z0.b,z0.b\[16\]' +.*: Error: operand mismatch -- `dupq z0.h,z0.b\[16\]' +.*: Info: did you mean this\? +.*: Info: dupq z0.b, z0.b\[16\] +.*: Info: other valid variant\(s\): +.*: Info: dupq z0.h, z0.h\[16\] +.*: Info: dupq z0.s, z0.s\[16\] +.*: Info: dupq z0.d, z0.d\[16\] +.*: Error: operand mismatch -- `dupq z0.h,z0.s\[16\]' +.*: Info: did you mean this\? +.*: Info: dupq z0.h, z0.h\[16\] +.*: Info: other valid variant\(s\): +.*: Info: dupq z0.b, z0.b\[16\] +.*: Info: dupq z0.s, z0.s\[16\] +.*: Info: dupq z0.d, z0.d\[16\] +.*: Error: operand mismatch -- `dupq z0.s,z0.d\[16\]' +.*: Info: did you mean this\? +.*: Info: dupq z0.s, z0.s\[16\] +.*: Info: other valid variant\(s\): +.*: Info: dupq z0.b, z0.b\[16\] +.*: Info: dupq z0.h, z0.h\[16\] +.*: Info: dupq z0.d, z0.d\[16\] +.*: Error: register element index out of range 0 to 7 at operand 2 -- `dupq z0.h,z0.h\[8\]' +.*: Error: register element index out of range 0 to 3 at operand 2 -- `dupq z0.s,z0.s\[4\]' +.*: Error: register element index out of range 0 to 1 at operand 2 -- `dupq z0.d,z0.d\[2\]' +.*: Error: operand mismatch -- `dupq z0.q,z0.d\[16\]' +.*: Info: did you mean this\? +.*: Info: dupq z0.d, z0.d\[16\] +.*: Info: other valid variant\(s\): +.*: Info: dupq z0.b, z0.b\[16\] +.*: Info: dupq z0.h, z0.h\[16\] +.*: Info: dupq z0.s, z0.s\[16\] +.*: Error: operand mismatch -- `dupq z0.s,z0.q\[16\]' +.*: Info: did you mean this\? +.*: Info: dupq z0.s, z0.s\[16\] +.*: Info: other valid variant\(s\): +.*: Info: dupq z0.b, z0.b\[16\] +.*: Info: dupq z0.h, z0.h\[16\] +.*: Info: dupq z0.d, z0.d\[16\] +.*: Error: operand mismatch -- `dupq z10.q,z20.q\[0\]' +.*: Info: did you mean this\? +.*: Info: dupq z10.b, z20.b\[0\] +.*: Info: other valid variant\(s\): +.*: Info: dupq z10.h, z20.h\[0\] +.*: Info: dupq z10.s, z20.s\[0\] +.*: Info: dupq z10.d, z20.d\[0\] diff --git a/gas/testsuite/gas/aarch64/sve2p1-2-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.s new file mode 100644 index 00000000000..8f5fd528bc7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.s @@ -0,0 +1,10 @@ + dupq z0.b, z0.b[16] + dupq z0.h, z0.b[16] + dupq z0.h, z0.s[16] + dupq z0.s, z0.d[16] + dupq z0.h, z0.h[8] + dupq z0.s, z0.s[4] + dupq z0.d, z0.d[2] + dupq z0.q, z0.d[16] + dupq z0.s, z0.q[16] + dupq z10.q, z20.q[0] diff --git a/gas/testsuite/gas/aarch64/sve2p1-2.d b/gas/testsuite/gas/aarch64/sve2p1-2.d new file mode 100644 index 00000000000..cd9900da2b0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-2.d @@ -0,0 +1,34 @@ +#name: Test of SVE2.1 dupq instructions. +#as: -march=armv9.4-a +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: 05212400 dupq z0.b, z0.b\[0\] +.*: 0521241f dupq z31.b, z0.b\[0\] +.*: 052127e0 dupq z0.b, z31.b\[0\] +.*: 053f2400 dupq z0.b, z0.b\[15\] +.*: 053f27ff dupq z31.b, z31.b\[15\] +.*: 052925e7 dupq z7.b, z15.b\[4\] +.*: 05222400 dupq z0.h, z0.h\[0\] +.*: 0522241f dupq z31.h, z0.h\[0\] +.*: 052227e0 dupq z0.h, z31.h\[0\] +.*: 053e2400 dupq z0.h, z0.h\[7\] +.*: 053e27ff dupq z31.h, z31.h\[7\] +.*: 053225e7 dupq z7.h, z15.h\[4\] +.*: 05242400 dupq z0.s, z0.s\[0\] +.*: 0524241f dupq z31.s, z0.s\[0\] +.*: 052427e0 dupq z0.s, z31.s\[0\] +.*: 053c2400 dupq z0.s, z0.s\[3\] +.*: 053c27ff dupq z31.s, z31.s\[3\] +.*: 053425e7 dupq z7.s, z15.s\[2\] +.*: 05282400 dupq z0.d, z0.d\[0\] +.*: 0528241f dupq z31.d, z0.d\[0\] +.*: 052827e0 dupq z0.d, z31.d\[0\] +.*: 05382400 dupq z0.d, z0.d\[1\] +.*: 053827ff dupq z31.d, z31.d\[1\] +.*: 052825e7 dupq z7.d, z15.d\[0\] diff --git a/gas/testsuite/gas/aarch64/sve2p1-2.s b/gas/testsuite/gas/aarch64/sve2p1-2.s new file mode 100644 index 00000000000..4fc3cdc9e26 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-2.s @@ -0,0 +1,28 @@ + .text + dupq z0.b, z0.b[0] + dupq z31.b, z0.b[0] + dupq z0.b, z31.b[0] + dupq z0.b, z0.b[15] + dupq z31.b, z31.b[15] + dupq z7.b, z15.b[4] + + dupq z0.h, z0.h[0] + dupq z31.h, z0.h[0] + dupq z0.h, z31.h[0] + dupq z0.h, z0.h[7] + dupq z31.h, z31.h[7] + dupq z7.h, z15.h[4] + + dupq z0.s, z0.s[0] + dupq z31.s, z0.s[0] + dupq z0.s, z31.s[0] + dupq z0.s, z0.s[3] + dupq z31.s, z31.s[3] + dupq z7.s, z15.s[2] + + dupq z0.d, z0.d[0] + dupq z31.d, z0.d[0] + dupq z0.d, z31.d[0] + dupq z0.d, z0.d[1] + dupq z31.d, z31.d[1] + dupq z7.d, z15.d[0] diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 7ae30bb456c..db4e99cc868 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -749,8 +749,8 @@ enum aarch64_opnd AARCH64_OPND_SVE_Zm_imm4, /* SVE vector register with 4bit index. */ AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ - AARCH64_OPND_SVE_Zn_5_INDEX, /* Indexed SVE vector register, for DUPQ. */ AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ + AARCH64_OPND_SVE_Zn_5_INDEX, /* Indexed SVE vector register, for DUPQ. */ AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 5c6a31167c6..f5cb69270e8 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1281,23 +1281,8 @@ aarch64_ins_sve_index (const aarch64_operand *self, { unsigned int esize = aarch64_get_qualifier_esize (info->qualifier); insert_field (self->fields[0], code, info->reglane.regno, 0); - insert_fields (code, (info->reglane.index * 2 + 1) * esize, 0, - 2, FLD_imm5, FLD_SVE_tszh); - return true; -} - -/* Encode Zn.[], where is an immediate with range of 0 to one less - than the number of elements in 128 bit, which can encode il:tsz. */ -bool -aarch64_ins_sve_index_imm (const aarch64_operand *self, - const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED, - aarch64_operand_error *errors ATTRIBUTE_UNUSED) -{ - insert_field (self->fields[0], code, info->reglane.regno, 0); - unsigned int esize = aarch64_get_qualifier_esize (info->qualifier); - insert_fields (code, (info->reglane.index * 2 + 1) * esize, 0, - 2, self->fields[1],self->fields[2]); + insert_all_fields_after (self, 1, code, + (info->reglane.index * 2 + 1) * esize); return true; } diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h index edeb6d8de7e..88143eecfcd 100644 --- a/opcodes/aarch64-asm.h +++ b/opcodes/aarch64-asm.h @@ -95,7 +95,6 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_one); AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_two); AARCH64_DECL_OPD_INSERTER (ins_sve_float_zero_one); AARCH64_DECL_OPD_INSERTER (ins_sve_index); -AARCH64_DECL_OPD_INSERTER (ins_sve_index_imm); AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov); AARCH64_DECL_OPD_INSERTER (ins_sve_quad_index); AARCH64_DECL_OPD_INSERTER (ins_sve_reglist); diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 213df616608..d08cf057336 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2222,7 +2222,7 @@ aarch64_ext_sve_index (const aarch64_operand *self, int val; info->reglane.regno = extract_field (self->fields[0], code, 0); - val = extract_fields (code, 0, 2, FLD_SVE_tszh, FLD_imm5); + val = extract_all_fields_after (self, 1, code); if ((val & 31) == 0) return 0; while ((val & 1) == 0) @@ -2231,26 +2231,6 @@ aarch64_ext_sve_index (const aarch64_operand *self, return true; } -/* Decode Zn.[], where is an immediate with range of 0 to one less - than the number of elements in 128 bit, which can encode il:tsz. */ -bool -aarch64_ext_sve_index_imm (const aarch64_operand *self, - aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED, - aarch64_operand_error *errors ATTRIBUTE_UNUSED) -{ - int val; - - info->reglane.regno = extract_field (self->fields[0], code, 0); - val = extract_fields (code, 0, 2, self->fields[2], self->fields[1]); - if ((val & 15) == 0) - return 0; - while ((val & 1) == 0) - val /= 2; - info->reglane.index = val / 2; - return true; -} - /* Decode a logical immediate for the MOV alias of SVE DUPM. */ bool aarch64_ext_sve_limm_mov (const aarch64_operand *self, @@ -3435,7 +3415,8 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) break; case sve_index: - i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5); + i = extract_field (FLD_imm5, inst->value, 0); + if ((i & 31) == 0) return false; while ((i & 1) == 0) @@ -3445,17 +3426,6 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) } break; - case sve_index1: - i = extract_fields (inst->value, 0, 2, FLD_SVE_tsz, FLD_SVE_i2h); - if ((i & 15) == 0) - return false; - while ((i & 1) == 0) - { - i >>= 1; - variant += 1; - } - break; - case sve_limm: /* Pick the smallest applicable element size. */ if ((inst->value & 0x20600) == 0x600) diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h index 9e8f7c214d7..a71524f9c64 100644 --- a/opcodes/aarch64-dis.h +++ b/opcodes/aarch64-dis.h @@ -119,7 +119,6 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_one); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_two); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_zero_one); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index); -AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index_imm); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_limm_mov); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_quad_index); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist); diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 1d12630273e..0ae54bc1ef7 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -6518,7 +6518,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = SVE2p1_INSNC("fminnmqv",0x6415a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), SVE2p1_INSNC("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), - SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index1, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0), + SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0), SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 1), SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0), SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), @@ -7109,11 +7109,12 @@ const struct aarch64_opcode aarch64_opcode_table[] = "an indexed SVE vector register") \ Y(SVE_REG, regno, "SVE_Zn", 0, F(FLD_SVE_Zn), \ "an SVE vector register") \ - Y(SVE_REG, sve_index_imm, "SVE_Zn_5_INDEX", 0, \ - F(FLD_SVE_Zn, FLD_SVE_i2h, FLD_SVE_tsz), \ - "a 5 bit idexed SVE vector register") \ - Y(SVE_REG, sve_index, "SVE_Zn_INDEX", 0, F(FLD_SVE_Zn), \ + Y(SVE_REG, sve_index, "SVE_Zn_INDEX", 0, \ + F(FLD_SVE_Zn, FLD_SVE_tszh, FLD_imm5), \ "an indexed SVE vector register") \ + Y(SVE_REG, sve_index, "SVE_Zn_5_INDEX", 0, \ + F(FLD_SVE_Zn, FLD_imm5), \ + "a 5 bit indexed SVE vector register") \ Y(SVE_REGLIST, sve_reglist, "SVE_ZnxN", 0, F(FLD_SVE_Zn), \ "a list of SVE vector registers") \ Y(SVE_REG, regno, "SVE_Zt", 0, F(FLD_SVE_Zt), \ --------------2.25.1--