From: Matthieu Longo <matthieu.longo@arm.com>
To: <binutils@sourceware.org>
Cc: Richard Earnshaw <richard.earnshaw@arm.com>,
Nick Clifton <nickc@redhat.com>,
Matthieu Longo <matthieu.longo@arm.com>
Subject: [PATCH v1 1/4] aarch64: add E3DSE feature and its associated registers
Date: Thu, 4 Jul 2024 15:23:35 +0100 [thread overview]
Message-ID: <20240704142338.1582659-2-matthieu.longo@arm.com> (raw)
In-Reply-To: <20240704142338.1582659-1-matthieu.longo@arm.com>
[-- Attachment #1: Type: text/plain, Size: 1033 bytes --]
AArch64 defines new registers for the feature e3dse (Delegated SError
exceptions for EL3): vdisr_el3 and vdisr_el3. e3dse is an Armv9.5-A
feature.
This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.
---
.../sysreg/armv9_5-a-sysregs-archv9_4-unsupported.d | 3 +++
.../sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l | 9 +++++++++
.../gas/aarch64/sysreg/armv9_5-a-sysregs.d | 13 +++++++++++++
.../gas/aarch64/sysreg/armv9_5-a-sysregs.s | 7 +++++++
include/opcode/aarch64.h | 6 +++++-
opcodes/aarch64-sys-regs.def | 2 ++
6 files changed, 39 insertions(+), 1 deletion(-)
create mode 100644 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.d
create mode 100644 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
create mode 100644 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
create mode 100644 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0001-aarch64-add-E3DSE-feature-and-its-associated-regi.patch --]
[-- Type: text/x-patch; name="v1-0001-aarch64-add-E3DSE-feature-and-its-associated-regi.patch", Size: 4555 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.d b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.d
new file mode 100644
index 00000000000..8ad01bc7409
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.d
@@ -0,0 +1,3 @@
+#source: armv9_5-a-sysregs.s
+#as: -march=armv9.4-a -I$srcdir/$subdir
+#error_output: armv9_5-a-sysregs-archv9_4-unsupported.l
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
new file mode 100644
index 00000000000..cf7f21febf7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
@@ -0,0 +1,9 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support system register name 'vdisr_el3'
+[^ :]+:[0-9]+: Info: macro invoked from here
+[^ :]+:[0-9]+: Error: selected processor does not support system register name 'vdisr_el3'
+[^ :]+:[0-9]+: Info: macro invoked from here
+[^ :]+:[0-9]+: Error: selected processor does not support system register name 'vsesr_el3'
+[^ :]+:[0-9]+: Info: macro invoked from here
+[^ :]+:[0-9]+: Error: selected processor does not support system register name 'vsesr_el3'
+[^ :]+:[0-9]+: Info: macro invoked from here
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
new file mode 100644
index 00000000000..31f4eb8e9cb
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
@@ -0,0 +1,13 @@
+#source: armv9_5-a-sysregs.s
+#as: -march=armv9.5-a -I$srcdir/$subdir
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*: d51ec120 msr vdisr_el3, x0
+.*: d53ec120 mrs x0, vdisr_el3
+.*: d51e5260 msr vsesr_el3, x0
+.*: d53e5260 mrs x0, vsesr_el3
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s
new file mode 100644
index 00000000000..085fced1652
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s
@@ -0,0 +1,7 @@
+.include "sysreg-test-utils.inc"
+
+.text
+
+/* Delegated SError exceptions for EL3. */
+rw_sys_reg sys_reg=vdisr_el3 xreg=x0 r=1 w=1
+rw_sys_reg sys_reg=vsesr_el3 xreg=x0 r=1 w=1
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 9daa911394f..17c4ee95e73 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -183,6 +183,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_LSE128,
/* ARMv8.9-A RAS Extensions. */
AARCH64_FEATURE_RASv2,
+ /* Delegated SError exceptions for EL3. */
+ AARCH64_FEATURE_E3DSE,
/* System Control Register2. */
AARCH64_FEATURE_SCTLR2,
/* Fine Grained Traps. */
@@ -366,7 +368,9 @@ enum aarch64_feature_bit {
#define AARCH64_ARCH_V9_5A_FEATURES(X) (AARCH64_FEATBIT (X, V9_5A) \
| AARCH64_FEATBIT (X, CPA) \
| AARCH64_FEATBIT (X, LUT) \
- | AARCH64_FEATBIT (X, FAMINMAX))
+ | AARCH64_FEATBIT (X, FAMINMAX)\
+ | AARCH64_FEATBIT (X, E3DSE) \
+ )
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8A(X) (AARCH64_FEATBIT (X, V8) \
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 3e68035d62a..def3dd65633 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -1229,6 +1229,7 @@
SYSREG ("vbar_el2", CPENC (3,4,12,0,0), 0, AARCH64_NO_FEATURES)
SYSREG ("vbar_el3", CPENC (3,6,12,0,0), 0, AARCH64_NO_FEATURES)
SYSREG ("vdisr_el2", CPENC (3,4,12,1,1), F_ARCHEXT, AARCH64_FEATURE (RAS))
+ SYSREG ("vdisr_el3", CPENC (3,6,12,1,1), F_ARCHEXT, AARCH64_FEATURE (E3DSE))
SYSREG ("vmecid_a_el2", CPENC (3,4,10,9,1), 0, AARCH64_NO_FEATURES)
SYSREG ("vmecid_p_el2", CPENC (3,4,10,9,0), 0, AARCH64_NO_FEATURES)
SYSREG ("vmpidr_el2", CPENC (3,4,0,0,5), 0, AARCH64_NO_FEATURES)
@@ -1236,6 +1237,7 @@
SYSREG ("vpidr_el2", CPENC (3,4,0,0,0), 0, AARCH64_NO_FEATURES)
SYSREG ("vsctlr_el2", CPENC (3,4,2,0,0), F_ARCHEXT, AARCH64_FEATURE (V8R))
SYSREG ("vsesr_el2", CPENC (3,4,5,2,3), F_ARCHEXT, AARCH64_FEATURE (RAS))
+ SYSREG ("vsesr_el3", CPENC (3,6,5,2,3), F_ARCHEXT, AARCH64_FEATURE (E3DSE))
SYSREG ("vstcr_el2", CPENC (3,4,2,6,2), F_ARCHEXT, AARCH64_FEATURE (V8_4A))
SYSREG ("vsttbr_el2", CPENC (3,4,2,6,0), F_ARCHEXT, AARCH64_FEATURES (2, V8A, V8_4A))
SYSREG ("vtcr_el2", CPENC (3,4,2,1,2), 0, AARCH64_NO_FEATURES)
next prev parent reply other threads:[~2024-07-04 14:24 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-04 14:23 [PATCH v1 0/4] aarch64: add new Armv9.5-A features and their associated registers (RAS, Debug, Performance Monitor) Matthieu Longo
2024-07-04 14:23 ` Matthieu Longo [this message]
2024-07-04 14:23 ` [PATCH v1 2/4] aarch64: add SPMU2 feature and its associated registers Matthieu Longo
2024-07-04 14:23 ` [PATCH v1 3/4] aarch64: add STEP2 " Matthieu Longo
2024-07-04 14:23 ` [PATCH v1 4/4] aarch64: add Debug Feature Register 2 (ID_AA64DFR2_EL1) Matthieu Longo
2024-07-05 12:20 ` [PATCH v1 0/4] aarch64: add new Armv9.5-A features and their associated registers (RAS, Debug, Performance Monitor) Richard Earnshaw (lists)
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