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charset="UTF-8"; format=fixed Content-Transfer-Encoding: 8bit AArch64 defines new registers for the feature spmu2 (System Performance Monitors Extension version 2). spmu2 is an Armv9.5-A feature. This patch also adds relevant tests. Regression tested on aarch64-none-elf, and no regression found. --- .../aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l | 4 ++++ gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d | 2 ++ gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s | 3 +++ include/opcode/aarch64.h | 3 +++ opcodes/aarch64-sys-regs.def | 1 + 5 files changed, 13 insertions(+) --------------2.45.1 Content-Type: text/x-patch; name="v1-0002-aarch64-add-SPMU2-feature-and-its-associated-regi.patch" Content-Transfer-Encoding: 8bit Content-Disposition: attachment; filename="v1-0002-aarch64-add-SPMU2-feature-and-its-associated-regi.patch" diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l index cf7f21febf7..66dd5e8558e 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l +++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l @@ -7,3 +7,7 @@ [^ :]+:[0-9]+: Info: macro invoked from here [^ :]+:[0-9]+: Error: selected processor does not support system register name 'vsesr_el3' [^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: selected processor does not support system register name 'spmzr_el0' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: selected processor does not support system register name 'spmzr_el0' +[^ :]+:[0-9]+: Info: macro invoked from here \ No newline at end of file diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d index 31f4eb8e9cb..1a6c3be8abb 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d +++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d @@ -11,3 +11,5 @@ Disassembly of section \.text: .*: d53ec120 mrs x0, vdisr_el3 .*: d51e5260 msr vsesr_el3, x0 .*: d53e5260 mrs x0, vsesr_el3 +.*: d5139c80 msr spmzr_el0, x0 +.*: d5339c80 mrs x0, spmzr_el0 diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s index 085fced1652..701a80ce903 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s +++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s @@ -5,3 +5,6 @@ /* Delegated SError exceptions for EL3. */ rw_sys_reg sys_reg=vdisr_el3 xreg=x0 r=1 w=1 rw_sys_reg sys_reg=vsesr_el3 xreg=x0 r=1 w=1 + +/* System Performance Monitors Extension version 2. */ +rw_sys_reg sys_reg=spmzr_el0 xreg=x0 r=1 w=1 diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 17c4ee95e73..4dc30193d40 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -222,6 +222,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_PMUv3_ICNTR, /* System Performance Monitors Extension */ AARCH64_FEATURE_SPMU, + /* System Performance Monitors Extension version 2 */ + AARCH64_FEATURE_SPMU2, /* Performance Monitors Synchronous-Exception-Based Event Extension. */ AARCH64_FEATURE_SEBEP, /* SVE2.1 and SME2.1 non-widening BFloat16 instructions. */ @@ -370,6 +372,7 @@ enum aarch64_feature_bit { | AARCH64_FEATBIT (X, LUT) \ | AARCH64_FEATBIT (X, FAMINMAX)\ | AARCH64_FEATBIT (X, E3DSE) \ + | AARCH64_FEATBIT (X, SPMU2) \ ) /* Architectures are the sum of the base and extensions. */ diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def index def3dd65633..4fbc65e32fd 100644 --- a/opcodes/aarch64-sys-regs.def +++ b/opcodes/aarch64-sys-regs.def @@ -951,6 +951,7 @@ SYSREG ("spmrootcr_el3", CPENC (2,6,9,14,7), F_ARCHEXT, AARCH64_FEATURE (SPMU)) SYSREG ("spmscr_el1", CPENC (2,7,9,14,7), F_ARCHEXT, AARCH64_FEATURE (SPMU)) SYSREG ("spmselr_el0", CPENC (2,3,9,12,5), F_ARCHEXT, AARCH64_FEATURE (SPMU)) + SYSREG ("spmzr_el0", CPENC (2,3,9,12,4), F_ARCHEXT, AARCH64_FEATURE (SPMU2)) SYSREG ("spsel", CPENC (3,0,4,2,0), 0, AARCH64_NO_FEATURES) SYSREG ("spsr_abt", CPENC (3,4,4,3,1), 0, AARCH64_NO_FEATURES) SYSREG ("spsr_el1", CPENC (3,0,4,0,0), 0, AARCH64_NO_FEATURES) --------------2.45.1--