[PATCH v1 3/4] aarch64: add STEP2 feature and its associated registers

[Matthieu Longo <matthieu.longo@arm.com>]

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AArch64 defines new registers for the feature step2 (Enhanced Software Step
Extension). step2 is an Armv9.5-A feature.

This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.
---
 .../aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l   | 4 ++++
 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d          | 2 ++
 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s          | 3 +++
 include/opcode/aarch64.h                                      | 3 +++
 opcodes/aarch64-sys-regs.def                                  | 1 +
 5 files changed, 13 insertions(+)


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diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
index 66dd5e8558e..58e7f9b9c26 100644
--- a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
+++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
@@ -10,4 +10,8 @@
 [^ :]+:[0-9]+: Error: selected processor does not support system register name 'spmzr_el0'
 [^ :]+:[0-9]+:  Info: macro invoked from here
 [^ :]+:[0-9]+: Error: selected processor does not support system register name 'spmzr_el0'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: selected processor does not support system register name 'mdstepop_el1'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: selected processor does not support system register name 'mdstepop_el1'
 [^ :]+:[0-9]+:  Info: macro invoked from here
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
index 1a6c3be8abb..c52142d3998 100644
--- a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
+++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
@@ -13,3 +13,5 @@ Disassembly of section \.text:
 .*:	d53e5260 	mrs	x0, vsesr_el3
 .*:	d5139c80 	msr	spmzr_el0, x0
 .*:	d5339c80 	mrs	x0, spmzr_el0
+.*:	d5100540 	msr	mdstepop_el1, x0
+.*:	d5300540 	mrs	x0, mdstepop_el1
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s
index 701a80ce903..e3ba989c88e 100644
--- a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s
+++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s
@@ -8,3 +8,6 @@ rw_sys_reg sys_reg=vsesr_el3 xreg=x0 r=1 w=1
 
 /* System Performance Monitors Extension version 2. */
 rw_sys_reg sys_reg=spmzr_el0 xreg=x0 r=1 w=1
+
+/* Enhanced Software Step Extension. */
+rw_sys_reg sys_reg=mdstepop_el1 xreg=x0 r=1 w=1
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 4dc30193d40..dfed0a509b2 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -234,6 +234,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_SVE2p1,
   /* RCPC3 instructions.  */
   AARCH64_FEATURE_RCPC3,
+  /* Enhanced Software Step Extension. */
+  AARCH64_FEATURE_STEP2,
   /* Checked Pointer Arithmetic instructions. */
   AARCH64_FEATURE_CPA,
   /* FAMINMAX instructions.  */
@@ -373,6 +375,7 @@ enum aarch64_feature_bit {
 					 | AARCH64_FEATBIT (X, FAMINMAX)\
 					 | AARCH64_FEATBIT (X, E3DSE)	\
 					 | AARCH64_FEATBIT (X, SPMU2)	\
+					 | AARCH64_FEATBIT (X, STEP2)	\
 					)
 
 /* Architectures are the sum of the base and extensions.  */
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 4fbc65e32fd..cd2f1ac8516 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -573,6 +573,7 @@
   SYSREG ("mdrar_el1",		CPENC (2,0,1,0,0),	F_REG_READ,		AARCH64_NO_FEATURES)
   SYSREG ("mdscr_el1",		CPENC (2,0,0,2,2),	0,			AARCH64_NO_FEATURES)
   SYSREG ("mdselr_el1",		CPENC (2,0,0,4,2),	F_ARCHEXT,		AARCH64_FEATURE (DEBUGv8p9))
+  SYSREG ("mdstepop_el1",	CPENC (2,0,0,5,2),	F_ARCHEXT,		AARCH64_FEATURE (STEP2))
   SYSREG ("mecid_a0_el2",	CPENC (3,4,10,8,1),	0,			AARCH64_NO_FEATURES)
   SYSREG ("mecid_a1_el2",	CPENC (3,4,10,8,3),	0,			AARCH64_NO_FEATURES)
   SYSREG ("mecid_p0_el2",	CPENC (3,4,10,8,0),	0,			AARCH64_NO_FEATURES)