From: Matthieu Longo <matthieu.longo@arm.com>
To: <binutils@sourceware.org>
Cc: Richard Earnshaw <richard.earnshaw@arm.com>,
Nick Clifton <nickc@redhat.com>,
Matthieu Longo <matthieu.longo@arm.com>
Subject: [PATCH v1 4/4] aarch64: add Debug Feature Register 2 (ID_AA64DFR2_EL1)
Date: Thu, 4 Jul 2024 15:23:38 +0100 [thread overview]
Message-ID: <20240704142338.1582659-5-matthieu.longo@arm.com> (raw)
In-Reply-To: <20240704142338.1582659-1-matthieu.longo@arm.com>
[-- Attachment #1: Type: text/plain, Size: 297 bytes --]
This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.
---
gas/testsuite/gas/aarch64/sysreg/sysreg.d | 5 +++++
gas/testsuite/gas/aarch64/sysreg/sysreg.s | 5 +++++
opcodes/aarch64-sys-regs.def | 1 +
3 files changed, 11 insertions(+)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0004-aarch64-add-Debug-Feature-Register-2-ID_AA64DFR2_.patch --]
[-- Type: text/x-patch; name="v1-0004-aarch64-add-Debug-Feature-Register-2-ID_AA64DFR2_.patch", Size: 2112 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.d b/gas/testsuite/gas/aarch64/sysreg/sysreg.d
index 54ade34a87e..4fa9f0d559d 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg.d
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.d
@@ -11,6 +11,11 @@ Disassembly of section \.text:
.*: d53b9c60 mrs x0, pmovsclr_el0
.*: d51b9e60 msr pmovsset_el0, x0
.*: d53b9e60 mrs x0, pmovsset_el0
+.*: d5380580 mrs x0, id_aa64afr0_el1
+.*: d53805a0 mrs x0, id_aa64afr1_el1
+.*: d5380500 mrs x0, id_aa64dfr0_el1
+.*: d5380520 mrs x0, id_aa64dfr1_el1
+.*: d5380540 mrs x0, id_aa64dfr2_el1
.*: d5380140 mrs x0, id_dfr0_el1
.*: d5380100 mrs x0, id_pfr0_el1
.*: d5380120 mrs x0, id_pfr1_el1
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.s b/gas/testsuite/gas/aarch64/sysreg/sysreg.s
index 9c0fd4ae2fd..cf0461412b5 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg.s
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.s
@@ -5,6 +5,11 @@
rw_sys_reg sys_reg=pmovsclr_el0
rw_sys_reg sys_reg=pmovsset_el0
+ rw_sys_reg sys_reg=id_aa64afr0_el1 w=0
+ rw_sys_reg sys_reg=id_aa64afr1_el1 w=0
+ rw_sys_reg sys_reg=id_aa64dfr0_el1 w=0
+ rw_sys_reg sys_reg=id_aa64dfr1_el1 w=0
+ rw_sys_reg sys_reg=id_aa64dfr2_el1 w=0
rw_sys_reg sys_reg=id_dfr0_el1 w=0
rw_sys_reg sys_reg=id_pfr0_el1 w=0
rw_sys_reg sys_reg=id_pfr1_el1 w=0
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index cd2f1ac8516..6a554d9a12a 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -519,6 +519,7 @@
SYSREG ("id_aa64afr1_el1", CPENC (3,0,0,5,5), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64dfr0_el1", CPENC (3,0,0,5,0), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64dfr1_el1", CPENC (3,0,0,5,1), F_REG_READ, AARCH64_NO_FEATURES)
+ SYSREG ("id_aa64dfr2_el1", CPENC (3,0,0,5,2), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64isar0_el1", CPENC (3,0,0,6,0), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64isar1_el1", CPENC (3,0,0,6,1), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64isar2_el1", CPENC (3,0,0,6,2), F_REG_READ, AARCH64_NO_FEATURES)
next prev parent reply other threads:[~2024-07-04 14:24 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-04 14:23 [PATCH v1 0/4] aarch64: add new Armv9.5-A features and their associated registers (RAS, Debug, Performance Monitor) Matthieu Longo
2024-07-04 14:23 ` [PATCH v1 1/4] aarch64: add E3DSE feature and its associated registers Matthieu Longo
2024-07-04 14:23 ` [PATCH v1 2/4] aarch64: add SPMU2 " Matthieu Longo
2024-07-04 14:23 ` [PATCH v1 3/4] aarch64: add STEP2 " Matthieu Longo
2024-07-04 14:23 ` Matthieu Longo [this message]
2024-07-05 12:20 ` [PATCH v1 0/4] aarch64: add new Armv9.5-A features and their associated registers (RAS, Debug, Performance Monitor) Richard Earnshaw (lists)
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