[PATCH v1 0/4] aarch64: add new Armv9.5-A features and their associated registers (RAS, Debug, Performance Monitor)

[PATCH v1 0/4] aarch64: add new Armv9.5-A features and their associated registers (RAS, Debug, Performance Monitor)

[Matthieu Longo]

Hi,

[patch 0/4] aarch64: aarch64: add new Armv9.5-A features and their associated registers (RAS, Debug, Performance Monitor)
    [patch v1 1/4] aarch64: add E3DSE feature and its associated registers
    [patch v1 2/4] aarch64: add SPMU2 feature and its associated registers
    [patch v1 3/4] aarch64: add STEP2 feature and its associated registers
    [patch v1 4/4] aarch64: add Debug Feature Register 2 (ID_AA64DFR2_EL1)

AArch64 defines new registers for Armv9.5-A architecture.
This patch series adds the following features and their associated system registers:
- e3dse (Delegated SError exceptions for EL3)
- fpmu2 (System Performance Monitors Extension version 2)
- step2 (Enhanced Software Step Extension)
- ID_AA64DFR2_EL1 (Debug Feature Register 2)

Each patch also adds relevant tests.
Regression tested on aarch64-none-elf, and no regression found.

Ok for binutils-master?

Regards,
Matthieu.

Link to V0 posting: https://sourceware.org/pipermail/binutils/2024-June/135226.html

Revision 1:
- Split id_aa64dfr2_el1 from the registers for STEP2 feature.
- Add test for id_aa64dfr2_el1 and its friends.   


Matthieu Longo (4):
  aarch64: add E3DSE feature and its associated registers
  aarch64: add SPMU2 feature and its associated registers
  aarch64: add STEP2 feature and its associated registers
  aarch64: add Debug Feature Register 2 (ID_AA64DFR2_EL1)

 .../armv9_5-a-sysregs-archv9_4-unsupported.d    |  3 +++
 .../armv9_5-a-sysregs-archv9_4-unsupported.l    | 17 +++++++++++++++++
 .../gas/aarch64/sysreg/armv9_5-a-sysregs.d      | 17 +++++++++++++++++
 .../gas/aarch64/sysreg/armv9_5-a-sysregs.s      | 13 +++++++++++++
 gas/testsuite/gas/aarch64/sysreg/sysreg.d       |  5 +++++
 gas/testsuite/gas/aarch64/sysreg/sysreg.s       |  5 +++++
 include/opcode/aarch64.h                        | 12 +++++++++++-
 opcodes/aarch64-sys-regs.def                    |  5 +++++
 8 files changed, 76 insertions(+), 1 deletion(-)
 create mode 100644 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.d
 create mode 100644 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
 create mode 100644 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
 create mode 100644 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s

-- 
2.45.1

[PATCH v1 1/4] aarch64: add E3DSE feature and its associated registers

[Matthieu Longo]

[-- Attachment #1: Type: text/plain, Size: 1033 bytes --]


AArch64 defines new registers for the feature e3dse (Delegated SError
exceptions for EL3): vdisr_el3 and vdisr_el3. e3dse is an Armv9.5-A
feature.

This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.
---
 .../sysreg/armv9_5-a-sysregs-archv9_4-unsupported.d |  3 +++
 .../sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l |  9 +++++++++
 .../gas/aarch64/sysreg/armv9_5-a-sysregs.d          | 13 +++++++++++++
 .../gas/aarch64/sysreg/armv9_5-a-sysregs.s          |  7 +++++++
 include/opcode/aarch64.h                            |  6 +++++-
 opcodes/aarch64-sys-regs.def                        |  2 ++
 6 files changed, 39 insertions(+), 1 deletion(-)
 create mode 100644 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.d
 create mode 100644 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
 create mode 100644 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
 create mode 100644 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0001-aarch64-add-E3DSE-feature-and-its-associated-regi.patch --]
[-- Type: text/x-patch; name="v1-0001-aarch64-add-E3DSE-feature-and-its-associated-regi.patch", Size: 4555 bytes --]

diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.d b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.d
new file mode 100644
index 00000000000..8ad01bc7409
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.d
@@ -0,0 +1,3 @@
+#source: armv9_5-a-sysregs.s
+#as: -march=armv9.4-a -I$srcdir/$subdir
+#error_output: armv9_5-a-sysregs-archv9_4-unsupported.l
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
new file mode 100644
index 00000000000..cf7f21febf7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
@@ -0,0 +1,9 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support system register name 'vdisr_el3'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: selected processor does not support system register name 'vdisr_el3'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: selected processor does not support system register name 'vsesr_el3'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: selected processor does not support system register name 'vsesr_el3'
+[^ :]+:[0-9]+:  Info: macro invoked from here
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
new file mode 100644
index 00000000000..31f4eb8e9cb
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
@@ -0,0 +1,13 @@
+#source: armv9_5-a-sysregs.s
+#as: -march=armv9.5-a -I$srcdir/$subdir
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d51ec120 	msr	vdisr_el3, x0
+.*:	d53ec120 	mrs	x0, vdisr_el3
+.*:	d51e5260 	msr	vsesr_el3, x0
+.*:	d53e5260 	mrs	x0, vsesr_el3
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s
new file mode 100644
index 00000000000..085fced1652
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s
@@ -0,0 +1,7 @@
+.include "sysreg-test-utils.inc"
+
+.text
+
+/* Delegated SError exceptions for EL3. */
+rw_sys_reg sys_reg=vdisr_el3 xreg=x0 r=1 w=1
+rw_sys_reg sys_reg=vsesr_el3 xreg=x0 r=1 w=1
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 9daa911394f..17c4ee95e73 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -183,6 +183,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_LSE128,
   /* ARMv8.9-A RAS Extensions.  */
   AARCH64_FEATURE_RASv2,
+  /* Delegated SError exceptions for EL3. */
+  AARCH64_FEATURE_E3DSE,
   /* System Control Register2.  */
   AARCH64_FEATURE_SCTLR2,
   /* Fine Grained Traps.  */
@@ -366,7 +368,9 @@ enum aarch64_feature_bit {
 #define AARCH64_ARCH_V9_5A_FEATURES(X)	(AARCH64_FEATBIT (X, V9_5A)	\
 					 | AARCH64_FEATBIT (X, CPA)	\
 					 | AARCH64_FEATBIT (X, LUT)	\
-					 | AARCH64_FEATBIT (X, FAMINMAX))
+					 | AARCH64_FEATBIT (X, FAMINMAX)\
+					 | AARCH64_FEATBIT (X, E3DSE)	\
+					)
 
 /* Architectures are the sum of the base and extensions.  */
 #define AARCH64_ARCH_V8A(X)	(AARCH64_FEATBIT (X, V8) \
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 3e68035d62a..def3dd65633 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -1229,6 +1229,7 @@
   SYSREG ("vbar_el2",		CPENC (3,4,12,0,0),	0,			AARCH64_NO_FEATURES)
   SYSREG ("vbar_el3",		CPENC (3,6,12,0,0),	0,			AARCH64_NO_FEATURES)
   SYSREG ("vdisr_el2",		CPENC (3,4,12,1,1),	F_ARCHEXT,		AARCH64_FEATURE (RAS))
+  SYSREG ("vdisr_el3",		CPENC (3,6,12,1,1),	F_ARCHEXT,		AARCH64_FEATURE (E3DSE))
   SYSREG ("vmecid_a_el2",	CPENC (3,4,10,9,1),	0,			AARCH64_NO_FEATURES)
   SYSREG ("vmecid_p_el2",	CPENC (3,4,10,9,0),	0,			AARCH64_NO_FEATURES)
   SYSREG ("vmpidr_el2",		CPENC (3,4,0,0,5),	0,			AARCH64_NO_FEATURES)
@@ -1236,6 +1237,7 @@
   SYSREG ("vpidr_el2",		CPENC (3,4,0,0,0),	0,			AARCH64_NO_FEATURES)
   SYSREG ("vsctlr_el2",		CPENC (3,4,2,0,0),	F_ARCHEXT,		AARCH64_FEATURE (V8R))
   SYSREG ("vsesr_el2",		CPENC (3,4,5,2,3),	F_ARCHEXT,		AARCH64_FEATURE (RAS))
+  SYSREG ("vsesr_el3",		CPENC (3,6,5,2,3),	F_ARCHEXT,		AARCH64_FEATURE (E3DSE))
   SYSREG ("vstcr_el2",		CPENC (3,4,2,6,2),	F_ARCHEXT,		AARCH64_FEATURE (V8_4A))
   SYSREG ("vsttbr_el2",		CPENC (3,4,2,6,0),	F_ARCHEXT,		AARCH64_FEATURES (2, V8A, V8_4A))
   SYSREG ("vtcr_el2",		CPENC (3,4,2,1,2),	0,			AARCH64_NO_FEATURES)

[PATCH v1 2/4] aarch64: add SPMU2 feature and its associated registers

[Matthieu Longo]

[-- Attachment #1: Type: text/plain, Size: 630 bytes --]


AArch64 defines new registers for the feature spmu2 (System Performance
Monitors Extension version 2). spmu2 is an Armv9.5-A feature.

This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.
---
 .../aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l   | 4 ++++
 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d          | 2 ++
 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s          | 3 +++
 include/opcode/aarch64.h                                      | 3 +++
 opcodes/aarch64-sys-regs.def                                  | 1 +
 5 files changed, 13 insertions(+)


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0002-aarch64-add-SPMU2-feature-and-its-associated-regi.patch --]
[-- Type: text/x-patch; name="v1-0002-aarch64-add-SPMU2-feature-and-its-associated-regi.patch", Size: 3464 bytes --]

diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
index cf7f21febf7..66dd5e8558e 100644
--- a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
+++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
@@ -7,3 +7,7 @@
 [^ :]+:[0-9]+:  Info: macro invoked from here
 [^ :]+:[0-9]+: Error: selected processor does not support system register name 'vsesr_el3'
 [^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: selected processor does not support system register name 'spmzr_el0'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: selected processor does not support system register name 'spmzr_el0'
+[^ :]+:[0-9]+:  Info: macro invoked from here
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
index 31f4eb8e9cb..1a6c3be8abb 100644
--- a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
+++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
@@ -11,3 +11,5 @@ Disassembly of section \.text:
 .*:	d53ec120 	mrs	x0, vdisr_el3
 .*:	d51e5260 	msr	vsesr_el3, x0
 .*:	d53e5260 	mrs	x0, vsesr_el3
+.*:	d5139c80 	msr	spmzr_el0, x0
+.*:	d5339c80 	mrs	x0, spmzr_el0
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s
index 085fced1652..701a80ce903 100644
--- a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s
+++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s
@@ -5,3 +5,6 @@
 /* Delegated SError exceptions for EL3. */
 rw_sys_reg sys_reg=vdisr_el3 xreg=x0 r=1 w=1
 rw_sys_reg sys_reg=vsesr_el3 xreg=x0 r=1 w=1
+
+/* System Performance Monitors Extension version 2. */
+rw_sys_reg sys_reg=spmzr_el0 xreg=x0 r=1 w=1
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 17c4ee95e73..4dc30193d40 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -222,6 +222,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_PMUv3_ICNTR,
   /* System Performance Monitors Extension */
   AARCH64_FEATURE_SPMU,
+  /* System Performance Monitors Extension version 2 */
+  AARCH64_FEATURE_SPMU2,
   /* Performance Monitors Synchronous-Exception-Based Event Extension.  */
   AARCH64_FEATURE_SEBEP,
   /* SVE2.1 and SME2.1 non-widening BFloat16 instructions.  */
@@ -370,6 +372,7 @@ enum aarch64_feature_bit {
 					 | AARCH64_FEATBIT (X, LUT)	\
 					 | AARCH64_FEATBIT (X, FAMINMAX)\
 					 | AARCH64_FEATBIT (X, E3DSE)	\
+					 | AARCH64_FEATBIT (X, SPMU2)	\
 					)
 
 /* Architectures are the sum of the base and extensions.  */
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index def3dd65633..4fbc65e32fd 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -951,6 +951,7 @@
   SYSREG ("spmrootcr_el3",	CPENC (2,6,9,14,7),	F_ARCHEXT,		AARCH64_FEATURE (SPMU))
   SYSREG ("spmscr_el1",		CPENC (2,7,9,14,7),	F_ARCHEXT,		AARCH64_FEATURE (SPMU))
   SYSREG ("spmselr_el0",	CPENC (2,3,9,12,5),	F_ARCHEXT,		AARCH64_FEATURE (SPMU))
+  SYSREG ("spmzr_el0",		CPENC (2,3,9,12,4),	F_ARCHEXT,		AARCH64_FEATURE (SPMU2))
   SYSREG ("spsel",		CPENC (3,0,4,2,0),	0,			AARCH64_NO_FEATURES)
   SYSREG ("spsr_abt",		CPENC (3,4,4,3,1),	0,			AARCH64_NO_FEATURES)
   SYSREG ("spsr_el1",		CPENC (3,0,4,0,0),	0,			AARCH64_NO_FEATURES)

[PATCH v1 3/4] aarch64: add STEP2 feature and its associated registers

[Matthieu Longo]

[-- Attachment #1: Type: text/plain, Size: 615 bytes --]


AArch64 defines new registers for the feature step2 (Enhanced Software Step
Extension). step2 is an Armv9.5-A feature.

This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.
---
 .../aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l   | 4 ++++
 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d          | 2 ++
 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s          | 3 +++
 include/opcode/aarch64.h                                      | 3 +++
 opcodes/aarch64-sys-regs.def                                  | 1 +
 5 files changed, 13 insertions(+)


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0003-aarch64-add-STEP2-feature-and-its-associated-regi.patch --]
[-- Type: text/x-patch; name="v1-0003-aarch64-add-STEP2-feature-and-its-associated-regi.patch", Size: 3481 bytes --]

diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
index 66dd5e8558e..58e7f9b9c26 100644
--- a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
+++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
@@ -10,4 +10,8 @@
 [^ :]+:[0-9]+: Error: selected processor does not support system register name 'spmzr_el0'
 [^ :]+:[0-9]+:  Info: macro invoked from here
 [^ :]+:[0-9]+: Error: selected processor does not support system register name 'spmzr_el0'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: selected processor does not support system register name 'mdstepop_el1'
+[^ :]+:[0-9]+:  Info: macro invoked from here
+[^ :]+:[0-9]+: Error: selected processor does not support system register name 'mdstepop_el1'
 [^ :]+:[0-9]+:  Info: macro invoked from here
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
index 1a6c3be8abb..c52142d3998 100644
--- a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
+++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
@@ -13,3 +13,5 @@ Disassembly of section \.text:
 .*:	d53e5260 	mrs	x0, vsesr_el3
 .*:	d5139c80 	msr	spmzr_el0, x0
 .*:	d5339c80 	mrs	x0, spmzr_el0
+.*:	d5100540 	msr	mdstepop_el1, x0
+.*:	d5300540 	mrs	x0, mdstepop_el1
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s
index 701a80ce903..e3ba989c88e 100644
--- a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s
+++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s
@@ -8,3 +8,6 @@ rw_sys_reg sys_reg=vsesr_el3 xreg=x0 r=1 w=1
 
 /* System Performance Monitors Extension version 2. */
 rw_sys_reg sys_reg=spmzr_el0 xreg=x0 r=1 w=1
+
+/* Enhanced Software Step Extension. */
+rw_sys_reg sys_reg=mdstepop_el1 xreg=x0 r=1 w=1
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 4dc30193d40..dfed0a509b2 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -234,6 +234,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_SVE2p1,
   /* RCPC3 instructions.  */
   AARCH64_FEATURE_RCPC3,
+  /* Enhanced Software Step Extension. */
+  AARCH64_FEATURE_STEP2,
   /* Checked Pointer Arithmetic instructions. */
   AARCH64_FEATURE_CPA,
   /* FAMINMAX instructions.  */
@@ -373,6 +375,7 @@ enum aarch64_feature_bit {
 					 | AARCH64_FEATBIT (X, FAMINMAX)\
 					 | AARCH64_FEATBIT (X, E3DSE)	\
 					 | AARCH64_FEATBIT (X, SPMU2)	\
+					 | AARCH64_FEATBIT (X, STEP2)	\
 					)
 
 /* Architectures are the sum of the base and extensions.  */
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 4fbc65e32fd..cd2f1ac8516 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -573,6 +573,7 @@
   SYSREG ("mdrar_el1",		CPENC (2,0,1,0,0),	F_REG_READ,		AARCH64_NO_FEATURES)
   SYSREG ("mdscr_el1",		CPENC (2,0,0,2,2),	0,			AARCH64_NO_FEATURES)
   SYSREG ("mdselr_el1",		CPENC (2,0,0,4,2),	F_ARCHEXT,		AARCH64_FEATURE (DEBUGv8p9))
+  SYSREG ("mdstepop_el1",	CPENC (2,0,0,5,2),	F_ARCHEXT,		AARCH64_FEATURE (STEP2))
   SYSREG ("mecid_a0_el2",	CPENC (3,4,10,8,1),	0,			AARCH64_NO_FEATURES)
   SYSREG ("mecid_a1_el2",	CPENC (3,4,10,8,3),	0,			AARCH64_NO_FEATURES)
   SYSREG ("mecid_p0_el2",	CPENC (3,4,10,8,0),	0,			AARCH64_NO_FEATURES)

[PATCH v1 4/4] aarch64: add Debug Feature Register 2 (ID_AA64DFR2_EL1)

[Matthieu Longo]

[-- Attachment #1: Type: text/plain, Size: 297 bytes --]


This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.
---
 gas/testsuite/gas/aarch64/sysreg/sysreg.d | 5 +++++
 gas/testsuite/gas/aarch64/sysreg/sysreg.s | 5 +++++
 opcodes/aarch64-sys-regs.def              | 1 +
 3 files changed, 11 insertions(+)


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0004-aarch64-add-Debug-Feature-Register-2-ID_AA64DFR2_.patch --]
[-- Type: text/x-patch; name="v1-0004-aarch64-add-Debug-Feature-Register-2-ID_AA64DFR2_.patch", Size: 2112 bytes --]

diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.d b/gas/testsuite/gas/aarch64/sysreg/sysreg.d
index 54ade34a87e..4fa9f0d559d 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg.d
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.d
@@ -11,6 +11,11 @@ Disassembly of section \.text:
 .*:	d53b9c60 	mrs	x0, pmovsclr_el0
 .*:	d51b9e60 	msr	pmovsset_el0, x0
 .*:	d53b9e60 	mrs	x0, pmovsset_el0
+.*:	d5380580 	mrs	x0, id_aa64afr0_el1
+.*:	d53805a0 	mrs	x0, id_aa64afr1_el1
+.*:	d5380500 	mrs	x0, id_aa64dfr0_el1
+.*:	d5380520 	mrs	x0, id_aa64dfr1_el1
+.*:	d5380540 	mrs	x0, id_aa64dfr2_el1
 .*:	d5380140 	mrs	x0, id_dfr0_el1
 .*:	d5380100 	mrs	x0, id_pfr0_el1
 .*:	d5380120 	mrs	x0, id_pfr1_el1
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.s b/gas/testsuite/gas/aarch64/sysreg/sysreg.s
index 9c0fd4ae2fd..cf0461412b5 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg.s
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.s
@@ -5,6 +5,11 @@
 	rw_sys_reg sys_reg=pmovsclr_el0
 	rw_sys_reg sys_reg=pmovsset_el0
 
+	rw_sys_reg sys_reg=id_aa64afr0_el1 w=0
+	rw_sys_reg sys_reg=id_aa64afr1_el1 w=0
+	rw_sys_reg sys_reg=id_aa64dfr0_el1 w=0
+	rw_sys_reg sys_reg=id_aa64dfr1_el1 w=0
+	rw_sys_reg sys_reg=id_aa64dfr2_el1 w=0
 	rw_sys_reg sys_reg=id_dfr0_el1 w=0
 	rw_sys_reg sys_reg=id_pfr0_el1 w=0
 	rw_sys_reg sys_reg=id_pfr1_el1 w=0
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index cd2f1ac8516..6a554d9a12a 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -519,6 +519,7 @@
   SYSREG ("id_aa64afr1_el1",	CPENC (3,0,0,5,5),	F_REG_READ,		AARCH64_NO_FEATURES)
   SYSREG ("id_aa64dfr0_el1",	CPENC (3,0,0,5,0),	F_REG_READ,		AARCH64_NO_FEATURES)
   SYSREG ("id_aa64dfr1_el1",	CPENC (3,0,0,5,1),	F_REG_READ,		AARCH64_NO_FEATURES)
+  SYSREG ("id_aa64dfr2_el1",	CPENC (3,0,0,5,2),	F_REG_READ,		AARCH64_NO_FEATURES)
   SYSREG ("id_aa64isar0_el1",	CPENC (3,0,0,6,0),	F_REG_READ,		AARCH64_NO_FEATURES)
   SYSREG ("id_aa64isar1_el1",	CPENC (3,0,0,6,1),	F_REG_READ,		AARCH64_NO_FEATURES)
   SYSREG ("id_aa64isar2_el1",	CPENC (3,0,0,6,2),	F_REG_READ,		AARCH64_NO_FEATURES)

Re: [PATCH v1 0/4] aarch64: add new Armv9.5-A features and their associated registers (RAS, Debug, Performance Monitor)

[Richard Earnshaw (lists)]

On 04/07/2024 15:23, Matthieu Longo wrote:
> Hi,
> 
> [patch 0/4] aarch64: aarch64: add new Armv9.5-A features and their associated registers (RAS, Debug, Performance Monitor)
>     [patch v1 1/4] aarch64: add E3DSE feature and its associated registers
>     [patch v1 2/4] aarch64: add SPMU2 feature and its associated registers
>     [patch v1 3/4] aarch64: add STEP2 feature and its associated registers
>     [patch v1 4/4] aarch64: add Debug Feature Register 2 (ID_AA64DFR2_EL1)
> 
> AArch64 defines new registers for Armv9.5-A architecture.
> This patch series adds the following features and their associated system registers:
> - e3dse (Delegated SError exceptions for EL3)
> - fpmu2 (System Performance Monitors Extension version 2)
> - step2 (Enhanced Software Step Extension)
> - ID_AA64DFR2_EL1 (Debug Feature Register 2)
> 
> Each patch also adds relevant tests.
> Regression tested on aarch64-none-elf, and no regression found.
> 
> Ok for binutils-master?

OK, thanks

R.

> 
> Regards,
> Matthieu.
> 
> Link to V0 posting: https://sourceware.org/pipermail/binutils/2024-June/135226.html
> 
> Revision 1:
> - Split id_aa64dfr2_el1 from the registers for STEP2 feature.
> - Add test for id_aa64dfr2_el1 and its friends.   
> 
> 
> Matthieu Longo (4):
>   aarch64: add E3DSE feature and its associated registers
>   aarch64: add SPMU2 feature and its associated registers
>   aarch64: add STEP2 feature and its associated registers
>   aarch64: add Debug Feature Register 2 (ID_AA64DFR2_EL1)
> 
>  .../armv9_5-a-sysregs-archv9_4-unsupported.d    |  3 +++
>  .../armv9_5-a-sysregs-archv9_4-unsupported.l    | 17 +++++++++++++++++
>  .../gas/aarch64/sysreg/armv9_5-a-sysregs.d      | 17 +++++++++++++++++
>  .../gas/aarch64/sysreg/armv9_5-a-sysregs.s      | 13 +++++++++++++
>  gas/testsuite/gas/aarch64/sysreg/sysreg.d       |  5 +++++
>  gas/testsuite/gas/aarch64/sysreg/sysreg.s       |  5 +++++
>  include/opcode/aarch64.h                        | 12 +++++++++++-
>  opcodes/aarch64-sys-regs.def                    |  5 +++++
>  8 files changed, 76 insertions(+), 1 deletion(-)
>  create mode 100644 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.d
>  create mode 100644 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
>  create mode 100644 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
>  create mode 100644 gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s
>