* [PATCH v1 0/6] Binutils] aarch64: Add support for sme2p1 instructions.
@ 2024-07-08 15:36 Srinath Parvathaneni
2024-07-08 15:36 ` [PATCH v1 1/6] aarch64: Add support for sme2.1 luti2 and luti4 instructions Srinath Parvathaneni
` (6 more replies)
0 siblings, 7 replies; 10+ messages in thread
From: Srinath Parvathaneni @ 2024-07-08 15:36 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
Hi,
This patch series adds the support for aarch64 sme2p1 instructions
and the spec can be found here [1].
Srinath Parvathaneni (6):
aarch64: Add support for sme2.1 luti2 and luti4 instructions.
aarch64: Add support for sme2.1 luti2 and luti4 instructions (regenerated files).
aarch64: Add support for sme2.1 movaz instructions.
aarch64: Add support for sme2.1 movaz instructions (regenerated files).
aarch64: Add support for sme2.1 zero instructions.
aarch64: Add support for sme2.1 zero instructions (regenerated files).
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
Ok for binutils-master?
Regards,
Srinath.
gas/config/tc-aarch64.c | 1 +
gas/testsuite/gas/aarch64/sme-4-illegal.l | 2 +-
gas/testsuite/gas/aarch64/sme2p1-2-bad.d | 4 +
gas/testsuite/gas/aarch64/sme2p1-2-bad.l | 62 ++
gas/testsuite/gas/aarch64/sme2p1-2-bad.s | 48 ++
gas/testsuite/gas/aarch64/sme2p1-2.d | 87 +++
gas/testsuite/gas/aarch64/sme2p1-2.s | 87 +++
gas/testsuite/gas/aarch64/sme2p1-3-bad.d | 4 +
gas/testsuite/gas/aarch64/sme2p1-3-bad.l | 30 +
gas/testsuite/gas/aarch64/sme2p1-3-bad.s | 20 +
gas/testsuite/gas/aarch64/sme2p1-3.d | 26 +
gas/testsuite/gas/aarch64/sme2p1-3.s | 19 +
gas/testsuite/gas/aarch64/sme2p1-4-bad.d | 4 +
gas/testsuite/gas/aarch64/sme2p1-4-bad.l | 76 +++
gas/testsuite/gas/aarch64/sme2p1-4-bad.s | 48 ++
gas/testsuite/gas/aarch64/sme2p1-4.d | 53 ++
gas/testsuite/gas/aarch64/sme2p1-4.s | 48 ++
gas/testsuite/gas/aarch64/sme2p1-5-bad.d | 4 +
gas/testsuite/gas/aarch64/sme2p1-5-bad.l | 103 +++
gas/testsuite/gas/aarch64/sme2p1-5-bad.s | 54 ++
gas/testsuite/gas/aarch64/sme2p1-5.d | 54 ++
gas/testsuite/gas/aarch64/sme2p1-5.s | 54 ++
include/opcode/aarch64.h | 13 +-
opcodes/aarch64-asm-2.c | 94 +--
opcodes/aarch64-asm.c | 47 ++
opcodes/aarch64-asm.h | 1 +
opcodes/aarch64-dis-2.c | 753 ++++++++++++++--------
opcodes/aarch64-dis.c | 55 ++
opcodes/aarch64-dis.h | 1 +
opcodes/aarch64-opc-2.c | 1 +
opcodes/aarch64-opc.c | 71 +-
opcodes/aarch64-opc.h | 4 +
opcodes/aarch64-tbl.h | 47 ++
33 files changed, 1634 insertions(+), 341 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-2-bad.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-2-bad.l
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-2-bad.s
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-2.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-2.s
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.l
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.s
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3.s
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-4-bad.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-4-bad.l
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-4-bad.s
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-4.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-4.s
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-5-bad.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-5-bad.l
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-5-bad.s
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-5.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-5.s
--
2.25.1
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v1 1/6] aarch64: Add support for sme2.1 luti2 and luti4 instructions.
2024-07-08 15:36 [PATCH v1 0/6] Binutils] aarch64: Add support for sme2p1 instructions Srinath Parvathaneni
@ 2024-07-08 15:36 ` Srinath Parvathaneni
2024-07-08 15:36 ` [PATCH v1 2/6] aarch64: Add support for sme2.1 luti2 and luti4 instructions (regenerated files) Srinath Parvathaneni
` (5 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Srinath Parvathaneni @ 2024-07-08 15:36 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 1187 bytes --]
This patch adds support for following sme2.1 luti2 and luti4 instructions, spec is
available here [1]
1. LUTI2 (two registers) strided.
2. LUTI2 (four registers) strided.
3. LUTI4 (two registers) strided.
4. LUTI4 (four registers) strided.
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en
---
gas/testsuite/gas/aarch64/sme2p1-2-bad.d | 4 ++
gas/testsuite/gas/aarch64/sme2p1-2-bad.l | 62 +++++++++++++++++
gas/testsuite/gas/aarch64/sme2p1-2-bad.s | 48 +++++++++++++
gas/testsuite/gas/aarch64/sme2p1-2.d | 87 ++++++++++++++++++++++++
gas/testsuite/gas/aarch64/sme2p1-2.s | 87 ++++++++++++++++++++++++
include/opcode/aarch64.h | 1 +
opcodes/aarch64-asm.c | 4 ++
opcodes/aarch64-dis.c | 6 ++
opcodes/aarch64-tbl.h | 10 +++
9 files changed, 309 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-2-bad.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-2-bad.l
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-2-bad.s
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-2.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-2.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0001-aarch64-Add-support-for-sme2.1-luti2-and-luti4-in.patch --]
[-- Type: text/x-patch; name="v1-0001-aarch64-Add-support-for-sme2.1-luti2-and-luti4-in.patch", Size: 19325 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-2-bad.d b/gas/testsuite/gas/aarch64/sme2p1-2-bad.d
new file mode 100644
index 00000000000..f165f1f960a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-2-bad.d
@@ -0,0 +1,4 @@
+#name: Negative test of SME2.1 luti2 and luti4 instructions.
+#as: -march=armv9.4-a+sme2p1
+#source: sme2p1-2-bad.s
+#error_output: sme2p1-2-bad.l
diff --git a/gas/testsuite/gas/aarch64/sme2p1-2-bad.l b/gas/testsuite/gas/aarch64/sme2p1-2-bad.l
new file mode 100644
index 00000000000..8fd4039f37e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-2-bad.l
@@ -0,0 +1,62 @@
+.*: Assembler messages:
+.*: Error: the register list must have a stride of 1 or 8 at operand 1 -- `luti2 {z0.b,z7.b},zt0,z0\[0\]`
+.*: Error: the register list must have a stride of 1 at operand 1 -- `luti2 {Z0.s,Z8.s},ZT0,Z0\[0\]'
+.*: Error: operand mismatch -- `luti2 {z7.d,z15.d},zt0,z0\[0\]'
+.*: Info: did you mean this\?
+.*: Info: luti2 {z7.b, z15.b}, zt0, z0\[0\]
+.*: Info: other valid variant\(s\):
+.*: Info: luti2 {z7.h, z15.h}, zt0, z0\[0\]
+.*: Info: luti2 {z7.s, z15.s}, zt0, z0\[0\]
+.*: Error: operand 3 must be an indexed SVE vector register -- `luti2 {z16.b,z24.b},zt0,z0'
+.*: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 {z23.b,z31.b},zt0,z0\[8\]'
+.*: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 {z0.b,z8.b},zt0,z31\[15\]'
+.*: Error: unexpected register type at operand 2 -- `luti2 {z0.b,z8.b},z0\[7\]'
+.*: Error: the register list must have a stride of 1 or 8 at operand 1 -- `luti2 {z8.b,z24.b},zt0,z31\[0\]`
+.*: Error: invalid register list at operand 1 -- `luti2 {z24.b,z24.b},zt0,z0\[7\]'
+.*: Error: the register list must have a stride of 1 or 8 at operand 1 -- `luti2 {z4.h,z16.h},zt0,z20\[4\]`
+.*: Error: the register list must have a stride of 1 or 8 at operand 1 -- `luti2 {z20.h,z22.h},zt0,z12\[2\]`
+.*: Error: invalid register list at operand 1 -- `luti2 {z0.b,z3.b,z18.b,z1.b},zt0,z0\[0\]'
+.*: Error: the register list must have a stride of 1 at operand 1 -- `luti2 {Z0.s,Z4.s,Z8.s,Z12.s},ZT0,Z0\[0\]'
+.*: Error: operand mismatch -- `luti2 {z3.d,z7.d,z11.d,z15.d},zt0,z0\[0\]'
+.*: Info: did you mean this\?
+.*: Info: luti2 {z3.b, z7.b, z11.b, z15.b}, zt0, z0\[0\]
+.*: Info: other valid variant\(s\):
+.*: Info: luti2 {z3.h, z7.h, z11.h, z15.h}, zt0, z0\[0\]
+.*: Info: luti2 {z3.s, z7.s, z11.s, z15.s}, zt0, z0\[0\]
+.*: Error: operand 3 must be an indexed SVE vector register -- `luti2 {z16.h,z20.h,z24.h,z28.h},zt0,z0'
+.*: Error: register element index out of range 0 to 3 at operand 3 -- `luti2 {z19.h,z23.h,z27.h,z31.h},zt0,z0\[5\]'
+.*: Error: start register out of range at operand 1 -- `luti2 {z10.b,z14.b,z18.b,z22.b},zt0,z31\[0\]'
+.*: Error: invalid register list at operand 1 -- `luti2 {z20.b,z24.b,z28.b,z30.b},z0\[3\]'
+.*: Error: invalid register list at operand 1 -- `luti2 {z4.b,z7.b,z11.b,z18.b},zt0,z31\[0\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `luti2 {z6.b,z0.s,z2.d,z28.h},zt0,z0\[7\]'
+.*: Error: the register list must have a stride of 1 or 8 at operand 1 -- `luti4 {z0.b,z7.b},zt0,z0\[0\]`
+.*: Error: the register list must have a stride of 1 at operand 1 -- `luti2 {Z0.s,Z8.s},ZT0,Z0\[0\]'
+.*: Error: operand mismatch -- `luti4 {z7.d,z15.d},zt0,z0\[0\]'
+.*: Info: did you mean this\?
+.*: Info: luti4 {z7.b, z15.b}, zt0, z0\[0\]
+.*: Info: other valid variant\(s\):
+.*: Info: luti4 {z7.h, z15.h}, zt0, z0\[0\]
+.*: Info: luti4 {z7.s, z15.s}, zt0, z0\[0\]
+.*: Error: missing braces at operand 3 -- `luti4 {z16.b,z24.b},zt0,z0'
+.*: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 {z23.b,z31.b},zt0,z0\[8\]'
+.*: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 {z0.b,z8.b},zt0,z31\[15\]'
+.*: Error: unexpected register type at operand 2 -- `luti4 {z0.b,z8.b},z0\[7\]'
+.*: Error: the register list must have a stride of 1 or 8 at operand 1 -- `luti4 {z8.b,z24.b},zt0,z31\[0\]`
+.*: Error: invalid register list at operand 1 -- `luti4 {z24.b,z24.b},zt0,z0\[7\]'
+.*: Error: the register list must have a stride of 1 or 8 at operand 1 -- `luti4 {z4.h,z16.h},zt0,z20\[4\]`
+.*: Error: the register list must have a stride of 1 or 8 at operand 1 -- `luti4 {z20.h,z22.h},zt0,z12\[2\]`
+.*: Error: the register list must have a stride of 1 at operand 1 -- `luti4 {z0.s,z4.s,z8.s,z12.s},zt0,z0\[0\]'
+.*: Error: invalid register list at operand 1 -- `luti4 {z0.b,z3.b,z18.b,z1.b},zt0,z0\[0\]'
+.*: Error: the register list must have a stride of 1 at operand 1 -- `luti2 {Z0.s,Z4.s,Z8.s,Z12.s},ZT0,Z0\[0\]'
+.*: Error: operand mismatch -- `luti4 {z3.d,z7.d,z11.d,z15.d},zt0,z0\[0\]'
+.*: Info: did you mean this\?
+.*: Info: luti4 {z3.b, z7.b, z11.b, z15.b}, zt0, z0\[0\]
+.*: Info: other valid variant\(s\):
+.*: Info: luti4 {z3.h, z7.h, z11.h, z15.h}, zt0, z0\[0\]
+.*: Info: luti4 {z3.s, z7.s, z11.s, z15.s}, zt0, z0\[0\]
+.*: Error: missing braces at operand 3 -- `luti4 {z16.h,z20.h,z24.h,z28.h},zt0,z0'
+.*: Error: register element index out of range 0 to 1 at operand 3 -- `luti4 {z19.h,z23.h,z27.h,z31.h},zt0,z0\[5\]'
+.*: Error: expected a list of 2 registers at operand 1 -- `luti4 {z10.b,z14.b,z18.b,z22.b},zt0,z31\[0\]'
+.*: Error: invalid register list at operand 1 -- `luti4 {z20.b,z24.b,z28.b,z30.b},z0\[3\]'
+.*: Error: invalid register list at operand 1 -- `luti4 {z4.b,z7.b,z11.b,z18.b},zt0,z31\[0\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `luti4 {z6.b,z0.s,z2.d,z28.h},zt0,z0\[7\]'
diff --git a/gas/testsuite/gas/aarch64/sme2p1-2-bad.s b/gas/testsuite/gas/aarch64/sme2p1-2-bad.s
new file mode 100644
index 00000000000..52af11f4ead
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-2-bad.s
@@ -0,0 +1,48 @@
+/* LUTI2 (two registers) strided. */
+luti2 { z0.b , z7.b }, zt0, z0[0]
+LUTI2 { Z0.s , Z8.s }, ZT0, Z0[0]
+luti2 { z7.d , z15.d }, zt0, z0[0]
+luti2 { z16.b , z24.b }, zt0, z0
+luti2 { z23.b , z31.b }, zt0, z0[8]
+luti2 { z0.b , z8.b }, zt0, z31[15]
+luti2 { z0.b , z8.b }, z0[7]
+luti2 { z8.b , z24.b }, zt0, z31[0]
+luti2 { z24.b , z24.b }, zt0, z0[7]
+luti2 { z4.h , z16.h }, zt0, z20[4]
+luti2 { z20.h , z22.h }, zt0, z12[2]
+
+/* LUTI2 (four registers) strided. */
+luti2 { z0.b , z3.b , z18.b , z1.b }, zt0, z0[0]
+LUTI2 { Z0.s , Z4.s, Z8.s , Z12.s }, ZT0, Z0[0]
+luti2 { z3.d , z7.d, z11.d, z15.d }, zt0, z0[0]
+luti2 { z16.h , z20.h , z24.h , z28.h }, zt0, z0
+luti2 { z19.h , z23.h , z27.h , z31.h }, zt0, z0[5]
+luti2 { z10.b , z14.b , z18.b , z22.b }, zt0, z31[0]
+luti2 { z20.b , z24.b , z28.b , z30.b }, z0[3]
+luti2 { z4.b , z7.b , z11.b , z18.b }, zt0, z31[0]
+luti2 { z6.b , z0.s , z2.d , z28.h }, zt0, z0[7]
+
+/* LUTI4 (two registers) strided. */
+luti4 { z0.b , z7.b }, zt0, z0[0]
+LUTI2 { Z0.s , Z8.s }, ZT0, Z0[0]
+luti4 { z7.d , z15.d }, zt0, z0[0]
+luti4 { z16.b , z24.b }, zt0, z0
+luti4 { z23.b , z31.b }, zt0, z0[8]
+luti4 { z0.b , z8.b }, zt0, z31[15]
+luti4 { z0.b , z8.b }, z0[7]
+luti4 { z8.b , z24.b }, zt0, z31[0]
+luti4 { z24.b , z24.b }, zt0, z0[7]
+luti4 { z4.h , z16.h }, zt0, z20[4]
+luti4 { z20.h , z22.h }, zt0, z12[2]
+
+/* LUTI4 (four registers) strided. */
+luti4 { z0.s , z4.s , z8.s , z12.s }, zt0, z0[0]
+luti4 { z0.b , z3.b , z18.b , z1.b }, zt0, z0[0]
+LUTI2 { Z0.s , Z4.s, Z8.s , Z12.s }, ZT0, Z0[0]
+luti4 { z3.d , z7.d, z11.d, z15.d }, zt0, z0[0]
+luti4 { z16.h , z20.h , z24.h , z28.h }, zt0, z0
+luti4 { z19.h , z23.h , z27.h , z31.h }, zt0, z0[5]
+luti4 { z10.b , z14.b , z18.b , z22.b }, zt0, z31[0]
+luti4 { z20.b , z24.b , z28.b , z30.b }, z0[3]
+luti4 { z4.b , z7.b , z11.b , z18.b }, zt0, z31[0]
+luti4 { z6.b , z0.s , z2.d , z28.h }, zt0, z0[7]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-2.d b/gas/testsuite/gas/aarch64/sme2p1-2.d
new file mode 100644
index 00000000000..8be6db0d34f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-2.d
@@ -0,0 +1,87 @@
+#name: Test of SME2.1 luti2 and luti4 instructions.
+#as: -march=armv9.4-a+sme2p1
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: c09c4000 luti2 {z0.b, z8.b}, zt0, z0\[0\]
+.*: c09c4000 luti2 {z0.b, z8.b}, zt0, z0\[0\]
+.*: c09c4007 luti2 {z7.b, z15.b}, zt0, z0\[0\]
+.*: c09c4010 luti2 {z16.b, z24.b}, zt0, z0\[0\]
+.*: c09c4017 luti2 {z23.b, z31.b}, zt0, z0\[0\]
+.*: c09c43e0 luti2 {z0.b, z8.b}, zt0, z31\[0\]
+.*: c09fc000 luti2 {z0.b, z8.b}, zt0, z0\[7\]
+.*: c09c43f0 luti2 {z16.b, z24.b}, zt0, z31\[0\]
+.*: c09fc010 luti2 {z16.b, z24.b}, zt0, z0\[7\]
+.*: c09e4284 luti2 {z4.b, z12.b}, zt0, z20\[4\]
+.*: c09d4194 luti2 {z20.b, z28.b}, zt0, z12\[2\]
+.*: c09c5000 luti2 {z0.h, z8.h}, zt0, z0\[0\]
+.*: c09c5000 luti2 {z0.h, z8.h}, zt0, z0\[0\]
+.*: c09c5007 luti2 {z7.h, z15.h}, zt0, z0\[0\]
+.*: c09c5010 luti2 {z16.h, z24.h}, zt0, z0\[0\]
+.*: c09c5017 luti2 {z23.h, z31.h}, zt0, z0\[0\]
+.*: c09c53e0 luti2 {z0.h, z8.h}, zt0, z31\[0\]
+.*: c09fd000 luti2 {z0.h, z8.h}, zt0, z0\[7\]
+.*: c09c53f0 luti2 {z16.h, z24.h}, zt0, z31\[0\]
+.*: c09fd010 luti2 {z16.h, z24.h}, zt0, z0\[7\]
+.*: c09e5284 luti2 {z4.h, z12.h}, zt0, z20\[4\]
+.*: c09d5194 luti2 {z20.h, z28.h}, zt0, z12\[2\]
+.*: c09c8000 luti2 {z0.b, z4.b, z8.b, z12.b}, zt0, z0\[0\]
+.*: c09c8000 luti2 {z0.b, z4.b, z8.b, z12.b}, zt0, z0\[0\]
+.*: c09c8003 luti2 {z3.b, z7.b, z11.b, z15.b}, zt0, z0\[0\]
+.*: c09c8010 luti2 {z16.b, z20.b, z24.b, z28.b}, zt0, z0\[0\]
+.*: c09c8013 luti2 {z19.b, z23.b, z27.b, z31.b}, zt0, z0\[0\]
+.*: c09c83e0 luti2 {z0.b, z4.b, z8.b, z12.b}, zt0, z31\[0\]
+.*: c09f8000 luti2 {z0.b, z4.b, z8.b, z12.b}, zt0, z0\[3\]
+.*: c09c83f0 luti2 {z16.b, z20.b, z24.b, z28.b}, zt0, z31\[0\]
+.*: c09f8010 luti2 {z16.b, z20.b, z24.b, z28.b}, zt0, z0\[3\]
+.*: c09d8282 luti2 {z2.b, z6.b, z10.b, z14.b}, zt0, z20\[1\]
+.*: c09e8151 luti2 {z17.b, z21.b, z25.b, z29.b}, zt0, z10\[2\]
+.*: c09c9000 luti2 {z0.h, z4.h, z8.h, z12.h}, zt0, z0\[0\]
+.*: c09c9000 luti2 {z0.h, z4.h, z8.h, z12.h}, zt0, z0\[0\]
+.*: c09c9003 luti2 {z3.h, z7.h, z11.h, z15.h}, zt0, z0\[0\]
+.*: c09c9010 luti2 {z16.h, z20.h, z24.h, z28.h}, zt0, z0\[0\]
+.*: c09c9013 luti2 {z19.h, z23.h, z27.h, z31.h}, zt0, z0\[0\]
+.*: c09c93e0 luti2 {z0.h, z4.h, z8.h, z12.h}, zt0, z31\[0\]
+.*: c09f9000 luti2 {z0.h, z4.h, z8.h, z12.h}, zt0, z0\[3\]
+.*: c09c93f0 luti2 {z16.h, z20.h, z24.h, z28.h}, zt0, z31\[0\]
+.*: c09f9010 luti2 {z16.h, z20.h, z24.h, z28.h}, zt0, z0\[3\]
+.*: c09d9282 luti2 {z2.h, z6.h, z10.h, z14.h}, zt0, z20\[1\]
+.*: c09e9151 luti2 {z17.h, z21.h, z25.h, z29.h}, zt0, z10\[2\]
+.*: c09a4000 luti4 {z0.b, z8.b}, zt0, z0\[0\]
+.*: c09a4000 luti4 {z0.b, z8.b}, zt0, z0\[0\]
+.*: c09a4007 luti4 {z7.b, z15.b}, zt0, z0\[0\]
+.*: c09a4010 luti4 {z16.b, z24.b}, zt0, z0\[0\]
+.*: c09a4017 luti4 {z23.b, z31.b}, zt0, z0\[0\]
+.*: c09a43e0 luti4 {z0.b, z8.b}, zt0, z31\[0\]
+.*: c09bc000 luti4 {z0.b, z8.b}, zt0, z0\[3\]
+.*: c09a43f0 luti4 {z16.b, z24.b}, zt0, z31\[0\]
+.*: c09bc010 luti4 {z16.b, z24.b}, zt0, z0\[3\]
+.*: c09ac284 luti4 {z4.b, z12.b}, zt0, z20\[1\]
+.*: c09b4194 luti4 {z20.b, z28.b}, zt0, z12\[2\]
+.*: c09a5000 luti4 {z0.h, z8.h}, zt0, z0\[0\]
+.*: c09a5000 luti4 {z0.h, z8.h}, zt0, z0\[0\]
+.*: c09a5007 luti4 {z7.h, z15.h}, zt0, z0\[0\]
+.*: c09a5010 luti4 {z16.h, z24.h}, zt0, z0\[0\]
+.*: c09a5017 luti4 {z23.h, z31.h}, zt0, z0\[0\]
+.*: c09a53e0 luti4 {z0.h, z8.h}, zt0, z31\[0\]
+.*: c09bd000 luti4 {z0.h, z8.h}, zt0, z0\[3\]
+.*: c09a53f0 luti4 {z16.h, z24.h}, zt0, z31\[0\]
+.*: c09bd010 luti4 {z16.h, z24.h}, zt0, z0\[3\]
+.*: c09ad284 luti4 {z4.h, z12.h}, zt0, z20\[1\]
+.*: c09b5194 luti4 {z20.h, z28.h}, zt0, z12\[2\]
+.*: c09a9000 luti4 {z0.h, z4.h, z8.h, z12.h}, zt0, z0\[0\]
+.*: c09a9000 luti4 {z0.h, z4.h, z8.h, z12.h}, zt0, z0\[0\]
+.*: c09a9003 luti4 {z3.h, z7.h, z11.h, z15.h}, zt0, z0\[0\]
+.*: c09a9010 luti4 {z16.h, z20.h, z24.h, z28.h}, zt0, z0\[0\]
+.*: c09a9013 luti4 {z19.h, z23.h, z27.h, z31.h}, zt0, z0\[0\]
+.*: c09a93e0 luti4 {z0.h, z4.h, z8.h, z12.h}, zt0, z31\[0\]
+.*: c09b9000 luti4 {z0.h, z4.h, z8.h, z12.h}, zt0, z0\[1\]
+.*: c09a93f0 luti4 {z16.h, z20.h, z24.h, z28.h}, zt0, z31\[0\]
+.*: c09b9010 luti4 {z16.h, z20.h, z24.h, z28.h}, zt0, z0\[1\]
+.*: c09b9282 luti4 {z2.h, z6.h, z10.h, z14.h}, zt0, z20\[1\]
+.*: c09a9151 luti4 {z17.h, z21.h, z25.h, z29.h}, zt0, z10\[0\]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-2.s b/gas/testsuite/gas/aarch64/sme2p1-2.s
new file mode 100644
index 00000000000..a57baadf738
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-2.s
@@ -0,0 +1,87 @@
+/* LUTI2 (two registers) strided. */
+luti2 { z0.b , z8.b }, zt0, z0[0]
+LUTI2 { Z0.B , Z8.B }, ZT0, Z0[0]
+luti2 { z7.b , z15.b }, zt0, z0[0]
+luti2 { z16.b , z24.b }, zt0, z0[0]
+luti2 { z23.b , z31.b }, zt0, z0[0]
+luti2 { z0.b , z8.b }, zt0, z31[0]
+luti2 { z0.b , z8.b }, zt0, z0[7]
+luti2 { z16.b , z24.b }, zt0, z31[0]
+luti2 { z16.b , z24.b }, zt0, z0[7]
+luti2 { z4.b , z12.b }, zt0, z20[4]
+luti2 { z20.b , z28.b }, zt0, z12[2]
+
+luti2 { z0.h , z8.h }, zt0, z0[0]
+LUTI2 { Z0.H , Z8.H }, ZT0, Z0[0]
+luti2 { z7.h , z15.h }, zt0, z0[0]
+luti2 { z16.h , z24.h }, zt0, z0[0]
+luti2 { z23.h , z31.h }, zt0, z0[0]
+luti2 { z0.h , z8.h }, zt0, z31[0]
+luti2 { z0.h , z8.h }, zt0, z0[7]
+luti2 { z16.h , z24.h }, zt0, z31[0]
+luti2 { z16.h , z24.h }, zt0, z0[7]
+luti2 { z4.h , z12.h }, zt0, z20[4]
+luti2 { z20.h , z28.h }, zt0, z12[2]
+
+/* LUTI2 (four registers) strided. */
+luti2 { z0.b , z4.b , z8.b , z12.b }, zt0, z0[0]
+LUTI2 { Z0.B , Z4.B, Z8.B , Z12.B }, ZT0, Z0[0]
+luti2 { z3.b , z7.b, z11.b, z15.b }, zt0, z0[0]
+luti2 { z16.b , z20.b , z24.b , z28.b }, zt0, z0[0]
+luti2 { z19.b , z23.b , z27.b , z31.b }, zt0, z0[0]
+luti2 { z0.b , z4.b , z8.b , z12.b }, zt0, z31[0]
+luti2 { z0.b , z4.b , z8.b , z12.b }, zt0, z0[3]
+luti2 { z16.b , z20.b , z24.b , z28.b }, zt0, z31[0]
+luti2 { z16.b , z20.b , z24.b , z28.b }, zt0, z0[3]
+luti2 { z2.b , z6.b, z10.b , z14.b }, zt0, z20[1]
+luti2 { z17.b , z21.b, z25.b , z29.b }, zt0, z10[2]
+
+luti2 { z0.h , z4.h , z8.h , z12.h }, zt0, z0[0]
+LUTI2 { Z0.H , Z4.H, Z8.H , Z12.H }, ZT0, Z0[0]
+luti2 { z3.h , z7.h, z11.h, z15.h }, zt0, z0[0]
+luti2 { z16.h , z20.h , z24.h , z28.h }, zt0, z0[0]
+luti2 { z19.h , z23.h , z27.h , z31.h }, zt0, z0[0]
+luti2 { z0.h , z4.h , z8.h , z12.h }, zt0, z31[0]
+luti2 { z0.h , z4.h , z8.h , z12.h }, zt0, z0[3]
+luti2 { z16.h , z20.h , z24.h , z28.h }, zt0, z31[0]
+luti2 { z16.h , z20.h , z24.h , z28.h }, zt0, z0[3]
+luti2 { z2.h , z6.h, z10.h , z14.h }, zt0, z20[1]
+luti2 { z17.h , z21.h, z25.h , z29.h }, zt0, z10[2]
+
+/* LUTI4 (two registers) strided. */
+luti4 { z0.b , z8.b }, zt0, z0[0]
+LUTI4 { Z0.B , Z8.B }, ZT0, Z0[0]
+luti4 { z7.b , z15.b }, zt0, z0[0]
+luti4 { z16.b , z24.b }, zt0, z0[0]
+luti4 { z23.b , z31.b }, zt0, z0[0]
+luti4 { z0.b , z8.b }, zt0, z31[0]
+luti4 { z0.b , z8.b }, zt0, z0[3]
+luti4 { z16.b , z24.b }, zt0, z31[0]
+luti4 { z16.b , z24.b }, zt0, z0[3]
+luti4 { z4.b , z12.b }, zt0, z20[1]
+luti4 { z20.b , z28.b }, zt0, z12[2]
+
+luti4 { z0.h , z8.h }, zt0, z0[0]
+LUTI4 { Z0.H , Z8.H }, ZT0, Z0[0]
+luti4 { z7.h , z15.h }, zt0, z0[0]
+luti4 { z16.h , z24.h }, zt0, z0[0]
+luti4 { z23.h , z31.h }, zt0, z0[0]
+luti4 { z0.h , z8.h }, zt0, z31[0]
+luti4 { z0.h , z8.h }, zt0, z0[3]
+luti4 { z16.h , z24.h }, zt0, z31[0]
+luti4 { z16.h , z24.h }, zt0, z0[3]
+luti4 { z4.h , z12.h }, zt0, z20[1]
+luti4 { z20.h , z28.h }, zt0, z12[2]
+
+/* LUTI4 (four registers) strided. */
+luti4 { z0.h , z4.h , z8.h , z12.h }, zt0, z0[0]
+LUTI4 { Z0.H , Z4.H, Z8.H , Z12.H }, ZT0, Z0[0]
+luti4 { z3.h , z7.h, z11.h, z15.h }, zt0, z0[0]
+luti4 { z16.h , z20.h , z24.h , z28.h }, zt0, z0[0]
+luti4 { z19.h , z23.h , z27.h , z31.h }, zt0, z0[0]
+luti4 { z0.h , z4.h , z8.h , z12.h }, zt0, z31[0]
+luti4 { z0.h , z4.h , z8.h , z12.h }, zt0, z0[1]
+luti4 { z16.h , z20.h , z24.h , z28.h }, zt0, z31[0]
+luti4 { z16.h , z20.h , z24.h , z28.h }, zt0, z0[1]
+luti4 { z2.h , z6.h, z10.h , z14.h }, zt0, z20[1]
+luti4 { z17.h , z21.h, z25.h , z29.h }, zt0, z10[0]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index fc749fa280d..64959a8c50e 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1067,6 +1067,7 @@ enum aarch64_insn_class
sme_ldr,
sme_psel,
sme_shift,
+ sme_size_12_bh,
sme_size_12_bhs,
sme_size_12_hs,
sme_size_12_b,
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 0867c08940c..e621bd86e87 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -2139,6 +2139,10 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
/* The variant is encoded as part of the immediate. */
break;
+ case sme_size_12_bh:
+ insert_field (FLD_S, &inst->value, aarch64_get_variant (inst), 0);
+ break;
+
case sme_size_12_bhs:
case sme_size_12_b:
insert_field (FLD_SME_size_12, &inst->value,
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index d3f38c3cda5..81ebbe0bd55 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -3397,6 +3397,12 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
i = extract_field (FLD_SVE_tszh, inst->value, 0);
goto sve_shift;
+ case sme_size_12_bh:
+ variant = extract_field (FLD_S, inst->value, 0);
+ if (variant > 1)
+ return false;
+ break;
+
case sme_size_12_bhs:
variant = extract_field (FLD_SME_size_12, inst->value, 0);
if (variant >= 3)
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index ad0d8ae7be6..eccfac53ad1 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2084,6 +2084,11 @@
{ \
QLF3(S_B,NIL,NIL), \
}
+#define OP_SVE_VUU_BH \
+{ \
+ QLF3(S_B,NIL,NIL), \
+ QLF3(S_H,NIL,NIL), \
+}
#define OP_SVE_VUU_BHS \
{ \
QLF3(S_B,NIL,NIL), \
@@ -6641,6 +6646,11 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2p1_INSN ("movaz", 0xc0860200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrss_1), OP_SVE_SS, 0, 0),
SME2p1_INSN ("movaz", 0xc0c60200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsd_1), OP_SVE_DD, 0, 0),
+ SME2p1_INSN ("luti2", 0xc09c4000, 0xfffc4c08, sme_size_12_bh, 0, OP3 (SME_Ztx2_STRIDED, SME_ZT0, SME_Zn_INDEX3_15), OP_SVE_VUU_BH, 0, 0),
+ SME2p1_INSN ("luti2", 0xc09c8000, 0xfffccc0c, sme_size_12_bh, 0, OP3 (SME_Ztx4_STRIDED, SME_ZT0, SME_Zn_INDEX2_16), OP_SVE_VUU_BH, 0, 0),
+ SME2p1_INSN ("luti4", 0xc09a4000, 0xfffe4c08, sme_size_12_bh, 0, OP3 (SME_Ztx2_STRIDED, SME_ZT0, SME_Zn_INDEX2_15), OP_SVE_VUU_BH, 0, 0),
+ SME2p1_INSN ("luti4", 0xc09a9000, 0xfffefc0c, sme_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_ZT0, SME_Zn_INDEX1_16), OP_SVE_HUU, 0, 0),
+
/* SVE2p1 Instructions. */
SVE2p1_INSN("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
SVE2p1_INSN("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v1 2/6] aarch64: Add support for sme2.1 luti2 and luti4 instructions (regenerated files).
2024-07-08 15:36 [PATCH v1 0/6] Binutils] aarch64: Add support for sme2p1 instructions Srinath Parvathaneni
2024-07-08 15:36 ` [PATCH v1 1/6] aarch64: Add support for sme2.1 luti2 and luti4 instructions Srinath Parvathaneni
@ 2024-07-08 15:36 ` Srinath Parvathaneni
2024-07-08 15:36 ` [PATCH v1 3/6] aarch64: Add support for sme2.1 movaz instructions Srinath Parvathaneni
` (4 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Srinath Parvathaneni @ 2024-07-08 15:36 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 239 bytes --]
This patch includes the regenerated files for
aarch64: Add support for sme2.1 luti2 and luti4 instructions.
---
opcodes/aarch64-dis-2.c | 484 ++++++++++++++++++++++------------------
1 file changed, 264 insertions(+), 220 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0002-aarch64-Add-support-for-sme2.1-luti2-and-luti4-in.patch --]
[-- Type: text/x-patch; name="v1-0002-aarch64-Add-support-for-sme2.1-luti2-and-luti4-in.patch", Size: 130459 bytes --]
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 64407afaca4..36542af2dc4 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -216,7 +216,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3409;
+ return 3413;
}
else
{
@@ -247,11 +247,33 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000xx01101xxxxxxxxxxxxxxxxx
- luti4. */
- return 3410;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx01101x00xxxxxxxxxxxxxx
+ luti4. */
+ return 3414;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx01101x10xxxxxxxxxxxxxx
+ luti4. */
+ return 3309;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx01101xx1xxxxxxxxxxxxxx
+ luti4. */
+ return 3308;
+ }
}
}
}
@@ -327,64 +349,86 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 14) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000x00x11xxx0xx00xxxxxxxxxx
- luti2. */
- return 2668;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x00011xxx0xx00xxxxxxxxxx
+ luti2. */
+ return 2668;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x00011xxx1xx00xxxxxxxxxx
+ luti2. */
+ return 2667;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000x00x11xxx1xx00xxxxxxxxxx
- luti2. */
- return 2667;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x100000001001100xxxx00xxxxxxxxxx
+ movt. */
+ return 2689;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x100000001001110xxxx00xxxxxxxxxx
+ movt. */
+ return 2688;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000010011x1xxxx00xxxxxxxxxx
+ movt. */
+ return 3415;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000110011xxxxxx00xxxxxxxxxx
+ luti2. */
+ return 2666;
+ }
}
}
else
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- if (((word >> 16) & 0x1) == 0)
- {
- if (((word >> 17) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000010x1100xxxx00xxxxxxxxxx
- movt. */
- return 2689;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000010x1110xxxx00xxxxxxxxxx
- movt. */
- return 2688;
- }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000010x11x1xxxx00xxxxxxxxxx
- movt. */
- return 3411;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0111xxx0xx00xxxxxxxxxx
+ luti2. */
+ return 3307;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000000110x11xxxxxx00xxxxxxxxxx
+ x1000000xx0111xxx1xx00xxxxxxxxxx
luti2. */
- return 2666;
+ return 3306;
}
}
}
@@ -1157,7 +1201,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3477;
+ return 3481;
}
else
{
@@ -1165,7 +1209,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3476;
+ return 3480;
}
}
else
@@ -1513,7 +1557,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3470;
+ return 3474;
}
}
}
@@ -1543,7 +1587,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxxxxx1xxxxxx00xxxx
fdot. */
- return 3455;
+ return 3459;
}
}
else
@@ -1915,7 +1959,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3469;
+ return 3473;
}
}
}
@@ -2020,7 +2064,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3462;
+ return 3466;
}
}
}
@@ -2193,7 +2237,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3461;
+ return 3465;
}
}
}
@@ -2235,7 +2279,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3468;
+ return 3472;
}
else
{
@@ -2603,7 +2647,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3448;
+ return 3452;
}
else
{
@@ -2672,7 +2716,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3449;
+ return 3453;
}
else
{
@@ -2751,7 +2795,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3460;
+ return 3464;
}
else
{
@@ -2806,7 +2850,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3479;
+ return 3483;
}
else
{
@@ -2824,7 +2868,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3454;
+ return 3458;
}
}
}
@@ -2898,7 +2942,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3478;
+ return 3482;
}
}
}
@@ -2978,7 +3022,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3480;
+ return 3484;
}
else
{
@@ -3155,7 +3199,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3474;
+ return 3478;
}
else
{
@@ -3163,7 +3207,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3475;
+ return 3479;
}
}
}
@@ -3218,7 +3262,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3472;
+ return 3476;
}
else
{
@@ -3226,7 +3270,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3473;
+ return 3477;
}
}
}
@@ -3280,7 +3324,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3458;
+ return 3462;
}
else
{
@@ -3288,7 +3332,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3459;
+ return 3463;
}
}
}
@@ -3350,7 +3394,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3466;
+ return 3470;
}
else
{
@@ -3358,7 +3402,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3467;
+ return 3471;
}
}
}
@@ -3413,7 +3457,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3464;
+ return 3468;
}
else
{
@@ -3421,7 +3465,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3465;
+ return 3469;
}
}
}
@@ -3490,7 +3534,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3471;
+ return 3475;
}
}
else
@@ -3573,7 +3617,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3463;
+ return 3467;
}
}
else
@@ -3594,7 +3638,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx00xxx
fadd. */
- return 3412;
+ return 3416;
}
}
else
@@ -3613,7 +3657,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx00xxx
fadd. */
- return 3413;
+ return 3417;
}
}
}
@@ -3739,7 +3783,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3452;
+ return 3456;
}
else
{
@@ -3747,7 +3791,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx110xxx
fdot. */
- return 3453;
+ return 3457;
}
}
}
@@ -4038,7 +4082,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx01xxx
fdot. */
- return 3456;
+ return 3460;
}
else
{
@@ -4046,7 +4090,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx01xxx
fdot. */
- return 3457;
+ return 3461;
}
}
}
@@ -4317,7 +4361,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx01xxx
fsub. */
- return 3414;
+ return 3418;
}
}
else
@@ -4336,7 +4380,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx01xxx
fsub. */
- return 3415;
+ return 3419;
}
}
}
@@ -4398,7 +4442,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx11xxx
fdot. */
- return 3450;
+ return 3454;
}
else
{
@@ -4406,7 +4450,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx11xxx
fdot. */
- return 3451;
+ return 3455;
}
}
}
@@ -4941,7 +4985,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3386;
+ return 3390;
}
}
else
@@ -5089,7 +5133,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3383;
+ return 3387;
}
else
{
@@ -5097,7 +5141,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3378;
+ return 3382;
}
}
else
@@ -5106,7 +5150,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3384;
+ return 3388;
}
}
else
@@ -5157,7 +5201,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3385;
+ return 3389;
}
}
}
@@ -5240,7 +5284,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3379;
+ return 3383;
}
else
{
@@ -5248,7 +5292,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3380;
+ return 3384;
}
}
else
@@ -5259,7 +5303,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3374;
+ return 3378;
}
else
{
@@ -5267,7 +5311,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3375;
+ return 3379;
}
}
}
@@ -5302,7 +5346,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3381;
+ return 3385;
}
else
{
@@ -5310,7 +5354,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxx10111000xxxxxxxxx1
f2cvtl. */
- return 3382;
+ return 3386;
}
}
else
@@ -5321,7 +5365,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001011xxx10111000xxxxxxxxx1
bf1cvtl. */
- return 3376;
+ return 3380;
}
else
{
@@ -5329,7 +5373,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001111xxx10111000xxxxxxxxx1
bf2cvtl. */
- return 3377;
+ return 3381;
}
}
}
@@ -5598,7 +5642,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1100xx100xxxx0
fscale. */
- return 3388;
+ return 3392;
}
}
else
@@ -5774,7 +5818,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1010xx100xxxx0
fscale. */
- return 3387;
+ return 3391;
}
else
{
@@ -5782,7 +5826,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1110xx100xxxx0
fscale. */
- return 3389;
+ return 3393;
}
}
}
@@ -10950,7 +10994,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3390;
+ return 3394;
}
else
{
@@ -10958,7 +11002,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3391;
+ return 3395;
}
}
}
@@ -11876,7 +11920,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3392;
+ return 3396;
}
else
{
@@ -11884,7 +11928,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3393;
+ return 3397;
}
}
}
@@ -11969,7 +12013,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3394;
+ return 3398;
}
else
{
@@ -12076,7 +12120,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3396;
+ return 3400;
}
else
{
@@ -12281,7 +12325,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3395;
+ return 3399;
}
else
{
@@ -12322,7 +12366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3397;
+ return 3401;
}
else
{
@@ -13980,7 +14024,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3399;
+ return 3403;
}
}
else
@@ -14010,7 +14054,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3398;
+ return 3402;
}
}
}
@@ -14318,7 +14362,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx00x100001xxxxxxxxxxxxx
smaxqv. */
- return 3308;
+ return 3312;
}
else
{
@@ -14326,7 +14370,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx01x100001xxxxxxxxxxxxx
orqv. */
- return 3319;
+ return 3323;
}
}
else
@@ -14337,7 +14381,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x0101001xxxxxxxxxxxxx
addqv. */
- return 3306;
+ return 3310;
}
else
{
@@ -14347,7 +14391,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx001101001xxxxxxxxxxxxx
umaxqv. */
- return 3310;
+ return 3314;
}
else
{
@@ -14355,7 +14399,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011101001xxxxxxxxxxxxx
eorqv. */
- return 3312;
+ return 3316;
}
}
}
@@ -14392,7 +14436,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx00x110001xxxxxxxxxxxxx
sminqv. */
- return 3309;
+ return 3313;
}
else
{
@@ -14400,7 +14444,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx01x110001xxxxxxxxxxxxx
andqv. */
- return 3307;
+ return 3311;
}
}
}
@@ -14420,7 +14464,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0xx111001xxxxxxxxxxxxx
uminqv. */
- return 3311;
+ return 3315;
}
}
}
@@ -15164,7 +15208,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x0x00xxxxx101xxxxxxxxxxxxx
ld1q. */
- return 3335;
+ return 3339;
}
else
{
@@ -16178,7 +16222,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x00xxxxxxxxxx
zipq1. */
- return 3325;
+ return 3329;
}
else
{
@@ -16188,7 +16232,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111010xxxxxxxxxx
uzpq1. */
- return 3323;
+ return 3327;
}
else
{
@@ -16196,7 +16240,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111110xxxxxxxxxx
tblq. */
- return 3320;
+ return 3324;
}
}
}
@@ -16208,7 +16252,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x01xxxxxxxxxx
zipq2. */
- return 3326;
+ return 3330;
}
else
{
@@ -16216,7 +16260,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x11xxxxxxxxxx
uzpq2. */
- return 3324;
+ return 3328;
}
}
}
@@ -16696,7 +16740,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0x00xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3344;
+ return 3348;
}
else
{
@@ -16706,7 +16750,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0010xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3343;
+ return 3347;
}
else
{
@@ -16714,7 +16758,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0110xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3345;
+ return 3349;
}
}
}
@@ -17161,7 +17205,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0x0000101xxxxxxxxxxxxx
faddqv. */
- return 3313;
+ return 3317;
}
else
{
@@ -17178,7 +17222,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx100101xxxxxxxxxxxxx
fmaxnmqv. */
- return 3314;
+ return 3318;
}
}
else
@@ -17219,7 +17263,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx110101xxxxxxxxxxxxx
fmaxqv. */
- return 3315;
+ return 3319;
}
}
}
@@ -17241,7 +17285,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx101101xxxxxxxxxxxxx
fminnmqv. */
- return 3316;
+ return 3320;
}
}
else
@@ -17260,7 +17304,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx111101xxxxxxxxxxxxx
fminqv. */
- return 3317;
+ return 3321;
}
}
}
@@ -17380,7 +17424,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx01xxxx111xxxxxxxxxxxxx
ld2q. */
- return 3336;
+ return 3340;
}
}
}
@@ -17516,7 +17560,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx1xxxxx100xxxxxxxxxxxxx
ld2q. */
- return 3339;
+ return 3343;
}
}
else
@@ -17661,7 +17705,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x00x1xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3346;
+ return 3350;
}
}
else
@@ -17704,7 +17748,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0101xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3347;
+ return 3351;
}
}
else
@@ -17745,7 +17789,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0111xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3348;
+ return 3352;
}
}
}
@@ -17774,7 +17818,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3435;
+ return 3439;
}
}
else
@@ -17783,7 +17827,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3437;
+ return 3441;
}
}
else
@@ -17824,7 +17868,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3447;
+ return 3451;
}
}
else
@@ -17857,7 +17901,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3433;
+ return 3437;
}
}
else
@@ -17928,7 +17972,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3438;
+ return 3442;
}
}
else
@@ -17937,7 +17981,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3434;
+ return 3438;
}
}
else
@@ -17946,7 +17990,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3439;
+ return 3443;
}
}
else
@@ -17955,7 +17999,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3440;
+ return 3444;
}
}
else
@@ -17982,7 +18026,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3436;
+ return 3440;
}
}
else
@@ -18000,7 +18044,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3443;
+ return 3447;
}
}
else
@@ -18009,7 +18053,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3446;
+ return 3450;
}
}
else
@@ -18042,7 +18086,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3432;
+ return 3436;
}
}
else
@@ -18051,7 +18095,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3441;
+ return 3445;
}
}
else
@@ -18083,7 +18127,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3445;
+ return 3449;
}
}
else
@@ -18382,7 +18426,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0xx1xxxxx001xxxxxxxxxxxxx
st1q. */
- return 3342;
+ return 3346;
}
}
else
@@ -18397,7 +18441,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3442;
+ return 3446;
}
else
{
@@ -18405,7 +18449,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1011xxxxxxxxxxxx
fmlalltt. */
- return 3444;
+ return 3448;
}
}
else
@@ -19123,7 +19167,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001010x0001110xxxxxxxxxx
pmov. */
- return 3327;
+ return 3331;
}
else
{
@@ -19131,7 +19175,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001011x0001110xxxxxxxxxx
pmov. */
- return 3328;
+ return 3332;
}
}
else
@@ -19140,7 +19184,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x101101xx0001110xxxxxxxxxx
pmov. */
- return 3329;
+ return 3333;
}
}
else
@@ -19149,7 +19193,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x11x101xx0001110xxxxxxxxxx
pmov. */
- return 3330;
+ return 3334;
}
}
else
@@ -19195,7 +19239,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001x10x1001110xxxxxxxxxx
pmov. */
- return 3331;
+ return 3335;
}
else
{
@@ -19203,7 +19247,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001x11x1001110xxxxxxxxxx
pmov. */
- return 3332;
+ return 3336;
}
}
else
@@ -19212,7 +19256,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1011x1xx1001110xxxxxxxxxx
pmov. */
- return 3333;
+ return 3337;
}
}
else
@@ -19221,7 +19265,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x11x1x1xx1001110xxxxxxxxxx
pmov. */
- return 3334;
+ return 3338;
}
}
}
@@ -19240,7 +19284,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1x01xxxxx001001xxxxxxxxxx
dupq. */
- return 3318;
+ return 3322;
}
else
{
@@ -19248,7 +19292,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1x11xxxxx001001xxxxxxxxxx
extq. */
- return 3322;
+ return 3326;
}
}
else
@@ -19257,7 +19301,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1xx1xxxxx001101xxxxxxxxxx
tbxq. */
- return 3321;
+ return 3325;
}
}
else
@@ -20860,7 +20904,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101100xxxxxxxxxx
luti2. */
- return 3404;
+ return 3408;
}
}
else
@@ -20869,7 +20913,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x10xxxxxxxxxx
luti2. */
- return 3405;
+ return 3409;
}
}
else
@@ -20882,7 +20926,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101001xxxxxxxxxx
luti4. */
- return 3406;
+ return 3410;
}
else
{
@@ -20890,7 +20934,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101101xxxxxxxxxx
luti4. */
- return 3407;
+ return 3411;
}
}
else
@@ -20899,7 +20943,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x11xxxxxxxxxx
luti4. */
- return 3408;
+ return 3412;
}
}
}
@@ -21850,7 +21894,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x00xxxxxxxxxx
f1cvt. */
- return 3366;
+ return 3370;
}
else
{
@@ -21858,7 +21902,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x10xxxxxxxxxx
bf1cvt. */
- return 3362;
+ return 3366;
}
}
else
@@ -21869,7 +21913,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x01xxxxxxxxxx
f2cvt. */
- return 3367;
+ return 3371;
}
else
{
@@ -21877,7 +21921,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x11xxxxxxxxxx
bf2cvt. */
- return 3363;
+ return 3367;
}
}
}
@@ -21922,7 +21966,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x00xxxxxxxxxx
fcvtn. */
- return 3371;
+ return 3375;
}
else
{
@@ -21930,7 +21974,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x10xxxxxxxxxx
bfcvtn. */
- return 3370;
+ return 3374;
}
}
else
@@ -21941,7 +21985,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x01xxxxxxxxxx
fcvtnb. */
- return 3372;
+ return 3376;
}
else
{
@@ -21949,7 +21993,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x11xxxxxxxxxx
fcvtnt. */
- return 3373;
+ return 3377;
}
}
}
@@ -22010,7 +22054,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x00xxxxxxxxxx
f1cvtlt. */
- return 3368;
+ return 3372;
}
else
{
@@ -22018,7 +22062,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x10xxxxxxxxxx
bf1cvtlt. */
- return 3364;
+ return 3368;
}
}
else
@@ -22029,7 +22073,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x01xxxxxxxxxx
f2cvtlt. */
- return 3369;
+ return 3373;
}
else
{
@@ -22037,7 +22081,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x11xxxxxxxxxx
bf2cvtlt. */
- return 3365;
+ return 3369;
}
}
}
@@ -23363,7 +23407,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x01xxxx111xxxxxxxxxxxxx
ld3q. */
- return 3337;
+ return 3341;
}
else
{
@@ -23371,7 +23415,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x01xxxx111xxxxxxxxxxxxx
ld4q. */
- return 3338;
+ return 3342;
}
}
}
@@ -24544,7 +24588,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x1xxxxx100xxxxxxxxxxxxx
ld3q. */
- return 3340;
+ return 3344;
}
else
{
@@ -24552,7 +24596,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x1xxxxx100xxxxxxxxxxxxx
ld4q. */
- return 3341;
+ return 3345;
}
}
else
@@ -26617,7 +26661,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110100xxxxxxxx100xxxxxxxxxx
luti2. */
- return 3400;
+ return 3404;
}
}
}
@@ -26631,7 +26675,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxxxx000xxxxxxxxxx
luti4. */
- return 3402;
+ return 3406;
}
else
{
@@ -26639,7 +26683,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxxxx100xxxxxxxxxx
luti4. */
- return 3403;
+ return 3407;
}
}
else
@@ -26648,7 +26692,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110110xxxxxxxxx00xxxxxxxxxx
luti2. */
- return 3401;
+ return 3405;
}
}
}
@@ -26764,7 +26808,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx10001xxxxxxxxxx
fmlallbb. */
- return 3424;
+ return 3428;
}
else
{
@@ -26772,7 +26816,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx10001xxxxxxxxxx
fmlalltb. */
- return 3426;
+ return 3430;
}
}
else
@@ -26783,7 +26827,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x10xxxxxx10001xxxxxxxxxx
fmlallbt. */
- return 3425;
+ return 3429;
}
else
{
@@ -26791,7 +26835,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x10xxxxxx10001xxxxxxxxxx
fmlalltt. */
- return 3427;
+ return 3431;
}
}
}
@@ -26879,7 +26923,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3357;
+ return 3361;
}
else
{
@@ -26887,7 +26931,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx11101xxxxxxxxxx
fcvtn2. */
- return 3358;
+ return 3362;
}
}
else
@@ -26896,7 +26940,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x10xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3359;
+ return 3363;
}
}
}
@@ -27039,7 +27083,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x00xxxxxx11111xxxxxxxxxx
fdot. */
- return 3416;
+ return 3420;
}
else
{
@@ -27049,7 +27093,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxx11111xxxxxxxxxx
fdot. */
- return 3418;
+ return 3422;
}
else
{
@@ -27059,7 +27103,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110110xxxxxx11111xxxxxxxxxx
fmlalb. */
- return 3420;
+ return 3424;
}
else
{
@@ -27067,7 +27111,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110110xxxxxx11111xxxxxxxxxx
fmlalt. */
- return 3421;
+ return 3425;
}
}
}
@@ -27341,7 +27385,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx101110110xxxxx0x1111xxxxxxxxxx
fscale. */
- return 3360;
+ return 3364;
}
}
}
@@ -28733,7 +28777,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110001xxxx1011110xxxxxxxxxx
f1cvtl. */
- return 3353;
+ return 3357;
}
else
{
@@ -28741,7 +28785,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110001xxxx1011110xxxxxxxxxx
f1cvtl2. */
- return 3354;
+ return 3358;
}
}
else
@@ -28752,7 +28796,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110101xxxx1011110xxxxxxxxxx
bf1cvtl. */
- return 3349;
+ return 3353;
}
else
{
@@ -28760,7 +28804,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110101xxxx1011110xxxxxxxxxx
bf1cvtl2. */
- return 3350;
+ return 3354;
}
}
}
@@ -28774,7 +28818,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110011xxxx1011110xxxxxxxxxx
f2cvtl. */
- return 3355;
+ return 3359;
}
else
{
@@ -28782,7 +28826,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110011xxxx1011110xxxxxxxxxx
f2cvtl2. */
- return 3356;
+ return 3360;
}
}
else
@@ -28793,7 +28837,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110111xxxx1011110xxxxxxxxxx
bf2cvtl. */
- return 3351;
+ return 3355;
}
else
{
@@ -28801,7 +28845,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110111xxxx1011110xxxxxxxxxx
bf2cvtl2. */
- return 3352;
+ return 3356;
}
}
}
@@ -30800,7 +30844,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx1011101x1xxxxx111111xxxxxxxxxx
fscale. */
- return 3361;
+ return 3365;
}
}
}
@@ -32516,7 +32560,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111100xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3417;
+ return 3421;
}
else
{
@@ -32546,7 +32590,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111101xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3419;
+ return 3423;
}
else
{
@@ -32556,7 +32600,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x000111111xxxxxx0000x0xxxxxxxxxx
fmlalb. */
- return 3422;
+ return 3426;
}
else
{
@@ -32564,7 +32608,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x100111111xxxxxx0000x0xxxxxxxxxx
fmlalt. */
- return 3423;
+ return 3427;
}
}
}
@@ -33106,7 +33150,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010111100xxxxxx1000x0xxxxxxxxxx
fmlallbb. */
- return 3428;
+ return 3432;
}
else
{
@@ -33114,7 +33158,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x110111100xxxxxx1000x0xxxxxxxxxx
fmlalltb. */
- return 3430;
+ return 3434;
}
}
else
@@ -33145,7 +33189,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101111x1xxxxxx1000x0xxxxxxxxxx
fmlallbt. */
- return 3429;
+ return 3433;
}
else
{
@@ -33153,7 +33197,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101111x1xxxxxx1000x0xxxxxxxxxx
fmlalltt. */
- return 3431;
+ return 3435;
}
}
}
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v1 3/6] aarch64: Add support for sme2.1 movaz instructions.
2024-07-08 15:36 [PATCH v1 0/6] Binutils] aarch64: Add support for sme2p1 instructions Srinath Parvathaneni
2024-07-08 15:36 ` [PATCH v1 1/6] aarch64: Add support for sme2.1 luti2 and luti4 instructions Srinath Parvathaneni
2024-07-08 15:36 ` [PATCH v1 2/6] aarch64: Add support for sme2.1 luti2 and luti4 instructions (regenerated files) Srinath Parvathaneni
@ 2024-07-08 15:36 ` Srinath Parvathaneni
2024-07-15 6:14 ` Jan Beulich
2024-07-08 15:36 ` [PATCH v1 4/6] aarch64: Add support for sme2.1 movaz instructions (regenerated files) Srinath Parvathaneni
` (3 subsequent siblings)
6 siblings, 1 reply; 10+ messages in thread
From: Srinath Parvathaneni @ 2024-07-08 15:36 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 2025 bytes --]
This patch adds support for following sme2.1 movaz instructions and
the spec is available here [1].
1. MOVAZ (array to vector, two registers).
2. MOVAZ (array to vector, four registers).
3. MOVAZ (tile to vector, single).
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en
---
gas/config/tc-aarch64.c | 1 +
gas/testsuite/gas/aarch64/sme2p1-3-bad.d | 4 ++
gas/testsuite/gas/aarch64/sme2p1-3-bad.l | 30 ++++++++++
gas/testsuite/gas/aarch64/sme2p1-3-bad.s | 20 +++++++
gas/testsuite/gas/aarch64/sme2p1-3.d | 26 ++++++++
gas/testsuite/gas/aarch64/sme2p1-3.s | 19 ++++++
gas/testsuite/gas/aarch64/sme2p1-4-bad.d | 4 ++
gas/testsuite/gas/aarch64/sme2p1-4-bad.l | 76 ++++++++++++++++++++++++
gas/testsuite/gas/aarch64/sme2p1-4-bad.s | 48 +++++++++++++++
gas/testsuite/gas/aarch64/sme2p1-4.d | 53 +++++++++++++++++
gas/testsuite/gas/aarch64/sme2p1-4.s | 48 +++++++++++++++
include/opcode/aarch64.h | 1 +
opcodes/aarch64-asm.c | 43 ++++++++++++++
opcodes/aarch64-asm.h | 1 +
opcodes/aarch64-dis.c | 49 +++++++++++++++
opcodes/aarch64-dis.h | 1 +
opcodes/aarch64-opc.c | 13 +++-
opcodes/aarch64-opc.h | 4 ++
opcodes/aarch64-tbl.h | 19 ++++++
19 files changed, 459 insertions(+), 1 deletion(-)
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.l
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.s
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3.s
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-4-bad.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-4-bad.l
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-4-bad.s
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-4.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-4.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0003-aarch64-Add-support-for-sme2.1-movaz-instructions.patch --]
[-- Type: text/x-patch; name="v1-0003-aarch64-Add-support-for-sme2.1-movaz-instructions.patch", Size: 27235 bytes --]
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 2cd47f3d099..d4906ef3ddb 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8181,6 +8181,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SME_ZA_array_vrsh_2:
case AARCH64_OPND_SME_ZA_array_vrss_2:
case AARCH64_OPND_SME_ZA_array_vrsd_2:
+ case AARCH64_OPND_SME_ZA_ARRAY4:
if (!parse_dual_indexed_reg (&str, REG_TYPE_ZATHV,
&info->indexed_za, &qualifier, 0))
goto failure;
diff --git a/gas/testsuite/gas/aarch64/sme2p1-3-bad.d b/gas/testsuite/gas/aarch64/sme2p1-3-bad.d
new file mode 100644
index 00000000000..730d3bff752
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-3-bad.d
@@ -0,0 +1,4 @@
+#name: Negative test of SME2.1 movaz array to vector instructions.
+#as: -march=armv9.4-a+sme2p1
+#source: sme2p1-3-bad.s
+#error_output: sme2p1-3-bad.l
diff --git a/gas/testsuite/gas/aarch64/sme2p1-3-bad.l b/gas/testsuite/gas/aarch64/sme2p1-3-bad.l
new file mode 100644
index 00000000000..8b7019f6163
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-3-bad.l
@@ -0,0 +1,30 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `movaz {z0.s-z1.s},za.d\[w8,0,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: movaz {z0.d-z1.d}, za.d\[w8, 0, vgx2\]
+.*: Error: operand mismatch -- `movaz {z30.h-z31.h},za.d\[w8,0,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: movaz {z30.d-z31.d}, za.d\[w8, 0, vgx2\]
+.*: Error: operand mismatch -- `movaz {z0.b-z1.b},za.b\[w11,0,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: movaz {z0.d-z1.d}, za.d\[w11, 0, vgx2\]
+.*: Error: expected a selection register in the range w8-w11 at operand 2 -- `movaz {z0.d-z1.d},za.d\[w13,7,vgx2\]'
+.*: Error: immediate offset out of range 0 to 7 at operand 2 -- `movaz {z30.d-z31.d},za.d\[w11,15,vgx2\]'
+.*: Error: invalid vector group size at operand 2 -- `movaz {z14.d-z15.d},za.d\[w9,4,vgx3\]'
+.*: Error: missing immediate offset at operand 2 -- `movaz {z6.d-z7.d},za.d\[w10\]'
+.*: Error: missing immediate offset at operand 2 -- `movaz {z2.d-z4.d},za.d\[w10 6\]'
+.*: Error: operand mismatch -- `movaz {z0.s-z3.s},za.d\[w8,0,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: movaz {z0.d-z3.d}, za.d\[w8, 0, vgx4\]
+.*: Error: operand mismatch -- `movaz {z28.h-z31.h},za.d\[w8,0,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: movaz {z28.d-z31.d}, za.d\[w8, 0, vgx4\]
+.*: Error: operand mismatch -- `movaz {z0.b-z3.b},za.b\[w11,0,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: movaz {z0.d-z3.d}, za.d\[w11, 0, vgx4\]
+.*: Error: expected a selection register in the range w8-w11 at operand 2 -- `movaz {z0.d-z3.d},za.d\[w14,7,vgx4\]'
+.*: Error: invalid vector group size at operand 2 -- `movaz {z28.d-z31.d},za.d\[w11,11,vgx3\]'
+.*: Error: start register out of range at operand 1 -- `movaz {z14.d-z17.d},za.d\[w9,4,vgx4\]'
+.*: Error: too many registers in vector register list at operand 1 -- `movaz {z4.d-z8.d},za.d\[w10,3,vgx4\]'
+.*: Error: missing immediate offset at operand 2 -- `movaz {z0.d,z3.d},za.d\[w10\]'
+.*: Error: the register list must have a stride of 1 at operand 1 -- `movaz {z1.d,z4.d},za.d\[w10,20\]'
diff --git a/gas/testsuite/gas/aarch64/sme2p1-3-bad.s b/gas/testsuite/gas/aarch64/sme2p1-3-bad.s
new file mode 100644
index 00000000000..cec5987e535
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-3-bad.s
@@ -0,0 +1,20 @@
+/* MOVAZ (array to vector, two registers). */
+movaz {z0.s - z1.s} , za.d[w8, 0, vgx2]
+movaz {z30.h - z31.h} , za.d[w8, 0, vgx2]
+movaz {z0.b - z1.b} , za.b[w11, 0, vgx2]
+movaz {z0.d - z1.d} , za.d[w13, 7, vgx2]
+movaz {z30.d - z31.d} , za.d[w11, 15, vgx2]
+movaz {z14.d - z15.d} , za.d[w9, 4, vgx3]
+movaz {z6.d - z7.d} , za.d[w10]
+movaz {z2.d - z4.d} , za.d[w10 6]
+
+/* MOVAZ (array to vector, four registers). */
+movaz {z0.s - z3.s} , za.d[w8, 0, vgx4]
+movaz {z28.h - z31.h} , za.d[w8, 0, vgx4]
+movaz {z0.b - z3.b} , za.b[w11, 0, vgx4]
+movaz {z0.d - z3.d} , za.d[w14, 7, vgx4]
+movaz {z28.d - z31.d} , za.d[w11, 11, vgx3]
+movaz {z14.d - z17.d} , za.d[w9, 4, vgx4]
+movaz {z4.d - z8.d} , za.d[w10, 3, vgx4]
+movaz {z0.d, z3.d} , za.d[w10]
+movaz {z1.d, z4.d} , za.d[w10 , 20]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-3.d b/gas/testsuite/gas/aarch64/sme2p1-3.d
new file mode 100644
index 00000000000..f9f20eb8a04
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-3.d
@@ -0,0 +1,26 @@
+#name: Test of SME2.1 movaz array to vector instructions.
+#as: -march=armv9.4-a+sme2p1
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: c0060a00 movaz {z0.d-z1.d}, za.d\[w8, 0, vgx2\]
+.*: c0060a1e movaz {z30.d-z31.d}, za.d\[w8, 0, vgx2\]
+.*: c0066a00 movaz {z0.d-z1.d}, za.d\[w11, 0, vgx2\]
+.*: c0060ae0 movaz {z0.d-z1.d}, za.d\[w8, 7, vgx2\]
+.*: c0066afe movaz {z30.d-z31.d}, za.d\[w11, 7, vgx2\]
+.*: c0062a8e movaz {z14.d-z15.d}, za.d\[w9, 4, vgx2\]
+.*: c0064a66 movaz {z6.d-z7.d}, za.d\[w10, 3, vgx2\]
+.*: c0064ac2 movaz {z2.d-z3.d}, za.d\[w10, 6, vgx2\]
+.*: c0060e00 movaz {z0.d-z3.d}, za.d\[w8, 0, vgx4\]
+.*: c0060e1c movaz {z28.d-z31.d}, za.d\[w8, 0, vgx4\]
+.*: c0066e00 movaz {z0.d-z3.d}, za.d\[w11, 0, vgx4\]
+.*: c0060ee0 movaz {z0.d-z3.d}, za.d\[w8, 7, vgx4\]
+.*: c0066efc movaz {z28.d-z31.d}, za.d\[w11, 7, vgx4\]
+.*: c0062e8c movaz {z12.d-z15.d}, za.d\[w9, 4, vgx4\]
+.*: c0064e64 movaz {z4.d-z7.d}, za.d\[w10, 3, vgx4\]
+.*: c0064ec0 movaz {z0.d-z3.d}, za.d\[w10, 6, vgx4\]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-3.s b/gas/testsuite/gas/aarch64/sme2p1-3.s
new file mode 100644
index 00000000000..3a822da478d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-3.s
@@ -0,0 +1,19 @@
+/* MOVAZ (array to vector, two registers). */
+movaz {z0.d - z1.d} , za.d[w8, 0, vgx2]
+movaz {z30.d - z31.d} , za.d[w8, 0, vgx2]
+movaz {z0.d - z1.d} , za.d[w11, 0, vgx2]
+movaz {z0.d - z1.d} , za.d[w8, 7, vgx2]
+movaz {z30.d - z31.d} , za.d[w11, 7, vgx2]
+movaz {z14.d - z15.d} , za.d[w9, 4, vgx2]
+movaz {z6.d - z7.d} , za.d[w10, 3, vgx2]
+movaz {z2.d - z3.d} , za.d[w10, 6]
+
+/* MOVAZ (array to vector, four registers). */
+movaz {z0.d - z3.d} , za.d[w8, 0, vgx4]
+movaz {z28.d - z31.d} , za.d[w8, 0, vgx4]
+movaz {z0.d - z3.d} , za.d[w11, 0, vgx4]
+movaz {z0.d - z3.d} , za.d[w8, 7, vgx4]
+movaz {z28.d - z31.d} , za.d[w11, 7, vgx4]
+movaz {z12.d - z15.d} , za.d[w9, 4, vgx4]
+movaz {z4.d - z7.d} , za.d[w10, 3, vgx4]
+movaz {z0.d - z3.d} , za.d[w10, 6]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-4-bad.d b/gas/testsuite/gas/aarch64/sme2p1-4-bad.d
new file mode 100644
index 00000000000..4656ad626b2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-4-bad.d
@@ -0,0 +1,4 @@
+#name: Negative test of SME2.1 MOVAZ (tile to vector, single) instructions.
+#as: -march=armv9.4-a+sme2p1
+#source: sme2p1-4-bad.s
+#error_output: sme2p1-4-bad.l
diff --git a/gas/testsuite/gas/aarch64/sme2p1-4-bad.l b/gas/testsuite/gas/aarch64/sme2p1-4-bad.l
new file mode 100644
index 00000000000..fd35f4f2ffe
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-4-bad.l
@@ -0,0 +1,76 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `movaz z0.b,za0h.s\[w12,0\]'
+.*: Info: did you mean this\?
+.*: Info: movaz z0.b, za0h.b \[w12, 0\]
+.*: Error: operand mismatch -- `movaz z31.d,za0h.b\[w12,0\]'
+.*: Info: did you mean this\?
+.*: Info: movaz z31.b, za0h.b \[w12, 0\]
+.*: Error: operand mismatch -- `movaz z0.b,za0v.h\[w12,0\]'
+.*: Info: did you mean this\?
+.*: Info: movaz z0.b, za0v.b \[w12, 0\]
+.*: Error: expected a ZA tile slice at operand 2 -- `movaz z0.q,za0vh.b\[w15,0\]'
+.*: Error: operand mismatch -- `movaz z0.s,za0h.b\[w10,15\]'
+.*: Info: did you mean this\?
+.*: Info: movaz z0.b, za0h.b \[w10, 15\]
+.*: Error: ZA tile number out of range at operand 2 -- `movaz z31.b,za1v.b\[w25,15\]'
+.*: Error: immediate offset out of range 0 to 15 at operand 2 -- `movaz z15.b,za0h.b\[w13,31\]'
+.*: Error: missing immediate offset at operand 2 -- `movaz z7.h,za0h.b\[w14\]'
+.*: Error: operand mismatch -- `movaz z0.s,za0h.h\[w12,0\]'
+.*: Info: did you mean this\?
+.*: Info: movaz z0.h, za0h.h \[w12, 0\]
+.*: Error: operand mismatch -- `movaz z31.h,za0h.d\[w12,0\]'
+.*: Info: did you mean this\?
+.*: Info: movaz z31.h, za0h.h \[w12, 0\]
+.*: Error: ZA tile number out of range at operand 2 -- `movaz z0.h,za1h.b\[w12,0\]'
+.*: Error: expected a ZA tile slice at operand 2 -- `movaz z0.q,za0vh.h\[w12,0\]'
+.*: Error: expected a selection register in the range w12-w15 at operand 2 -- `movaz z0.h,za0h.h\[w17,0\]'
+.*: Error: immediate offset out of range 0 to 15 at operand 2 -- `movaz z0.h,za0h.h\[w12,27\]'
+.*: Error: ZA tile number out of range at operand 2 -- `movaz z31.h,za3v.h\[w15,7\]'
+.*: Error: expected a selection register in the range w12-w15 at operand 2 -- `movaz z15.h,za0h.h\[w2,3\]'
+.*: Error: missing immediate offset at operand 2 -- `movaz z7.d,za0h.h\[w14\]'
+.*: Error: operand mismatch -- `movaz z0.b,za0h.s\[w12,0\]'
+.*: Info: did you mean this\?
+.*: Info: movaz z0.b, za0h.b \[w12, 0\]
+.*: Error: operand mismatch -- `movaz z31.s,za0h.h\[w12,0\]'
+.*: Info: did you mean this\?
+.*: Info: movaz z31.h, za0h.h \[w12, 0\]
+.*: Error: operand mismatch -- `movaz z0.s,za3h\[w12,0\]'
+.*: Info: did you mean this\?
+.*: Info: movaz z0.s, za3h.s \[w12, 0\]
+.*: Error: expected a selection register in the range w12-w15 at operand 2 -- `movaz z0.s,za0v.s\[w1,0\]'
+.*: Error: operand mismatch -- `movaz z0.q,za0h.s\[w25,0\]'
+.*: Info: did you mean this\?
+.*: Info: movaz z0.s, za0h.s \[w25, 0\]
+.*: Error: ZA tile number out of range at operand 2 -- `movaz z31.s,za5v.s\[w15,3\]'
+.*: Error: missing immediate offset at operand 2 -- `movaz z15.s,za1h.s\[w13\]'
+.*: Error: operand mismatch -- `movaz z7.b,za2h.d\[w14,1\]'
+.*: Info: did you mean this\?
+.*: Info: movaz z7.b, za2h.b \[w14, 1\]
+.*: Error: operand mismatch -- `movaz z0.b,za0h.d\[w12,0\]'
+.*: Info: did you mean this\?
+.*: Info: movaz z0.b, za0h.b \[w12, 0\]
+.*: Error: operand mismatch -- `movaz z31.d,za0h.h\[w12,0\]'
+.*: Info: did you mean this\?
+.*: Info: movaz z31.h, za0h.h \[w12, 0\]
+.*: Error: ZA tile number out of range at operand 2 -- `movaz z0.d,za7h.s\[w12,0\]'
+.*: Error: operand mismatch -- `movaz z0.s,za0v.q\[w12,0\]'
+.*: Info: did you mean this\?
+.*: Info: movaz z0.s, za0v.s \[w12, 0\]
+.*: Error: expected a ZA tile slice at operand 2 -- `movaz z0.d,za0vh.d\[w15,0\]'
+.*: Error: ZA tile number out of range at operand 2 -- `movaz z31.d,za11v.d\[w1,1\]'
+.*: Error: expected a selection register in the range w12-w15 at operand 2 -- `movaz z15.d,za3h.d\[w23,0\]'
+.*: Error: missing immediate offset at operand 2 -- `movaz z7.s,za4h.q\[w14\]'
+.*: Error: operand mismatch -- `movaz z0.b,za0h.q\[w12,0\]'
+.*: Info: did you mean this\?
+.*: Info: movaz z0.b, za0h.b \[w12, 0\]
+.*: Error: expected a ZA tile slice at operand 2 -- `movaz z31.q,za0vh.s\[w12,0\]'
+.*: Error: ZA tile number out of range at operand 2 -- `movaz z0.q,za15h.h\[w20,0\]'
+.*: Error: operand mismatch -- `movaz z0.s,za0v.d\[w12,0\]'
+.*: Info: did you mean this\?
+.*: Info: movaz z0.s, za0v.s \[w12, 0\]
+.*: Error: expected a selection register in the range w12-w15 at operand 2 -- `movaz z0.q,za0h.q\[w1,0\]'
+.*: Error: operand mismatch -- `movaz z31.q,za15v\[w15,0\]'
+.*: Info: did you mean this\?
+.*: Info: movaz z31.q, za15v.q \[w15, 0\]
+.*: Error: expected a ZA tile slice at operand 2 -- `movaz z5.q,za27.q\[w13,0\]'
+.*: Error: missing immediate offset at operand 2 -- `movaz z7.q,za6h\[w14\]'
diff --git a/gas/testsuite/gas/aarch64/sme2p1-4-bad.s b/gas/testsuite/gas/aarch64/sme2p1-4-bad.s
new file mode 100644
index 00000000000..1a13191d5b2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-4-bad.s
@@ -0,0 +1,48 @@
+/* MOVAZ (tile to vector, single). */
+movaz z0.b, za0h.s[w12, 0]
+movaz z31.d, za0h.b[w12, 0]
+movaz z0.b, za0v.h[w12, 0]
+movaz z0.q, za0vh.b[w15, 0]
+movaz z0.s, za0h.b[w10, 15]
+movaz z31.b, za1v.b[w25, 15]
+movaz z15.b, za0h.b[w13, 31]
+movaz z7.h, za0h.b[w14]
+
+movaz z0.s, za0h.h[w12, 0]
+movaz z31.h, za0h.d[w12, 0]
+movaz z0.h, za1h.b[w12, 0]
+movaz z0.q, za0vh.h[w12, 0]
+movaz z0.h, za0h.h[w17, 0]
+movaz z0.h, za0h.h[w12, 27]
+movaz z31.h, za3v.h[w15, 7]
+movaz z15.h, za0h.h[w2, 3]
+movaz z7.d, za0h.h[w14]
+
+movaz z0.b, za0h.s[w12, 0]
+movaz z31.s, za0h.h[w12, 0]
+movaz z0.s, za3h[w12, 0]
+movaz z0.s, za0v.s[w1, 0]
+movaz z0.q, za0h.s[w25, 0]
+movaz z0.s, za0h.s[w12, 13]
+movaz z31.s, za5v.s[w15, 3]
+movaz z15.s, za1h.s[w13]
+movaz z7.b, za2h.d[w14, 1]
+
+movaz z0.b, za0h.d[w12, 0]
+movaz z31.d, za0h.h[w12, 0]
+movaz z0.d, za7h.s[w12, 0]
+movaz z0.s, za0v.q[w12, 0]
+movaz z0.d, za0vh.d[w15, 0]
+movaz z0.d, za0h.d[w12, 1]
+movaz z31.d, za11v.d[w1, 1]
+movaz z15.d, za3h.d[w23, 0]
+movaz z7.s, za4h.q[w14]
+
+movaz z0.b, za0h.q[w12, 0]
+movaz z31.q, za0vh.s[w12, 0]
+movaz z0.q, za15h.h[w20, 0]
+movaz z0.s, za0v.d[w12, 0]
+movaz z0.q, za0h.q[w1, 0]
+movaz z31.q, za15v[w15, 0]
+movaz z5.q, za27.q[w13, 0]
+movaz z7.q, za6h[w14]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-4.d b/gas/testsuite/gas/aarch64/sme2p1-4.d
new file mode 100644
index 00000000000..add27084245
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-4.d
@@ -0,0 +1,53 @@
+#name: Test of SME2.1 MOVAZ (tile to vector, single) instructions.
+#as: -march=armv9.4-a+sme2p1
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: c0020200 movaz z0.b, za0h.b \[w12, 0\]
+.*: c002021f movaz z31.b, za0h.b \[w12, 0\]
+.*: c0028200 movaz z0.b, za0v.b \[w12, 0\]
+.*: c0026200 movaz z0.b, za0h.b \[w15, 0\]
+.*: c00203e0 movaz z0.b, za0h.b \[w12, 15\]
+.*: c002e3ff movaz z31.b, za0v.b \[w15, 15\]
+.*: c002226f movaz z15.b, za0h.b \[w13, 3\]
+.*: c0024227 movaz z7.b, za0h.b \[w14, 1\]
+.*: c0420200 movaz z0.h, za0h.h \[w12, 0\]
+.*: c042021f movaz z31.h, za0h.h \[w12, 0\]
+.*: c0420300 movaz z0.h, za1h.h \[w12, 0\]
+.*: c0428200 movaz z0.h, za0v.h \[w12, 0\]
+.*: c0426200 movaz z0.h, za0h.h \[w15, 0\]
+.*: c04202e0 movaz z0.h, za0h.h \[w12, 7\]
+.*: c042e3ff movaz z31.h, za1v.h \[w15, 7\]
+.*: c042226f movaz z15.h, za0h.h \[w13, 3\]
+.*: c0424227 movaz z7.h, za0h.h \[w14, 1\]
+.*: c0820200 movaz z0.s, za0h.s \[w12, 0\]
+.*: c082021f movaz z31.s, za0h.s \[w12, 0\]
+.*: c0820380 movaz z0.s, za3h.s \[w12, 0\]
+.*: c0828200 movaz z0.s, za0v.s \[w12, 0\]
+.*: c0826200 movaz z0.s, za0h.s \[w15, 0\]
+.*: c0820260 movaz z0.s, za0h.s \[w12, 3\]
+.*: c082e3ff movaz z31.s, za3v.s \[w15, 3\]
+.*: c08222cf movaz z15.s, za1h.s \[w13, 2\]
+.*: c0824327 movaz z7.s, za2h.s \[w14, 1\]
+.*: c0c20200 movaz z0.d, za0h.d \[w12, 0\]
+.*: c0c2021f movaz z31.d, za0h.d \[w12, 0\]
+.*: c0c203c0 movaz z0.d, za7h.d \[w12, 0\]
+.*: c0c28200 movaz z0.d, za0v.d \[w12, 0\]
+.*: c0c26200 movaz z0.d, za0h.d \[w15, 0\]
+.*: c0c20220 movaz z0.d, za0h.d \[w12, 1\]
+.*: c0c2e3ff movaz z31.d, za7v.d \[w15, 1\]
+.*: c0c222cf movaz z15.d, za3h.d \[w13, 0\]
+.*: c0c24327 movaz z7.d, za4h.d \[w14, 1\]
+.*: c0c30200 movaz z0.q, za0h.q \[w12, 0\]
+.*: c0c3021f movaz z31.q, za0h.q \[w12, 0\]
+.*: c0c303e0 movaz z0.q, za15h.q \[w12, 0\]
+.*: c0c38200 movaz z0.q, za0v.q \[w12, 0\]
+.*: c0c36200 movaz z0.q, za0h.q \[w15, 0\]
+.*: c0c3e3ff movaz z31.q, za15v.q \[w15, 0\]
+.*: c0c322ef movaz z15.q, za7h.q \[w13, 0\]
+.*: c0c342c7 movaz z7.q, za6h.q \[w14, 0\]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-4.s b/gas/testsuite/gas/aarch64/sme2p1-4.s
new file mode 100644
index 00000000000..5c48af46cb7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-4.s
@@ -0,0 +1,48 @@
+/* MOVAZ (tile to vector, single). */
+movaz z0.b, za0h.b[w12, 0]
+movaz z31.b, za0h.b[w12, 0]
+movaz z0.b, za0v.b[w12, 0]
+movaz z0.b, za0h.b[w15, 0]
+movaz z0.b, za0h.b[w12, 15]
+movaz z31.b, za0v.b[w15, 15]
+movaz z15.b, za0h.b[w13, 3]
+movaz z7.b, za0h.b[w14, 1]
+
+movaz z0.h, za0h.h[w12, 0]
+movaz z31.h, za0h.h[w12, 0]
+movaz z0.h, za1h.h[w12, 0]
+movaz z0.h, za0v.h[w12, 0]
+movaz z0.h, za0h.h[w15, 0]
+movaz z0.h, za0h.h[w12, 7]
+movaz z31.h, za1v.h[w15, 7]
+movaz z15.h, za0h.h[w13, 3]
+movaz z7.h, za0h.h[w14, 1]
+
+movaz z0.s, za0h.s[w12, 0]
+movaz z31.s, za0h.s[w12, 0]
+movaz z0.s, za3h.s[w12, 0]
+movaz z0.s, za0v.s[w12, 0]
+movaz z0.s, za0h.s[w15, 0]
+movaz z0.s, za0h.s[w12, 3]
+movaz z31.s, za3v.s[w15, 3]
+movaz z15.s, za1h.s[w13, 2]
+movaz z7.s, za2h.s[w14, 1]
+
+movaz z0.d, za0h.d[w12, 0]
+movaz z31.d, za0h.d[w12, 0]
+movaz z0.d, za7h.d[w12, 0]
+movaz z0.d, za0v.d[w12, 0]
+movaz z0.d, za0h.d[w15, 0]
+movaz z0.d, za0h.d[w12, 1]
+movaz z31.d, za7v.d[w15, 1]
+movaz z15.d, za3h.d[w13, 0]
+movaz z7.d, za4h.d[w14, 1]
+
+movaz z0.q, za0h.q[w12, 0]
+movaz z31.q, za0h.q[w12, 0]
+movaz z0.q, za15h.q[w12, 0]
+movaz z0.q, za0v.q[w12, 0]
+movaz z0.q, za0h.q[w15, 0]
+movaz z31.q, za15v.q[w15, 0]
+movaz z15.q, za7h.q[w13, 0]
+movaz z7.q, za6h.q[w14, 0]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 64959a8c50e..5a2b99d2bc5 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -789,6 +789,7 @@ enum aarch64_opnd
AARCH64_OPND_SME_ZA_array_vrsh_2, /* Tile to vector, four registers (H). */
AARCH64_OPND_SME_ZA_array_vrss_2, /* Tile to vector, four registers (S). */
AARCH64_OPND_SME_ZA_array_vrsd_2, /* Tile to vector, four registers (D). */
+ AARCH64_OPND_SME_ZA_ARRAY4, /* Tile to vector, single (BHSDQ). */
AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index e621bd86e87..cd79ec19cdc 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1521,6 +1521,49 @@ aarch64_ins_sme_za_vrs2 (const aarch64_operand *self,
return true;
}
+/* Encode in SME instruction such as MOVZA ZA tile slice to vector. */
+bool
+aarch64_ins_sme_za_tile_to_vec (const aarch64_operand *self,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ int fld_v = info->indexed_za.v;
+ int fld_rv = info->indexed_za.index.regno - 12;
+ int fld_zan_imm = info->indexed_za.index.imm;
+ int regno = info->indexed_za.regno;
+
+ switch (info->qualifier)
+ {
+ case AARCH64_OPND_QLF_S_B:
+ insert_field (FLD_imm4_5, code, fld_zan_imm, 0);
+ break;
+ case AARCH64_OPND_QLF_S_H:
+ insert_field (FLD_ZA8_1, code, regno, 0);
+ insert_field (FLD_imm3_5, code, fld_zan_imm, 0);
+ break;
+ case AARCH64_OPND_QLF_S_S:
+ insert_field (FLD_ZA7_2, code, regno, 0);
+ insert_field (FLD_off2, code, fld_zan_imm, 0);
+ break;
+ case AARCH64_OPND_QLF_S_D:
+ insert_field (FLD_ZA6_3, code, regno, 0);
+ insert_field (FLD_ol, code, fld_zan_imm, 0);
+ break;
+ case AARCH64_OPND_QLF_S_Q:
+ insert_field (FLD_ZA5_4, code, regno, 0);
+ break;
+ default:
+ return false;
+ }
+
+ insert_field (self->fields[0], code, fld_v, 0);
+ insert_field (self->fields[1], code, fld_rv, 0);
+
+ return true;
+}
+
/* Encode in SME instruction such as MOVA ZA tile vector register number,
vector indicator, vector selector and immediate. */
bool
diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h
index 88143eecfcd..dca0690137c 100644
--- a/opcodes/aarch64-asm.h
+++ b/opcodes/aarch64-asm.h
@@ -104,6 +104,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm);
AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm);
AARCH64_DECL_OPD_INSERTER (ins_sme_za_vrs1);
AARCH64_DECL_OPD_INSERTER (ins_sme_za_vrs2);
+AARCH64_DECL_OPD_INSERTER (ins_sme_za_tile_to_vec);
AARCH64_DECL_OPD_INSERTER (ins_sme_za_hv_tiles);
AARCH64_DECL_OPD_INSERTER (ins_sme_za_hv_tiles_range);
AARCH64_DECL_OPD_INSERTER (ins_sme_za_list);
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 81ebbe0bd55..6e945705319 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1956,6 +1956,55 @@ aarch64_ext_sve_float_zero_one (const aarch64_operand *self,
return true;
}
+/* Decode SME instruction such as MOVZA ZA tile slice to vector. */
+bool
+aarch64_ext_sme_za_tile_to_vec (const aarch64_operand *self,
+ aarch64_opnd_info *info, aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ aarch64_insn Qsize; /* fields Q:S:size. */
+ int fld_v = extract_field (self->fields[0], code, 0);
+ int fld_rv = extract_field (self->fields[1], code, 0);
+ int fld_zan_imm = extract_field (FLD_imm4_5, code, 0);
+
+ Qsize = extract_fields (inst->value, 0, 2, FLD_SME_size_22, FLD_SME_Q);
+ switch (Qsize)
+ {
+ case 0x0:
+ info->qualifier = AARCH64_OPND_QLF_S_B;
+ info->indexed_za.regno = 0;
+ info->indexed_za.index.imm = fld_zan_imm;
+ break;
+ case 0x2:
+ info->qualifier = AARCH64_OPND_QLF_S_H;
+ info->indexed_za.regno = fld_zan_imm >> 3;
+ info->indexed_za.index.imm = fld_zan_imm & 0x07;
+ break;
+ case 0x4:
+ info->qualifier = AARCH64_OPND_QLF_S_S;
+ info->indexed_za.regno = fld_zan_imm >> 2;
+ info->indexed_za.index.imm = fld_zan_imm & 0x03;
+ break;
+ case 0x6:
+ info->qualifier = AARCH64_OPND_QLF_S_D;
+ info->indexed_za.regno = fld_zan_imm >> 1;
+ info->indexed_za.index.imm = fld_zan_imm & 0x01;
+ break;
+ case 0x7:
+ info->qualifier = AARCH64_OPND_QLF_S_Q;
+ info->indexed_za.regno = fld_zan_imm;
+ break;
+ default:
+ return false;
+ }
+
+ info->indexed_za.index.regno = fld_rv + 12;
+ info->indexed_za.v = fld_v;
+
+ return true;
+}
+
/* Decode ZA tile vector, vector indicator, vector selector, qualifier and
immediate on numerous SME instruction fields such as MOVA. */
bool
diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h
index a71524f9c64..2ffcef0e652 100644
--- a/opcodes/aarch64-dis.h
+++ b/opcodes/aarch64-dis.h
@@ -128,6 +128,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shrimm);
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_vrs1);
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_vrs2);
+AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_tile_to_vec);
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles);
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles_range);
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_list);
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 0e726102693..f65f83a0126 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -433,7 +433,11 @@ const aarch64_field fields[] =
{ 6, 1 }, /* ZAn: name of the bit encoded ZA tile. */
{ 12, 4 }, /* opc2: in rcpc3 ld/st inst deciding the pre/post-index. */
{ 30, 2 }, /* rcpc3_size: in rcpc3 ld/st, field controls Rt/Rt2 width. */
- { 5, 1 }, /* FLD_brbop: used in BRB to mean IALL or INJ. */
+ { 5, 1 }, /* FLD_brbop: used in BRB to mean IALL or INJ. */
+ { 8, 1 }, /* ZA8_1: name of the 1 bit encoded ZA tile ZA0-ZA1. */
+ { 7, 2 }, /* ZA7_2: name of the 2 bits encoded ZA tile ZA0-ZA3. */
+ { 6, 3 }, /* ZA6_3: name of the 3 bits encoded ZA tile ZA0-ZA7. */
+ { 5, 4 }, /* ZA5_4: name of the 4 bits encoded ZA tile ZA0-ZA15. */
};
enum aarch64_operand_class
@@ -2066,6 +2070,12 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
return 0;
break;
+ case AARCH64_OPND_SME_ZA_ARRAY4:
+ if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, 1,
+ get_opcode_dependent_value (opcode)))
+ return 0;
+ break;
+
case AARCH64_OPND_SME_ZA_array_vrss_2:
case AARCH64_OPND_SME_ZA_array_vrsd_2:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 0, 4,
@@ -4408,6 +4418,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SME_ZA_array_vrsh_2:
case AARCH64_OPND_SME_ZA_array_vrss_2:
case AARCH64_OPND_SME_ZA_array_vrsd_2:
+ case AARCH64_OPND_SME_ZA_ARRAY4:
snprintf (buf, size, "%s [%s, %s%s%s]",
style_reg (styler, "za%d%c%s%s",
opnd->indexed_za.regno,
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 49310960305..b3ef440f98b 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -235,6 +235,10 @@ enum aarch64_field_kind
FLD_opc2,
FLD_rcpc3_size,
FLD_brbop,
+ FLD_ZA8_1,
+ FLD_ZA7_2,
+ FLD_ZA6_3,
+ FLD_ZA5_4,
};
/* Field description. */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index eccfac53ad1..38be471965c 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2269,6 +2269,10 @@
QLF3(S_H,S_S,S_S), \
QLF3(S_S,S_D,S_D), \
}
+#define OP_SVE_VV_D \
+{ \
+ QLF2(S_D, S_D) \
+}
#define OP_SVE_VV_BHS_HSD \
{ \
QLF2(S_B,S_H), \
@@ -6651,6 +6655,19 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2p1_INSN ("luti4", 0xc09a4000, 0xfffe4c08, sme_size_12_bh, 0, OP3 (SME_Ztx2_STRIDED, SME_ZT0, SME_Zn_INDEX2_15), OP_SVE_VUU_BH, 0, 0),
SME2p1_INSN ("luti4", 0xc09a9000, 0xfffefc0c, sme_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_ZT0, SME_Zn_INDEX1_16), OP_SVE_HUU, 0, 0),
+ /* SME2.1 MOVAZ (array to vector, two registers). */
+ SME2p1_INSN ("movaz", 0xc0060a00, 0xffff9f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_D, F_OD (2), 0),
+
+ /* SME2.1 MOVAZ (array to vector, four registers). */
+ SME2p1_INSN ("movaz", 0xc0060e00, 0xffff9f03, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_D, F_OD (4), 0),
+
+ /* SME2.1 MOVAZ (tile to vector, single). */
+ SME2p1_INSN ("movaz", 0xc0020200, 0xffff1e00, sme2_movaz, 0, OP2 (SVE_Zd, SME_ZA_ARRAY4), OP_SVE_BB, 0, 0),
+ SME2p1_INSN ("movaz", 0xc0420200, 0xffff1e00, sme2_movaz, 0, OP2 (SVE_Zd, SME_ZA_ARRAY4), OP_SVE_HH, 0, 0),
+ SME2p1_INSN ("movaz", 0xc0820200, 0xffff1e00, sme2_movaz, 0, OP2 (SVE_Zd, SME_ZA_ARRAY4), OP_SVE_SS, 0, 0),
+ SME2p1_INSN ("movaz", 0xc0c20200, 0xffff1e00, sme2_movaz, 0, OP2 (SVE_Zd, SME_ZA_ARRAY4), OP_SVE_DD, 0, 0),
+ SME2p1_INSN ("movaz", 0xc0c30200, 0xffff1e00, sme2_movaz, 0, OP2 (SVE_Zd, SME_ZA_ARRAY4), OP_SVE_QQ, 0, 0),
+
/* SVE2p1 Instructions. */
SVE2p1_INSN("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
SVE2p1_INSN("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
@@ -7325,6 +7342,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
F(FLD_SME_V,FLD_SME_Rv,FLD_off2), "2 bit ZA tile") \
Y(ZA_ACCESS, sme_za_vrs2, "SME_ZA_array_vrsd_2", 0, \
F(FLD_SME_V,FLD_SME_Rv,FLD_ZAn_3), "3 bit ZA tile") \
+ Y(ZA_ACCESS, sme_za_tile_to_vec, "SME_ZA_ARRAY4", 0, \
+ F(FLD_SME_V,FLD_SME_Rv), "ZA tile to vector register") \
Y(SVE_REG, regno, "SVE_Za_5", 0, F(FLD_SVE_Za_5), \
"an SVE vector register") \
Y(SVE_REG, regno, "SVE_Za_16", 0, F(FLD_SVE_Za_16), \
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v1 4/6] aarch64: Add support for sme2.1 movaz instructions (regenerated files).
2024-07-08 15:36 [PATCH v1 0/6] Binutils] aarch64: Add support for sme2p1 instructions Srinath Parvathaneni
` (2 preceding siblings ...)
2024-07-08 15:36 ` [PATCH v1 3/6] aarch64: Add support for sme2.1 movaz instructions Srinath Parvathaneni
@ 2024-07-08 15:36 ` Srinath Parvathaneni
2024-07-08 15:36 ` [PATCH v1 5/6] aarch64: Add support for sme2.1 zero instructions Srinath Parvathaneni
` (2 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Srinath Parvathaneni @ 2024-07-08 15:36 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 302 bytes --]
This patch includes the regenerated files for
aarch64: Add support for sme2.1 movaz instructions.
---
opcodes/aarch64-asm-2.c | 94 +++----
opcodes/aarch64-dis-2.c | 551 +++++++++++++++++++++++-----------------
opcodes/aarch64-opc-2.c | 1 +
3 files changed, 364 insertions(+), 282 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0004-aarch64-Add-support-for-sme2.1-movaz-instructions.patch --]
[-- Type: text/x-patch; name="v1-0004-aarch64-Add-support-for-sme2.1-movaz-instructions.patch", Size: 140158 bytes --]
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index bfc2d8027c2..a7744681f4c 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -672,29 +672,29 @@ aarch64_insert_operand (const aarch64_operand *self,
case 214:
case 215:
case 216:
- case 225:
case 226:
case 227:
case 228:
case 229:
- case 240:
- case 244:
- case 249:
- case 257:
+ case 230:
+ case 241:
+ case 245:
+ case 250:
case 258:
case 259:
- case 266:
+ case 260:
case 267:
case 268:
case 269:
- case 303:
- case 307:
+ case 270:
+ case 304:
+ case 308:
return aarch64_ins_regno (self, info, code, inst, errors);
case 6:
case 119:
case 120:
- case 313:
- case 316:
+ case 314:
+ case 317:
return aarch64_ins_none (self, info, code, inst, errors);
case 17:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -709,17 +709,16 @@ aarch64_insert_operand (const aarch64_operand *self,
case 37:
case 38:
case 39:
- case 318:
+ case 319:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 40:
case 41:
case 42:
- case 230:
case 231:
- case 234:
- case 270:
+ case 232:
+ case 235:
case 271:
- case 286:
+ case 272:
case 287:
case 288:
case 289:
@@ -736,12 +735,13 @@ aarch64_insert_operand (const aarch64_operand *self,
case 300:
case 301:
case 302:
- case 304:
+ case 303:
case 305:
case 306:
- case 308:
+ case 307:
case 309:
case 310:
+ case 311:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 43:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -791,14 +791,14 @@ aarch64_insert_operand (const aarch64_operand *self,
case 210:
case 211:
case 212:
- case 272:
- case 311:
+ case 273:
case 312:
- case 314:
+ case 313:
case 315:
- case 317:
- case 322:
+ case 316:
+ case 318:
case 323:
+ case 324:
return aarch64_ins_imm (self, info, code, inst, errors);
case 52:
case 53:
@@ -947,7 +947,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 201:
case 202:
case 203:
- case 285:
+ case 286:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 217:
case 218:
@@ -959,67 +959,69 @@ aarch64_insert_operand (const aarch64_operand *self,
case 223:
case 224:
return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors);
- case 232:
+ case 225:
+ return aarch64_ins_sme_za_tile_to_vec (self, info, code, inst, errors);
case 233:
- case 235:
+ case 234:
case 236:
case 237:
case 238:
case 239:
+ case 240:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
- case 241:
case 242:
- return aarch64_ins_sve_index (self, info, code, inst, errors);
case 243:
- case 245:
- case 265:
- return aarch64_ins_sve_reglist (self, info, code, inst, errors);
+ return aarch64_ins_sve_index (self, info, code, inst, errors);
+ case 244:
case 246:
+ case 266:
+ return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 247:
- case 250:
+ case 248:
case 251:
case 252:
case 253:
case 254:
- case 264:
- return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
- case 248:
case 255:
+ case 265:
+ return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
+ case 249:
case 256:
+ case 257:
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
- case 260:
- case 262:
- case 273:
- return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 261:
case 263:
- return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 274:
+ return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
+ case 262:
+ case 264:
+ return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 275:
case 276:
case 277:
case 278:
case 279:
case 280:
- return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 281:
- return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+ return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 282:
- return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+ return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 283:
- return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 284:
+ return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 285:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
- case 319:
case 320:
case 321:
+ case 322:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
- case 324:
case 325:
case 326:
case 327:
- return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 328:
+ return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 329:
return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 36542af2dc4..7a7af4afea2 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -196,11 +196,66 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 19) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000xx0x001xxxxxxxxxxxxxxxxx
- mov. */
- return 2436;
+ if (((word >> 9) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0x001xxxxxxx0xxxxxxxxx
+ mov. */
+ return 2436;
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000000x0010xxxxxx1xxxxxxxxx
+ movaz. */
+ return 3312;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000100x0010xxxxxx1xxxxxxxxx
+ movaz. */
+ return 3314;
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000010x0010xxxxxx1xxxxxxxxx
+ movaz. */
+ return 3313;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000110x0010xxxxxx1xxxxxxxxx
+ movaz. */
+ return 3315;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0x0011xxxxxx1xxxxxxxxx
+ movaz. */
+ return 3316;
+ }
+ }
}
else
{
@@ -216,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3413;
+ return 3420;
}
else
{
@@ -255,7 +310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101x00xxxxxxxxxxxxxx
luti4. */
- return 3414;
+ return 3421;
}
else
{
@@ -399,7 +454,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010011x1xxxx00xxxxxxxxxx
movt. */
- return 3415;
+ return 3422;
}
}
else
@@ -445,11 +500,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000xx0xx11xxxxx10xxxxxxxxxx
- mov. */
- return 2672;
+ if (((word >> 9) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0xx11xxxxx100xxxxxxxxx
+ mov. */
+ return 2672;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0xx11xxxxx101xxxxxxxxx
+ movaz. */
+ return 3310;
+ }
}
}
}
@@ -530,11 +596,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000xx0xx11xxxxx11xxxxxxxxxx
- mov. */
- return 2673;
+ if (((word >> 9) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0xx11xxxxx110xxxxxxxxx
+ mov. */
+ return 2673;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0xx11xxxxx111xxxxxxxxx
+ movaz. */
+ return 3311;
+ }
}
}
}
@@ -1201,7 +1278,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3481;
+ return 3488;
}
else
{
@@ -1209,7 +1286,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3480;
+ return 3487;
}
}
else
@@ -1557,7 +1634,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3474;
+ return 3481;
}
}
}
@@ -1587,7 +1664,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxxxxx1xxxxxx00xxxx
fdot. */
- return 3459;
+ return 3466;
}
}
else
@@ -1959,7 +2036,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3473;
+ return 3480;
}
}
}
@@ -2064,7 +2141,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3466;
+ return 3473;
}
}
}
@@ -2237,7 +2314,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3465;
+ return 3472;
}
}
}
@@ -2279,7 +2356,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3472;
+ return 3479;
}
else
{
@@ -2647,7 +2724,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3452;
+ return 3459;
}
else
{
@@ -2716,7 +2793,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3453;
+ return 3460;
}
else
{
@@ -2795,7 +2872,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3464;
+ return 3471;
}
else
{
@@ -2850,7 +2927,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3483;
+ return 3490;
}
else
{
@@ -2868,7 +2945,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3458;
+ return 3465;
}
}
}
@@ -2942,7 +3019,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3482;
+ return 3489;
}
}
}
@@ -3022,7 +3099,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3484;
+ return 3491;
}
else
{
@@ -3199,7 +3276,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3478;
+ return 3485;
}
else
{
@@ -3207,7 +3284,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3479;
+ return 3486;
}
}
}
@@ -3262,7 +3339,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3476;
+ return 3483;
}
else
{
@@ -3270,7 +3347,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3477;
+ return 3484;
}
}
}
@@ -3324,7 +3401,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3462;
+ return 3469;
}
else
{
@@ -3332,7 +3409,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3463;
+ return 3470;
}
}
}
@@ -3394,7 +3471,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3470;
+ return 3477;
}
else
{
@@ -3402,7 +3479,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3471;
+ return 3478;
}
}
}
@@ -3457,7 +3534,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3468;
+ return 3475;
}
else
{
@@ -3465,7 +3542,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3469;
+ return 3476;
}
}
}
@@ -3534,7 +3611,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3475;
+ return 3482;
}
}
else
@@ -3617,7 +3694,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3467;
+ return 3474;
}
}
else
@@ -3638,7 +3715,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx00xxx
fadd. */
- return 3416;
+ return 3423;
}
}
else
@@ -3657,7 +3734,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx00xxx
fadd. */
- return 3417;
+ return 3424;
}
}
}
@@ -3783,7 +3860,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3456;
+ return 3463;
}
else
{
@@ -3791,7 +3868,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx110xxx
fdot. */
- return 3457;
+ return 3464;
}
}
}
@@ -4082,7 +4159,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx01xxx
fdot. */
- return 3460;
+ return 3467;
}
else
{
@@ -4090,7 +4167,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx01xxx
fdot. */
- return 3461;
+ return 3468;
}
}
}
@@ -4361,7 +4438,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx01xxx
fsub. */
- return 3418;
+ return 3425;
}
}
else
@@ -4380,7 +4457,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx01xxx
fsub. */
- return 3419;
+ return 3426;
}
}
}
@@ -4442,7 +4519,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx11xxx
fdot. */
- return 3454;
+ return 3461;
}
else
{
@@ -4450,7 +4527,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx11xxx
fdot. */
- return 3455;
+ return 3462;
}
}
}
@@ -4985,7 +5062,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3390;
+ return 3397;
}
}
else
@@ -5133,7 +5210,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3387;
+ return 3394;
}
else
{
@@ -5141,7 +5218,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3382;
+ return 3389;
}
}
else
@@ -5150,7 +5227,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3388;
+ return 3395;
}
}
else
@@ -5201,7 +5278,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3389;
+ return 3396;
}
}
}
@@ -5284,7 +5361,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3383;
+ return 3390;
}
else
{
@@ -5292,7 +5369,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3384;
+ return 3391;
}
}
else
@@ -5303,7 +5380,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3378;
+ return 3385;
}
else
{
@@ -5311,7 +5388,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3379;
+ return 3386;
}
}
}
@@ -5346,7 +5423,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3385;
+ return 3392;
}
else
{
@@ -5354,7 +5431,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxx10111000xxxxxxxxx1
f2cvtl. */
- return 3386;
+ return 3393;
}
}
else
@@ -5365,7 +5442,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001011xxx10111000xxxxxxxxx1
bf1cvtl. */
- return 3380;
+ return 3387;
}
else
{
@@ -5373,7 +5450,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001111xxx10111000xxxxxxxxx1
bf2cvtl. */
- return 3381;
+ return 3388;
}
}
}
@@ -5642,7 +5719,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1100xx100xxxx0
fscale. */
- return 3392;
+ return 3399;
}
}
else
@@ -5818,7 +5895,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1010xx100xxxx0
fscale. */
- return 3391;
+ return 3398;
}
else
{
@@ -5826,7 +5903,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1110xx100xxxx0
fscale. */
- return 3393;
+ return 3400;
}
}
}
@@ -10994,7 +11071,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3394;
+ return 3401;
}
else
{
@@ -11002,7 +11079,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3395;
+ return 3402;
}
}
}
@@ -11920,7 +11997,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3396;
+ return 3403;
}
else
{
@@ -11928,7 +12005,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3397;
+ return 3404;
}
}
}
@@ -12013,7 +12090,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3398;
+ return 3405;
}
else
{
@@ -12120,7 +12197,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3400;
+ return 3407;
}
else
{
@@ -12325,7 +12402,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3399;
+ return 3406;
}
else
{
@@ -12366,7 +12443,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3401;
+ return 3408;
}
else
{
@@ -14024,7 +14101,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3403;
+ return 3410;
}
}
else
@@ -14054,7 +14131,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3402;
+ return 3409;
}
}
}
@@ -14362,7 +14439,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx00x100001xxxxxxxxxxxxx
smaxqv. */
- return 3312;
+ return 3319;
}
else
{
@@ -14370,7 +14447,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx01x100001xxxxxxxxxxxxx
orqv. */
- return 3323;
+ return 3330;
}
}
else
@@ -14381,7 +14458,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x0101001xxxxxxxxxxxxx
addqv. */
- return 3310;
+ return 3317;
}
else
{
@@ -14391,7 +14468,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx001101001xxxxxxxxxxxxx
umaxqv. */
- return 3314;
+ return 3321;
}
else
{
@@ -14399,7 +14476,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011101001xxxxxxxxxxxxx
eorqv. */
- return 3316;
+ return 3323;
}
}
}
@@ -14436,7 +14513,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx00x110001xxxxxxxxxxxxx
sminqv. */
- return 3313;
+ return 3320;
}
else
{
@@ -14444,7 +14521,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx01x110001xxxxxxxxxxxxx
andqv. */
- return 3311;
+ return 3318;
}
}
}
@@ -14464,7 +14541,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0xx111001xxxxxxxxxxxxx
uminqv. */
- return 3315;
+ return 3322;
}
}
}
@@ -15208,7 +15285,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x0x00xxxxx101xxxxxxxxxxxxx
ld1q. */
- return 3339;
+ return 3346;
}
else
{
@@ -16222,7 +16299,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x00xxxxxxxxxx
zipq1. */
- return 3329;
+ return 3336;
}
else
{
@@ -16232,7 +16309,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111010xxxxxxxxxx
uzpq1. */
- return 3327;
+ return 3334;
}
else
{
@@ -16240,7 +16317,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111110xxxxxxxxxx
tblq. */
- return 3324;
+ return 3331;
}
}
}
@@ -16252,7 +16329,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x01xxxxxxxxxx
zipq2. */
- return 3330;
+ return 3337;
}
else
{
@@ -16260,7 +16337,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x11xxxxxxxxxx
uzpq2. */
- return 3328;
+ return 3335;
}
}
}
@@ -16740,7 +16817,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0x00xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3348;
+ return 3355;
}
else
{
@@ -16750,7 +16827,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0010xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3347;
+ return 3354;
}
else
{
@@ -16758,7 +16835,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0110xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3349;
+ return 3356;
}
}
}
@@ -17205,7 +17282,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0x0000101xxxxxxxxxxxxx
faddqv. */
- return 3317;
+ return 3324;
}
else
{
@@ -17222,7 +17299,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx100101xxxxxxxxxxxxx
fmaxnmqv. */
- return 3318;
+ return 3325;
}
}
else
@@ -17263,7 +17340,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx110101xxxxxxxxxxxxx
fmaxqv. */
- return 3319;
+ return 3326;
}
}
}
@@ -17285,7 +17362,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx101101xxxxxxxxxxxxx
fminnmqv. */
- return 3320;
+ return 3327;
}
}
else
@@ -17304,7 +17381,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx111101xxxxxxxxxxxxx
fminqv. */
- return 3321;
+ return 3328;
}
}
}
@@ -17424,7 +17501,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx01xxxx111xxxxxxxxxxxxx
ld2q. */
- return 3340;
+ return 3347;
}
}
}
@@ -17560,7 +17637,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx1xxxxx100xxxxxxxxxxxxx
ld2q. */
- return 3343;
+ return 3350;
}
}
else
@@ -17705,7 +17782,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x00x1xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3350;
+ return 3357;
}
}
else
@@ -17748,7 +17825,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0101xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3351;
+ return 3358;
}
}
else
@@ -17789,7 +17866,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0111xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3352;
+ return 3359;
}
}
}
@@ -17818,7 +17895,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3439;
+ return 3446;
}
}
else
@@ -17827,7 +17904,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3441;
+ return 3448;
}
}
else
@@ -17868,7 +17945,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3451;
+ return 3458;
}
}
else
@@ -17901,7 +17978,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3437;
+ return 3444;
}
}
else
@@ -17972,7 +18049,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3442;
+ return 3449;
}
}
else
@@ -17981,7 +18058,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3438;
+ return 3445;
}
}
else
@@ -17990,7 +18067,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3443;
+ return 3450;
}
}
else
@@ -17999,7 +18076,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3444;
+ return 3451;
}
}
else
@@ -18026,7 +18103,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3440;
+ return 3447;
}
}
else
@@ -18044,7 +18121,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3447;
+ return 3454;
}
}
else
@@ -18053,7 +18130,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3450;
+ return 3457;
}
}
else
@@ -18086,7 +18163,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3436;
+ return 3443;
}
}
else
@@ -18095,7 +18172,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3445;
+ return 3452;
}
}
else
@@ -18127,7 +18204,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3449;
+ return 3456;
}
}
else
@@ -18426,7 +18503,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0xx1xxxxx001xxxxxxxxxxxxx
st1q. */
- return 3346;
+ return 3353;
}
}
else
@@ -18441,7 +18518,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3446;
+ return 3453;
}
else
{
@@ -18449,7 +18526,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1011xxxxxxxxxxxx
fmlalltt. */
- return 3448;
+ return 3455;
}
}
else
@@ -19167,7 +19244,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001010x0001110xxxxxxxxxx
pmov. */
- return 3331;
+ return 3338;
}
else
{
@@ -19175,7 +19252,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001011x0001110xxxxxxxxxx
pmov. */
- return 3332;
+ return 3339;
}
}
else
@@ -19184,7 +19261,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x101101xx0001110xxxxxxxxxx
pmov. */
- return 3333;
+ return 3340;
}
}
else
@@ -19193,7 +19270,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x11x101xx0001110xxxxxxxxxx
pmov. */
- return 3334;
+ return 3341;
}
}
else
@@ -19239,7 +19316,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001x10x1001110xxxxxxxxxx
pmov. */
- return 3335;
+ return 3342;
}
else
{
@@ -19247,7 +19324,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001x11x1001110xxxxxxxxxx
pmov. */
- return 3336;
+ return 3343;
}
}
else
@@ -19256,7 +19333,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1011x1xx1001110xxxxxxxxxx
pmov. */
- return 3337;
+ return 3344;
}
}
else
@@ -19265,7 +19342,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x11x1x1xx1001110xxxxxxxxxx
pmov. */
- return 3338;
+ return 3345;
}
}
}
@@ -19284,7 +19361,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1x01xxxxx001001xxxxxxxxxx
dupq. */
- return 3322;
+ return 3329;
}
else
{
@@ -19292,7 +19369,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1x11xxxxx001001xxxxxxxxxx
extq. */
- return 3326;
+ return 3333;
}
}
else
@@ -19301,7 +19378,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1xx1xxxxx001101xxxxxxxxxx
tbxq. */
- return 3325;
+ return 3332;
}
}
else
@@ -20904,7 +20981,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101100xxxxxxxxxx
luti2. */
- return 3408;
+ return 3415;
}
}
else
@@ -20913,7 +20990,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x10xxxxxxxxxx
luti2. */
- return 3409;
+ return 3416;
}
}
else
@@ -20926,7 +21003,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101001xxxxxxxxxx
luti4. */
- return 3410;
+ return 3417;
}
else
{
@@ -20934,7 +21011,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101101xxxxxxxxxx
luti4. */
- return 3411;
+ return 3418;
}
}
else
@@ -20943,7 +21020,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x11xxxxxxxxxx
luti4. */
- return 3412;
+ return 3419;
}
}
}
@@ -21894,7 +21971,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x00xxxxxxxxxx
f1cvt. */
- return 3370;
+ return 3377;
}
else
{
@@ -21902,7 +21979,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x10xxxxxxxxxx
bf1cvt. */
- return 3366;
+ return 3373;
}
}
else
@@ -21913,7 +21990,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x01xxxxxxxxxx
f2cvt. */
- return 3371;
+ return 3378;
}
else
{
@@ -21921,7 +21998,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x11xxxxxxxxxx
bf2cvt. */
- return 3367;
+ return 3374;
}
}
}
@@ -21966,7 +22043,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x00xxxxxxxxxx
fcvtn. */
- return 3375;
+ return 3382;
}
else
{
@@ -21974,7 +22051,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x10xxxxxxxxxx
bfcvtn. */
- return 3374;
+ return 3381;
}
}
else
@@ -21985,7 +22062,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x01xxxxxxxxxx
fcvtnb. */
- return 3376;
+ return 3383;
}
else
{
@@ -21993,7 +22070,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x11xxxxxxxxxx
fcvtnt. */
- return 3377;
+ return 3384;
}
}
}
@@ -22054,7 +22131,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x00xxxxxxxxxx
f1cvtlt. */
- return 3372;
+ return 3379;
}
else
{
@@ -22062,7 +22139,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x10xxxxxxxxxx
bf1cvtlt. */
- return 3368;
+ return 3375;
}
}
else
@@ -22073,7 +22150,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x01xxxxxxxxxx
f2cvtlt. */
- return 3373;
+ return 3380;
}
else
{
@@ -22081,7 +22158,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x11xxxxxxxxxx
bf2cvtlt. */
- return 3369;
+ return 3376;
}
}
}
@@ -23407,7 +23484,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x01xxxx111xxxxxxxxxxxxx
ld3q. */
- return 3341;
+ return 3348;
}
else
{
@@ -23415,7 +23492,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x01xxxx111xxxxxxxxxxxxx
ld4q. */
- return 3342;
+ return 3349;
}
}
}
@@ -24588,7 +24665,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x1xxxxx100xxxxxxxxxxxxx
ld3q. */
- return 3344;
+ return 3351;
}
else
{
@@ -24596,7 +24673,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x1xxxxx100xxxxxxxxxxxxx
ld4q. */
- return 3345;
+ return 3352;
}
}
else
@@ -26661,7 +26738,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110100xxxxxxxx100xxxxxxxxxx
luti2. */
- return 3404;
+ return 3411;
}
}
}
@@ -26675,7 +26752,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxxxx000xxxxxxxxxx
luti4. */
- return 3406;
+ return 3413;
}
else
{
@@ -26683,7 +26760,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxxxx100xxxxxxxxxx
luti4. */
- return 3407;
+ return 3414;
}
}
else
@@ -26692,7 +26769,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110110xxxxxxxxx00xxxxxxxxxx
luti2. */
- return 3405;
+ return 3412;
}
}
}
@@ -26808,7 +26885,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx10001xxxxxxxxxx
fmlallbb. */
- return 3428;
+ return 3435;
}
else
{
@@ -26816,7 +26893,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx10001xxxxxxxxxx
fmlalltb. */
- return 3430;
+ return 3437;
}
}
else
@@ -26827,7 +26904,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x10xxxxxx10001xxxxxxxxxx
fmlallbt. */
- return 3429;
+ return 3436;
}
else
{
@@ -26835,7 +26912,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x10xxxxxx10001xxxxxxxxxx
fmlalltt. */
- return 3431;
+ return 3438;
}
}
}
@@ -26923,7 +27000,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3361;
+ return 3368;
}
else
{
@@ -26931,7 +27008,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx11101xxxxxxxxxx
fcvtn2. */
- return 3362;
+ return 3369;
}
}
else
@@ -26940,7 +27017,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x10xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3363;
+ return 3370;
}
}
}
@@ -27083,7 +27160,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x00xxxxxx11111xxxxxxxxxx
fdot. */
- return 3420;
+ return 3427;
}
else
{
@@ -27093,7 +27170,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxx11111xxxxxxxxxx
fdot. */
- return 3422;
+ return 3429;
}
else
{
@@ -27103,7 +27180,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110110xxxxxx11111xxxxxxxxxx
fmlalb. */
- return 3424;
+ return 3431;
}
else
{
@@ -27111,7 +27188,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110110xxxxxx11111xxxxxxxxxx
fmlalt. */
- return 3425;
+ return 3432;
}
}
}
@@ -27385,7 +27462,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx101110110xxxxx0x1111xxxxxxxxxx
fscale. */
- return 3364;
+ return 3371;
}
}
}
@@ -28777,7 +28854,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110001xxxx1011110xxxxxxxxxx
f1cvtl. */
- return 3357;
+ return 3364;
}
else
{
@@ -28785,7 +28862,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110001xxxx1011110xxxxxxxxxx
f1cvtl2. */
- return 3358;
+ return 3365;
}
}
else
@@ -28796,7 +28873,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110101xxxx1011110xxxxxxxxxx
bf1cvtl. */
- return 3353;
+ return 3360;
}
else
{
@@ -28804,7 +28881,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110101xxxx1011110xxxxxxxxxx
bf1cvtl2. */
- return 3354;
+ return 3361;
}
}
}
@@ -28818,7 +28895,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110011xxxx1011110xxxxxxxxxx
f2cvtl. */
- return 3359;
+ return 3366;
}
else
{
@@ -28826,7 +28903,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110011xxxx1011110xxxxxxxxxx
f2cvtl2. */
- return 3360;
+ return 3367;
}
}
else
@@ -28837,7 +28914,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110111xxxx1011110xxxxxxxxxx
bf2cvtl. */
- return 3355;
+ return 3362;
}
else
{
@@ -28845,7 +28922,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110111xxxx1011110xxxxxxxxxx
bf2cvtl2. */
- return 3356;
+ return 3363;
}
}
}
@@ -30844,7 +30921,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx1011101x1xxxxx111111xxxxxxxxxx
fscale. */
- return 3365;
+ return 3372;
}
}
}
@@ -32560,7 +32637,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111100xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3421;
+ return 3428;
}
else
{
@@ -32590,7 +32667,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111101xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3423;
+ return 3430;
}
else
{
@@ -32600,7 +32677,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x000111111xxxxxx0000x0xxxxxxxxxx
fmlalb. */
- return 3426;
+ return 3433;
}
else
{
@@ -32608,7 +32685,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x100111111xxxxxx0000x0xxxxxxxxxx
fmlalt. */
- return 3427;
+ return 3434;
}
}
}
@@ -33150,7 +33227,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010111100xxxxxx1000x0xxxxxxxxxx
fmlallbb. */
- return 3432;
+ return 3439;
}
else
{
@@ -33158,7 +33235,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x110111100xxxxxx1000x0xxxxxxxxxx
fmlalltb. */
- return 3434;
+ return 3441;
}
}
else
@@ -33189,7 +33266,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101111x1xxxxxx1000x0xxxxxxxxxx
fmlallbt. */
- return 3433;
+ return 3440;
}
else
{
@@ -33197,7 +33274,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101111x1xxxxxx1000x0xxxxxxxxxx
fmlalltt. */
- return 3435;
+ return 3442;
}
}
}
@@ -34670,29 +34747,29 @@ aarch64_extract_operand (const aarch64_operand *self,
case 214:
case 215:
case 216:
- case 225:
case 226:
case 227:
case 228:
case 229:
- case 240:
- case 244:
- case 249:
- case 257:
+ case 230:
+ case 241:
+ case 245:
+ case 250:
case 258:
case 259:
- case 266:
+ case 260:
case 267:
case 268:
case 269:
- case 303:
- case 307:
+ case 270:
+ case 304:
+ case 308:
return aarch64_ext_regno (self, info, code, inst, errors);
case 6:
case 119:
case 120:
- case 313:
- case 316:
+ case 314:
+ case 317:
return aarch64_ext_none (self, info, code, inst, errors);
case 11:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -34712,17 +34789,16 @@ aarch64_extract_operand (const aarch64_operand *self,
case 37:
case 38:
case 39:
- case 318:
+ case 319:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 40:
case 41:
case 42:
- case 230:
case 231:
- case 234:
- case 270:
+ case 232:
+ case 235:
case 271:
- case 286:
+ case 272:
case 287:
case 288:
case 289:
@@ -34739,12 +34815,13 @@ aarch64_extract_operand (const aarch64_operand *self,
case 300:
case 301:
case 302:
- case 304:
+ case 303:
case 305:
case 306:
- case 308:
+ case 307:
case 309:
case 310:
+ case 311:
return aarch64_ext_simple_index (self, info, code, inst, errors);
case 43:
return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -34795,14 +34872,14 @@ aarch64_extract_operand (const aarch64_operand *self,
case 210:
case 211:
case 212:
- case 272:
- case 311:
+ case 273:
case 312:
- case 314:
+ case 313:
case 315:
- case 317:
- case 322:
+ case 316:
+ case 318:
case 323:
+ case 324:
return aarch64_ext_imm (self, info, code, inst, errors);
case 52:
case 53:
@@ -34953,7 +35030,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 201:
case 202:
case 203:
- case 285:
+ case 286:
return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
case 217:
case 218:
@@ -34965,67 +35042,69 @@ aarch64_extract_operand (const aarch64_operand *self,
case 223:
case 224:
return aarch64_ext_sme_za_vrs2 (self, info, code, inst, errors);
- case 232:
+ case 225:
+ return aarch64_ext_sme_za_tile_to_vec (self, info, code, inst, errors);
case 233:
- case 235:
+ case 234:
case 236:
case 237:
case 238:
case 239:
+ case 240:
return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
- case 241:
case 242:
- return aarch64_ext_sve_index (self, info, code, inst, errors);
case 243:
- case 245:
- case 265:
- return aarch64_ext_sve_reglist (self, info, code, inst, errors);
+ return aarch64_ext_sve_index (self, info, code, inst, errors);
+ case 244:
case 246:
+ case 266:
+ return aarch64_ext_sve_reglist (self, info, code, inst, errors);
case 247:
- case 250:
+ case 248:
case 251:
case 252:
case 253:
case 254:
- case 264:
- return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
- case 248:
case 255:
+ case 265:
+ return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
+ case 249:
case 256:
+ case 257:
return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors);
- case 260:
- case 262:
- case 273:
- return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
case 261:
case 263:
- return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 274:
+ return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
+ case 262:
+ case 264:
+ return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 275:
case 276:
case 277:
case 278:
case 279:
case 280:
- return aarch64_ext_sme_za_array (self, info, code, inst, errors);
case 281:
- return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+ return aarch64_ext_sme_za_array (self, info, code, inst, errors);
case 282:
- return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
+ return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 283:
- return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
case 284:
+ return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 285:
return aarch64_ext_plain_shrimm (self, info, code, inst, errors);
- case 319:
case 320:
case 321:
+ case 322:
return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
- case 324:
case 325:
case 326:
case 327:
- return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 328:
+ return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 329:
return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 926b310461f..953ee11549b 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -249,6 +249,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsh_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_ZAn,FLD_ol}, "1 bit ZA tile"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrss_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_off2}, "2 bit ZA tile"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsd_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_ZAn_3}, "3 bit ZA tile"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_ARRAY4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv}, "ZA tile to vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_5}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_16}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register"},
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v1 5/6] aarch64: Add support for sme2.1 zero instructions.
2024-07-08 15:36 [PATCH v1 0/6] Binutils] aarch64: Add support for sme2p1 instructions Srinath Parvathaneni
` (3 preceding siblings ...)
2024-07-08 15:36 ` [PATCH v1 4/6] aarch64: Add support for sme2.1 movaz instructions (regenerated files) Srinath Parvathaneni
@ 2024-07-08 15:36 ` Srinath Parvathaneni
2024-07-08 15:36 ` [PATCH v1 6/6] aarch64: Add support for sme2.1 zero instructions (regenerated files) Srinath Parvathaneni
2024-07-12 14:47 ` [PATCH v1 0/6] Binutils] aarch64: Add support for sme2p1 instructions Richard Earnshaw (lists)
6 siblings, 0 replies; 10+ messages in thread
From: Srinath Parvathaneni @ 2024-07-08 15:36 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 1560 bytes --]
This patch adds support for following sme2.1 zero instructions and
the spec is available here [1].
1. ZERO (single-vector).
2. ZERO (double-vector).
3. ZERO (quad-vector).
The VECTOR GROUP symbols VGx2 and VGx4 are optional for the assembler
for most of the sme and sve instructions. But for few of the sme2.1
zero instruction variants VECTOR GROUP symbols VGx2 and VGx4 are mandatory.
To address this a bit "F_VG_REQ" is introduced in this patch, on setting
F_VG_REQ bit in flags of aarch64_opcode forces the assembler to accept
instruction operand only having VECTOR GROUP symbols.
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en
---
gas/testsuite/gas/aarch64/sme-4-illegal.l | 2 +-
gas/testsuite/gas/aarch64/sme2p1-5-bad.d | 4 +
gas/testsuite/gas/aarch64/sme2p1-5-bad.l | 103 ++++++++++++++++++++++
gas/testsuite/gas/aarch64/sme2p1-5-bad.s | 54 ++++++++++++
gas/testsuite/gas/aarch64/sme2p1-5.d | 54 ++++++++++++
gas/testsuite/gas/aarch64/sme2p1-5.s | 54 ++++++++++++
include/opcode/aarch64.h | 11 ++-
opcodes/aarch64-opc.c | 60 ++++++++-----
opcodes/aarch64-tbl.h | 18 ++++
9 files changed, 336 insertions(+), 24 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-5-bad.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-5-bad.l
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-5-bad.s
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-5.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p1-5.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0005-aarch64-Add-support-for-sme2.1-zero-instructions.patch --]
[-- Type: text/x-patch; name="v1-0005-aarch64-Add-support-for-sme2.1-zero-instructions.patch", Size: 20675 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.l b/gas/testsuite/gas/aarch64/sme-4-illegal.l
index a9e98524067..db52529e3e1 100644
--- a/gas/testsuite/gas/aarch64/sme-4-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-4-illegal.l
@@ -1,5 +1,5 @@
[^:]*: Assembler messages:
-[^:]*:[0-9]+: Error: expected '{' at operand 1 -- `zero za'
+[^:]*:[0-9]+: Error: expected '\[' at operand 1 -- `zero za'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za8\.d}'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za0\.d,za8.d}'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za2\.h}'
diff --git a/gas/testsuite/gas/aarch64/sme2p1-5-bad.d b/gas/testsuite/gas/aarch64/sme2p1-5-bad.d
new file mode 100644
index 00000000000..86a6834546e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-5-bad.d
@@ -0,0 +1,4 @@
+#name: Negative test of SME2.1 ZERO instructions.
+#as: -march=armv9.4-a+sme2p1
+#source: sme2p1-5-bad.s
+#error_output: sme2p1-5-bad.l
diff --git a/gas/testsuite/gas/aarch64/sme2p1-5-bad.l b/gas/testsuite/gas/aarch64/sme2p1-5-bad.l
new file mode 100644
index 00000000000..959864a9809
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-5-bad.l
@@ -0,0 +1,103 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `zero za.s\[w8,0,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 0, vgx2\]
+.*: Error: operand mismatch -- `zero za.b\[w14,0,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w14, 0, vgx2\]
+.*: Error: expected a selection register in the range w8-w11 at operand 1 -- `zero za.d\[w2,7,vgx2\]'
+.*: Error: immediate offset out of range 0 to 7 at operand 1 -- `zero za.d\[w11,17,vgx2\]'
+.*: Error: invalid vector group size at operand 1 -- `zero za.d\[w9,4,vgx3\]'
+.*: Error: operand mismatch -- `zero za.h\[w10,3\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w10, 3\]
+.*: Error: operand mismatch -- `zero za.s\[w18,0,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0, vgx4\]
+.*: Error: operand mismatch -- `zero za.b\[w1,0,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0, vgx4\]
+.*: Error: operand mismatch -- `zero za.q\[w8,17,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 17, vgx2\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w11,7,vgx3\]'
+.*: Error: expected a constant immediate offset at operand 1 -- `zero za.s\[w9,vg\]'
+.*: Error: operand mismatch -- `zero za.b\[w10,3\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w10, 3\]
+.*: Error: operand mismatch -- `zero za.s\[w18,0:1\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0:1\]
+.*: Error: operand mismatch -- `zero za.s\[w1,0:1\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0:1\]
+.*: Error: operand mismatch -- `zero za.b\[w8,4:5\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 4:5\]
+.*: Error: operand mismatch -- `zero za.b\[w11,1:5\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w11, 1:5\]
+.*: Error: operand mismatch -- `zero za.h\[w9,2:13\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w9, 2:13\]
+.*: Error: the last offset is less than the first offset at operand 1 -- `zero za.h\[w10,16:7\]'
+.*: Error: operand mismatch -- `zero za.s\[w18,0:3,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0:3, vgx2\]
+.*: Error: operand mismatch -- `zero za.b\[w1,0:1,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0:1, vgx4\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w8,6:7,vg\]'
+.*: Error: invalid vector group size at operand 1 -- `zero za.q\[w9,12:13,vgx3\]'
+.*: Error: operand mismatch -- `zero za.s\[w18,0:1,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0:1, vgx4\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w1,0:1,vgx3\]'
+.*: Error: operand mismatch -- `zero za.b\[w8,16:17,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 16:17, vgx4\]
+.*: Error: operand mismatch -- `zero za.q\[w9,12:13\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w9, 12:13\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.s\[w18,0:3,\]'
+.*: Error: operand mismatch -- `zero za.s\[w1,0:3\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0:3\]
+.*: Error: operand mismatch -- `zero za.b\[w8,8:11\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 8:11\]
+.*: Error: the last offset is less than the first offset at operand 1 -- `zero za.b\[w11,18:1,vgx3\]'
+.*: Error: operand mismatch -- `zero za.h\[w9,4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w9, 4\]
+.*: Error: operand mismatch -- `zero za.h\[w10,10:13\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w10, 10:13\]
+.*: Error: operand mismatch -- `zero za.s\[w18,0:3,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0:3, vgx2\]
+.*: Error: operand mismatch -- `zero za.s\[w1,0:3,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0:3, vgx2\]
+.*: Error: operand mismatch -- `zero za.b\[w8,14:17,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 14:17, vgx2\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.b\[w11,4:7,vg\]'
+.*: Error: operand mismatch -- `zero za.h\[w9,0:3\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w9, 0:3\]
+.*: Error: expected a constant immediate offset at operand 1 -- `zero za.q\[w10,vgx2\]'
+.*: Error: operand mismatch -- `zero za.s\[w18,0:3,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0:3, vgx4\]
+.*: Error: operand mismatch -- `zero za.s\[w1,0:3,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0:3, vgx4\]
+.*: Error: operand mismatch -- `zero za.b\[w8,14:17,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 14:17, vgx4\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.b\[w11,4:7,vg\]'
+.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w9,0:3,vgx3\]'
+.*: Error: operand mismatch -- `zero za.q\[w10,4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w10, 4\]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-5-bad.s b/gas/testsuite/gas/aarch64/sme2p1-5-bad.s
new file mode 100644
index 00000000000..5b69634e5b2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-5-bad.s
@@ -0,0 +1,54 @@
+/* ZERO (single-vector). */
+zero za.s[w8, 0, vgx2]
+zero za.b[w14, 0, vgx2]
+zero za.d[w2, 7, vgx2]
+zero za.d[w11, 17, vgx2]
+zero za.d[w9, 4, vgx3]
+zero za.h[w10, 3]
+
+zero za.s[w18, 0, vgx4]
+zero za.b[w1, 0, vgx4]
+zero za.q[w8, 17, vgx2]
+zero za.h[w11, 7, vgx3]
+zero za.s[w9, vg]
+zero za.b[w10, 3]
+
+/* ZERO (double-vector). */
+zero za.s[w18, 0:1]
+zero za.s[w1, 0:1]
+zero za.b[w8, 4:5]
+zero za.b[w11, 1:5]
+zero za.h[w9, 2:13]
+zero za.h[w10, 16:7]
+
+zero za.s[w18, 0:3, vgx2]
+zero za.b[w1, 0:1, vgx4]
+zero za.h[w8, 6:7, vg]
+zero za.q[w9, 12:13, vgx3]
+
+zero za.s[w18, 0:1, vgx4]
+zero za.h[w1, 0:1, vgx3]
+zero za.b[w8, 16:17, vgx4]
+zero za.q[w9, 12:13]
+
+/* ZERO (quad-vector). */
+zero za.s[w18, 0:3,]
+zero za.s[w1, 0:3]
+zero za.b[w8, 8:11]
+zero za.b[w11, 18:1, vgx3]
+zero za.h[w9, 4]
+zero za.h[w10, 10:13]
+
+zero za.s[w18, 0:3, vgx2]
+zero za.s[w1, 0:3, vgx2]
+zero za.b[w8, 14:17, vgx2]
+zero za.b[w11, 4:7, vg]
+zero za.h[w9, 0:3]
+zero za.q[w10, vgx2]
+
+zero za.s[w18, 0:3, vgx4]
+zero za.s[w1, 0:3, vgx4]
+zero za.b[w8, 14:17, vgx4]
+zero za.b[w11, 4:7, vg]
+zero za.h[w9, 0:3, vgx3]
+zero za.q[w10, 4]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-5.d b/gas/testsuite/gas/aarch64/sme2p1-5.d
new file mode 100644
index 00000000000..f63a171d461
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-5.d
@@ -0,0 +1,54 @@
+#name: Test of SME2.1 ZERO instructions.
+#as: -march=armv9.4-a+sme2p1
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: c00c0000 zero za.d\[w8, 0, vgx2\]
+.*: c00c6000 zero za.d\[w11, 0, vgx2\]
+.*: c00c0007 zero za.d\[w8, 7, vgx2\]
+.*: c00c6007 zero za.d\[w11, 7, vgx2\]
+.*: c00c2004 zero za.d\[w9, 4, vgx2\]
+.*: c00c4003 zero za.d\[w10, 3, vgx2\]
+.*: c00e0000 zero za.d\[w8, 0, vgx4\]
+.*: c00e6000 zero za.d\[w11, 0, vgx4\]
+.*: c00e0007 zero za.d\[w8, 7, vgx4\]
+.*: c00e6007 zero za.d\[w11, 7, vgx4\]
+.*: c00e2004 zero za.d\[w9, 4, vgx4\]
+.*: c00e4003 zero za.d\[w10, 3, vgx4\]
+.*: c00c8000 zero za.d\[w8, 0:1\]
+.*: c00ce000 zero za.d\[w11, 0:1\]
+.*: c00c8007 zero za.d\[w8, 14:15\]
+.*: c00ce007 zero za.d\[w11, 14:15\]
+.*: c00ca001 zero za.d\[w9, 2:3\]
+.*: c00cc003 zero za.d\[w10, 6:7\]
+.*: c00d0000 zero za.d\[w8, 0:1, vgx2\]
+.*: c00d6000 zero za.d\[w11, 0:1, vgx2\]
+.*: c00d0003 zero za.d\[w8, 6:7, vgx2\]
+.*: c00d2001 zero za.d\[w9, 2:3, vgx2\]
+.*: c00d8000 zero za.d\[w8, 0:1, vgx4\]
+.*: c00de000 zero za.d\[w11, 0:1, vgx4\]
+.*: c00d8003 zero za.d\[w8, 6:7, vgx4\]
+.*: c00da001 zero za.d\[w9, 2:3, vgx4\]
+.*: c00e8000 zero za.d\[w8, 0:3\]
+.*: c00ee000 zero za.d\[w11, 0:3\]
+.*: c00e8002 zero za.d\[w8, 8:11\]
+.*: c00ee002 zero za.d\[w11, 8:11\]
+.*: c00ea001 zero za.d\[w9, 4:7\]
+.*: c00ec000 zero za.d\[w10, 0:3\]
+.*: c00f0000 zero za.d\[w8, 0:3, vgx2\]
+.*: c00f6000 zero za.d\[w11, 0:3, vgx2\]
+.*: c00f0001 zero za.d\[w8, 4:7, vgx2\]
+.*: c00f6001 zero za.d\[w11, 4:7, vgx2\]
+.*: c00f2000 zero za.d\[w9, 0:3, vgx2\]
+.*: c00f4001 zero za.d\[w10, 4:7, vgx2\]
+.*: c00f8000 zero za.d\[w8, 0:3, vgx4\]
+.*: c00fe000 zero za.d\[w11, 0:3, vgx4\]
+.*: c00f8001 zero za.d\[w8, 4:7, vgx4\]
+.*: c00fe001 zero za.d\[w11, 4:7, vgx4\]
+.*: c00fa000 zero za.d\[w9, 0:3, vgx4\]
+.*: c00fc001 zero za.d\[w10, 4:7, vgx4\]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-5.s b/gas/testsuite/gas/aarch64/sme2p1-5.s
new file mode 100644
index 00000000000..bd25682d2ef
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-5.s
@@ -0,0 +1,54 @@
+/* ZERO (single-vector). */
+zero za.d[w8, 0, vgx2]
+zero za.d[w11, 0, vgx2]
+zero za.d[w8, 7, vgx2]
+zero za.d[w11, 7, vgx2]
+zero za.d[w9, 4, vgx2]
+zero za.d[w10, 3, vgx2]
+
+zero za.d[w8, 0, vgx4]
+zero za.d[w11, 0, vgx4]
+zero za.d[w8, 7, vgx4]
+zero za.d[w11, 7, vgx4]
+zero za.d[w9, 4, vgx4]
+zero za.d[w10, 3, vgx4]
+
+/* ZERO (double-vector). */
+zero za.d[w8, 0:1]
+zero za.d[w11, 0:1]
+zero za.d[w8, 14:15]
+zero za.d[w11, 14:15]
+zero za.d[w9, 2:3]
+zero za.d[w10, 6:7]
+
+zero za.d[w8, 0:1, vgx2]
+zero za.d[w11, 0:1, vgx2]
+zero za.d[w8, 6:7, vgx2]
+zero za.d[w9, 2:3, vgx2]
+
+zero za.d[w8, 0:1, vgx4]
+zero za.d[w11, 0:1, vgx4]
+zero za.d[w8, 6:7, vgx4]
+zero za.d[w9, 2:3, vgx4]
+
+/* ZERO (quad-vector). */
+zero za.d[w8, 0:3]
+zero za.d[w11, 0:3]
+zero za.d[w8, 8:11]
+zero za.d[w11, 8:11]
+zero za.d[w9, 4:7]
+zero za.d[w10, 0:3]
+
+zero za.d[w8, 0:3, vgx2]
+zero za.d[w11, 0:3, vgx2]
+zero za.d[w8, 4:7, vgx2]
+zero za.d[w11, 4:7, vgx2]
+zero za.d[w9, 0:3, vgx2]
+zero za.d[w10, 4:7, vgx2]
+
+zero za.d[w8, 0:3, vgx4]
+zero za.d[w11, 0:3, vgx4]
+zero za.d[w8, 4:7, vgx4]
+zero za.d[w11, 4:7, vgx4]
+zero za.d[w9, 0:3, vgx4]
+zero za.d[w10, 4:7, vgx4]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 5a2b99d2bc5..1b01931b0cb 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1387,7 +1387,10 @@ extern const aarch64_opcode aarch64_opcode_table[];
#define F_OPD_SIZE (1ULL << 34)
/* RCPC3 instruction has the field of 'size'. */
#define F_RCPC3_SIZE (1ULL << 35)
-/* Next bit is 36. */
+/* This instruction need VGx2 or VGx4 mandatorily in the operand passed to
+ assembler. */
+#define F_VG_REQ (1ULL << 36)
+/* Next bit is 37. */
/* Instruction constraints. */
/* This instruction has a predication constraint on the instruction at PC+4. */
@@ -1450,6 +1453,12 @@ get_opcode_dependent_value (const aarch64_opcode *opcode)
return (opcode->flags >> 24) & 0x7;
}
+static inline bool
+get_opcode_dependent_vg_status (const aarch64_opcode *opcode)
+{
+ return (opcode->flags >> 36) & 0x1;
+}
+
static inline bool
opcode_has_special_coder (const aarch64_opcode *opcode)
{
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index f65f83a0126..b71d354d4c0 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1629,13 +1629,14 @@ check_reglist (const aarch64_opnd_info *opnd,
- an initial immediate offset that is a multiple of RANGE_SIZE
in the range [0, MAX_VALUE * RANGE_SIZE]
- - a vector group size of GROUP_SIZE. */
+ - a vector group size of GROUP_SIZE.
+ - STATUS_VG for cases where VGx2 or VGx4 is mandatory. */
static bool
check_za_access (const aarch64_opnd_info *opnd,
aarch64_operand_error *mismatch_detail, int idx,
int min_wreg, int max_value, unsigned int range_size,
- int group_size)
+ int group_size, bool status_vg)
{
if (!value_in_range_p (opnd->indexed_za.index.regno, min_wreg, min_wreg + 3))
{
@@ -1687,8 +1688,8 @@ check_za_access (const aarch64_opnd_info *opnd,
}
/* The vector group specifier is optional in assembly code. */
- if (opnd->indexed_za.group_size != 0
- && opnd->indexed_za.group_size != group_size)
+ if (opnd->indexed_za.group_size != group_size
+ && (status_vg || opnd->indexed_za.group_size != 0 ))
{
set_invalid_vg_size (mismatch_detail, idx, group_size);
return false;
@@ -1923,7 +1924,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
size = aarch64_get_qualifier_esize (opnd->qualifier);
max_value = 16 / size - 1;
if (!check_za_access (opnd, mismatch_detail, idx,
- 12, max_value, 1, 0))
+ 12, max_value, 1, 0, get_opcode_dependent_value (opcode)))
return 0;
break;
@@ -1993,93 +1994,108 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
size = aarch64_get_qualifier_esize (opnd->qualifier);
max_value = 16 / size - 1;
if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, 1,
- get_opcode_dependent_value (opcode)))
+ get_opcode_dependent_value (opcode),
+ get_opcode_dependent_vg_status (opcode)))
return 0;
break;
case AARCH64_OPND_SME_ZA_array_off4:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, 1,
- get_opcode_dependent_value (opcode)))
+ get_opcode_dependent_value (opcode),
+ get_opcode_dependent_vg_status (opcode)))
return 0;
break;
case AARCH64_OPND_SME_ZA_array_off3_0:
case AARCH64_OPND_SME_ZA_array_off3_5:
if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 1,
- get_opcode_dependent_value (opcode)))
+ get_opcode_dependent_value (opcode),
+ get_opcode_dependent_vg_status (opcode)))
return 0;
break;
case AARCH64_OPND_SME_ZA_array_off1x4:
if (!check_za_access (opnd, mismatch_detail, idx, 8, 1, 4,
- get_opcode_dependent_value (opcode)))
+ get_opcode_dependent_value (opcode),
+ get_opcode_dependent_vg_status (opcode)))
return 0;
break;
case AARCH64_OPND_SME_ZA_array_off2x2:
if (!check_za_access (opnd, mismatch_detail, idx, 8, 3, 2,
- get_opcode_dependent_value (opcode)))
+ get_opcode_dependent_value (opcode),
+ get_opcode_dependent_vg_status (opcode)))
return 0;
break;
case AARCH64_OPND_SME_ZA_array_off2x4:
if (!check_za_access (opnd, mismatch_detail, idx, 8, 3, 4,
- get_opcode_dependent_value (opcode)))
+ get_opcode_dependent_value (opcode),
+ get_opcode_dependent_vg_status (opcode)))
return 0;
break;
case AARCH64_OPND_SME_ZA_array_off3x2:
if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 2,
- get_opcode_dependent_value (opcode)))
+ get_opcode_dependent_value (opcode),
+ get_opcode_dependent_vg_status (opcode)))
return 0;
break;
case AARCH64_OPND_SME_ZA_array_vrsb_1:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 7, 2,
- get_opcode_dependent_value (opcode)))
+ get_opcode_dependent_value (opcode),
+ get_opcode_dependent_vg_status (opcode)))
return 0;
break;
case AARCH64_OPND_SME_ZA_array_vrsh_1:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 3, 2,
- get_opcode_dependent_value (opcode)))
+ get_opcode_dependent_value (opcode),
+ get_opcode_dependent_vg_status (opcode)))
return 0;
break;
case AARCH64_OPND_SME_ZA_array_vrss_1:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 1, 2,
- get_opcode_dependent_value (opcode)))
+ get_opcode_dependent_value (opcode),
+ get_opcode_dependent_vg_status (opcode)))
return 0;
break;
case AARCH64_OPND_SME_ZA_array_vrsd_1:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 0, 2,
- get_opcode_dependent_value (opcode)))
+ get_opcode_dependent_value (opcode),
+ get_opcode_dependent_vg_status (opcode)))
return 0;
break;
case AARCH64_OPND_SME_ZA_array_vrsb_2:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 3, 4,
- get_opcode_dependent_value (opcode)))
+ get_opcode_dependent_value (opcode),
+ get_opcode_dependent_vg_status (opcode)))
return 0;
break;
case AARCH64_OPND_SME_ZA_array_vrsh_2:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 1, 4,
- get_opcode_dependent_value (opcode)))
+ get_opcode_dependent_value (opcode),
+ get_opcode_dependent_vg_status (opcode)))
return 0;
break;
case AARCH64_OPND_SME_ZA_ARRAY4:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, 1,
- get_opcode_dependent_value (opcode)))
+ get_opcode_dependent_value (opcode),
+ get_opcode_dependent_vg_status (opcode)))
return 0;
break;
case AARCH64_OPND_SME_ZA_array_vrss_2:
case AARCH64_OPND_SME_ZA_array_vrsd_2:
if (!check_za_access (opnd, mismatch_detail, idx, 12, 0, 4,
- get_opcode_dependent_value (opcode)))
+ get_opcode_dependent_value (opcode),
+ get_opcode_dependent_vg_status (opcode)))
return 0;
break;
@@ -2090,8 +2106,8 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
max_value = 16 / num / size;
if (max_value > 0)
max_value -= 1;
- if (!check_za_access (opnd, mismatch_detail, idx,
- 12, max_value, num, 0))
+ if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, num,
+ 0, get_opcode_dependent_value (opcode)))
return 0;
break;
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 38be471965c..d49ad3683b5 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1606,6 +1606,10 @@
{ \
QLF3(S_B,P_Z,NIL), \
}
+#define OP_SVE_D \
+{ \
+ QLF1(S_D), \
+}
#define OP_SVE_DD \
{ \
QLF2(S_D,S_D), \
@@ -6668,6 +6672,20 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2p1_INSN ("movaz", 0xc0c20200, 0xffff1e00, sme2_movaz, 0, OP2 (SVE_Zd, SME_ZA_ARRAY4), OP_SVE_DD, 0, 0),
SME2p1_INSN ("movaz", 0xc0c30200, 0xffff1e00, sme2_movaz, 0, OP2 (SVE_Zd, SME_ZA_ARRAY4), OP_SVE_QQ, 0, 0),
+ /* ZERO (single-vector). */
+ SME2p1_INSN ("zero", 0xc00c0000, 0xffff9ff8, sme2_movaz, 0, OP1 (SME_ZA_array_off3_0), OP_SVE_D, F_OD (2) | F_VG_REQ, 0),
+ SME2p1_INSN ("zero", 0xc00e0000, 0xffff9ff8, sme2_movaz, 0, OP1 (SME_ZA_array_off3_0), OP_SVE_D, F_OD (4) | F_VG_REQ, 0),
+
+ /* ZERO (double-vector). */
+ SME2p1_INSN ("zero", 0xc00c8000, 0xffff9ff8, sme2_movaz, 0, OP1 (SME_ZA_array_off3x2), OP_SVE_D, 0, 0),
+ SME2p1_INSN ("zero", 0xc00d0000, 0xffff9ffc, sme2_movaz, 0, OP1 (SME_ZA_array_off2x2), OP_SVE_D, F_OD (2) | F_VG_REQ, 0),
+ SME2p1_INSN ("zero", 0xc00d8000, 0xffff9ffc, sme2_movaz, 0, OP1 (SME_ZA_array_off2x2), OP_SVE_D, F_OD (4) | F_VG_REQ, 0),
+
+ /* ZERO (quad-vector). */
+ SME2p1_INSN ("zero", 0xc00e8000, 0xffff9ffc, sme2_movaz, 0, OP1 (SME_ZA_array_off2x4), OP_SVE_D, 0, 0),
+ SME2p1_INSN ("zero", 0xc00f0000, 0xffff9ffe, sme2_movaz, 0, OP1 (SME_ZA_array_off1x4), OP_SVE_D, F_OD (2) | F_VG_REQ, 0),
+ SME2p1_INSN ("zero", 0xc00f8000, 0xffff9ffe, sme2_movaz, 0, OP1 (SME_ZA_array_off1x4), OP_SVE_D, F_OD (4) | F_VG_REQ, 0),
+
/* SVE2p1 Instructions. */
SVE2p1_INSN("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
SVE2p1_INSN("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v1 6/6] aarch64: Add support for sme2.1 zero instructions (regenerated files).
2024-07-08 15:36 [PATCH v1 0/6] Binutils] aarch64: Add support for sme2p1 instructions Srinath Parvathaneni
` (4 preceding siblings ...)
2024-07-08 15:36 ` [PATCH v1 5/6] aarch64: Add support for sme2.1 zero instructions Srinath Parvathaneni
@ 2024-07-08 15:36 ` Srinath Parvathaneni
2024-07-12 14:47 ` [PATCH v1 0/6] Binutils] aarch64: Add support for sme2p1 instructions Richard Earnshaw (lists)
6 siblings, 0 replies; 10+ messages in thread
From: Srinath Parvathaneni @ 2024-07-08 15:36 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 228 bytes --]
This patch includes the regenerated files for
aarch64: Add support for sme2.1 zero instructions.
---
opcodes/aarch64-dis-2.c | 460 ++++++++++++++++++++++++----------------
1 file changed, 274 insertions(+), 186 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0006-aarch64-Add-support-for-sme2.1-zero-instructions-.patch --]
[-- Type: text/x-patch; name="v1-0006-aarch64-Add-support-for-sme2.1-zero-instructions-.patch", Size: 129271 bytes --]
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 7a7af4afea2..4138ec8907f 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -271,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3420;
+ return 3428;
}
else
{
@@ -310,7 +310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101x00xxxxxxxxxxxxxx
luti4. */
- return 3421;
+ return 3429;
}
else
{
@@ -408,21 +408,109 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 22) & 0x1) == 0)
{
- if (((word >> 14) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000x00011xxx0xx00xxxxxxxxxx
- luti2. */
- return 2668;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000000011000xxx00xxxxxxxxxx
+ zero. */
+ return 3317;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000000011100xxx00xxxxxxxxxx
+ zero. */
+ return 3318;
+ }
+ }
+ else
+ {
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000000011010xxx00xxxxxxxxxx
+ zero. */
+ return 3320;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000000011110xxx00xxxxxxxxxx
+ zero. */
+ return 3323;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000000011001xxx00xxxxxxxxxx
+ zero. */
+ return 3319;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000000011101xxx00xxxxxxxxxx
+ zero. */
+ return 3322;
+ }
+ }
+ else
+ {
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000000011011xxx00xxxxxxxxxx
+ zero. */
+ return 3321;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000000011111xxx00xxxxxxxxxx
+ zero. */
+ return 3324;
+ }
+ }
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000x00011xxx1xx00xxxxxxxxxx
- luti2. */
- return 2667;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000100011xxx0xx00xxxxxxxxxx
+ luti2. */
+ return 2668;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000100011xxx1xx00xxxxxxxxxx
+ luti2. */
+ return 2667;
+ }
}
}
else
@@ -454,7 +542,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010011x1xxxx00xxxxxxxxxx
movt. */
- return 3422;
+ return 3430;
}
}
else
@@ -1278,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3488;
+ return 3496;
}
else
{
@@ -1286,7 +1374,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3487;
+ return 3495;
}
}
else
@@ -1634,7 +1722,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3481;
+ return 3489;
}
}
}
@@ -1664,7 +1752,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxxxxx1xxxxxx00xxxx
fdot. */
- return 3466;
+ return 3474;
}
}
else
@@ -2036,7 +2124,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3480;
+ return 3488;
}
}
}
@@ -2141,7 +2229,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3473;
+ return 3481;
}
}
}
@@ -2314,7 +2402,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3472;
+ return 3480;
}
}
}
@@ -2356,7 +2444,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3479;
+ return 3487;
}
else
{
@@ -2724,7 +2812,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3459;
+ return 3467;
}
else
{
@@ -2793,7 +2881,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3460;
+ return 3468;
}
else
{
@@ -2872,7 +2960,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3471;
+ return 3479;
}
else
{
@@ -2927,7 +3015,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3490;
+ return 3498;
}
else
{
@@ -2945,7 +3033,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3465;
+ return 3473;
}
}
}
@@ -3019,7 +3107,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3489;
+ return 3497;
}
}
}
@@ -3099,7 +3187,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3491;
+ return 3499;
}
else
{
@@ -3276,7 +3364,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3485;
+ return 3493;
}
else
{
@@ -3284,7 +3372,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3486;
+ return 3494;
}
}
}
@@ -3339,7 +3427,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3483;
+ return 3491;
}
else
{
@@ -3347,7 +3435,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3484;
+ return 3492;
}
}
}
@@ -3401,7 +3489,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3469;
+ return 3477;
}
else
{
@@ -3409,7 +3497,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3470;
+ return 3478;
}
}
}
@@ -3471,7 +3559,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3477;
+ return 3485;
}
else
{
@@ -3479,7 +3567,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3478;
+ return 3486;
}
}
}
@@ -3534,7 +3622,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3475;
+ return 3483;
}
else
{
@@ -3542,7 +3630,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3476;
+ return 3484;
}
}
}
@@ -3611,7 +3699,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3482;
+ return 3490;
}
}
else
@@ -3694,7 +3782,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3474;
+ return 3482;
}
}
else
@@ -3715,7 +3803,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx00xxx
fadd. */
- return 3423;
+ return 3431;
}
}
else
@@ -3734,7 +3822,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx00xxx
fadd. */
- return 3424;
+ return 3432;
}
}
}
@@ -3860,7 +3948,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3463;
+ return 3471;
}
else
{
@@ -3868,7 +3956,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx110xxx
fdot. */
- return 3464;
+ return 3472;
}
}
}
@@ -4159,7 +4247,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx01xxx
fdot. */
- return 3467;
+ return 3475;
}
else
{
@@ -4167,7 +4255,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx01xxx
fdot. */
- return 3468;
+ return 3476;
}
}
}
@@ -4438,7 +4526,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx01xxx
fsub. */
- return 3425;
+ return 3433;
}
}
else
@@ -4457,7 +4545,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx01xxx
fsub. */
- return 3426;
+ return 3434;
}
}
}
@@ -4519,7 +4607,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx11xxx
fdot. */
- return 3461;
+ return 3469;
}
else
{
@@ -4527,7 +4615,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx11xxx
fdot. */
- return 3462;
+ return 3470;
}
}
}
@@ -5062,7 +5150,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3397;
+ return 3405;
}
}
else
@@ -5210,7 +5298,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3394;
+ return 3402;
}
else
{
@@ -5218,7 +5306,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3389;
+ return 3397;
}
}
else
@@ -5227,7 +5315,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3395;
+ return 3403;
}
}
else
@@ -5278,7 +5366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3396;
+ return 3404;
}
}
}
@@ -5361,7 +5449,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3390;
+ return 3398;
}
else
{
@@ -5369,7 +5457,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3391;
+ return 3399;
}
}
else
@@ -5380,7 +5468,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3385;
+ return 3393;
}
else
{
@@ -5388,7 +5476,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3386;
+ return 3394;
}
}
}
@@ -5423,7 +5511,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3392;
+ return 3400;
}
else
{
@@ -5431,7 +5519,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxx10111000xxxxxxxxx1
f2cvtl. */
- return 3393;
+ return 3401;
}
}
else
@@ -5442,7 +5530,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001011xxx10111000xxxxxxxxx1
bf1cvtl. */
- return 3387;
+ return 3395;
}
else
{
@@ -5450,7 +5538,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001111xxx10111000xxxxxxxxx1
bf2cvtl. */
- return 3388;
+ return 3396;
}
}
}
@@ -5719,7 +5807,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1100xx100xxxx0
fscale. */
- return 3399;
+ return 3407;
}
}
else
@@ -5895,7 +5983,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1010xx100xxxx0
fscale. */
- return 3398;
+ return 3406;
}
else
{
@@ -5903,7 +5991,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1110xx100xxxx0
fscale. */
- return 3400;
+ return 3408;
}
}
}
@@ -11071,7 +11159,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3401;
+ return 3409;
}
else
{
@@ -11079,7 +11167,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3402;
+ return 3410;
}
}
}
@@ -11997,7 +12085,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3403;
+ return 3411;
}
else
{
@@ -12005,7 +12093,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3404;
+ return 3412;
}
}
}
@@ -12090,7 +12178,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3405;
+ return 3413;
}
else
{
@@ -12197,7 +12285,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3407;
+ return 3415;
}
else
{
@@ -12402,7 +12490,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3406;
+ return 3414;
}
else
{
@@ -12443,7 +12531,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3408;
+ return 3416;
}
else
{
@@ -14101,7 +14189,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3410;
+ return 3418;
}
}
else
@@ -14131,7 +14219,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3409;
+ return 3417;
}
}
}
@@ -14439,7 +14527,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx00x100001xxxxxxxxxxxxx
smaxqv. */
- return 3319;
+ return 3327;
}
else
{
@@ -14447,7 +14535,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx01x100001xxxxxxxxxxxxx
orqv. */
- return 3330;
+ return 3338;
}
}
else
@@ -14458,7 +14546,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x0101001xxxxxxxxxxxxx
addqv. */
- return 3317;
+ return 3325;
}
else
{
@@ -14468,7 +14556,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx001101001xxxxxxxxxxxxx
umaxqv. */
- return 3321;
+ return 3329;
}
else
{
@@ -14476,7 +14564,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011101001xxxxxxxxxxxxx
eorqv. */
- return 3323;
+ return 3331;
}
}
}
@@ -14513,7 +14601,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx00x110001xxxxxxxxxxxxx
sminqv. */
- return 3320;
+ return 3328;
}
else
{
@@ -14521,7 +14609,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx01x110001xxxxxxxxxxxxx
andqv. */
- return 3318;
+ return 3326;
}
}
}
@@ -14541,7 +14629,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0xx111001xxxxxxxxxxxxx
uminqv. */
- return 3322;
+ return 3330;
}
}
}
@@ -15285,7 +15373,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x0x00xxxxx101xxxxxxxxxxxxx
ld1q. */
- return 3346;
+ return 3354;
}
else
{
@@ -16299,7 +16387,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x00xxxxxxxxxx
zipq1. */
- return 3336;
+ return 3344;
}
else
{
@@ -16309,7 +16397,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111010xxxxxxxxxx
uzpq1. */
- return 3334;
+ return 3342;
}
else
{
@@ -16317,7 +16405,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111110xxxxxxxxxx
tblq. */
- return 3331;
+ return 3339;
}
}
}
@@ -16329,7 +16417,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x01xxxxxxxxxx
zipq2. */
- return 3337;
+ return 3345;
}
else
{
@@ -16337,7 +16425,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x11xxxxxxxxxx
uzpq2. */
- return 3335;
+ return 3343;
}
}
}
@@ -16817,7 +16905,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0x00xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3355;
+ return 3363;
}
else
{
@@ -16827,7 +16915,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0010xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3354;
+ return 3362;
}
else
{
@@ -16835,7 +16923,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0110xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3356;
+ return 3364;
}
}
}
@@ -17282,7 +17370,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0x0000101xxxxxxxxxxxxx
faddqv. */
- return 3324;
+ return 3332;
}
else
{
@@ -17299,7 +17387,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx100101xxxxxxxxxxxxx
fmaxnmqv. */
- return 3325;
+ return 3333;
}
}
else
@@ -17340,7 +17428,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx110101xxxxxxxxxxxxx
fmaxqv. */
- return 3326;
+ return 3334;
}
}
}
@@ -17362,7 +17450,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx101101xxxxxxxxxxxxx
fminnmqv. */
- return 3327;
+ return 3335;
}
}
else
@@ -17381,7 +17469,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx111101xxxxxxxxxxxxx
fminqv. */
- return 3328;
+ return 3336;
}
}
}
@@ -17501,7 +17589,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx01xxxx111xxxxxxxxxxxxx
ld2q. */
- return 3347;
+ return 3355;
}
}
}
@@ -17637,7 +17725,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx1xxxxx100xxxxxxxxxxxxx
ld2q. */
- return 3350;
+ return 3358;
}
}
else
@@ -17782,7 +17870,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x00x1xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3357;
+ return 3365;
}
}
else
@@ -17825,7 +17913,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0101xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3358;
+ return 3366;
}
}
else
@@ -17866,7 +17954,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0111xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3359;
+ return 3367;
}
}
}
@@ -17895,7 +17983,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3446;
+ return 3454;
}
}
else
@@ -17904,7 +17992,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3448;
+ return 3456;
}
}
else
@@ -17945,7 +18033,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3458;
+ return 3466;
}
}
else
@@ -17978,7 +18066,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3444;
+ return 3452;
}
}
else
@@ -18049,7 +18137,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3449;
+ return 3457;
}
}
else
@@ -18058,7 +18146,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3445;
+ return 3453;
}
}
else
@@ -18067,7 +18155,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3450;
+ return 3458;
}
}
else
@@ -18076,7 +18164,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3451;
+ return 3459;
}
}
else
@@ -18103,7 +18191,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3447;
+ return 3455;
}
}
else
@@ -18121,7 +18209,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3454;
+ return 3462;
}
}
else
@@ -18130,7 +18218,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3457;
+ return 3465;
}
}
else
@@ -18163,7 +18251,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3443;
+ return 3451;
}
}
else
@@ -18172,7 +18260,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3452;
+ return 3460;
}
}
else
@@ -18204,7 +18292,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3456;
+ return 3464;
}
}
else
@@ -18503,7 +18591,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0xx1xxxxx001xxxxxxxxxxxxx
st1q. */
- return 3353;
+ return 3361;
}
}
else
@@ -18518,7 +18606,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3453;
+ return 3461;
}
else
{
@@ -18526,7 +18614,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1011xxxxxxxxxxxx
fmlalltt. */
- return 3455;
+ return 3463;
}
}
else
@@ -19244,7 +19332,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001010x0001110xxxxxxxxxx
pmov. */
- return 3338;
+ return 3346;
}
else
{
@@ -19252,7 +19340,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001011x0001110xxxxxxxxxx
pmov. */
- return 3339;
+ return 3347;
}
}
else
@@ -19261,7 +19349,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x101101xx0001110xxxxxxxxxx
pmov. */
- return 3340;
+ return 3348;
}
}
else
@@ -19270,7 +19358,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x11x101xx0001110xxxxxxxxxx
pmov. */
- return 3341;
+ return 3349;
}
}
else
@@ -19316,7 +19404,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001x10x1001110xxxxxxxxxx
pmov. */
- return 3342;
+ return 3350;
}
else
{
@@ -19324,7 +19412,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001x11x1001110xxxxxxxxxx
pmov. */
- return 3343;
+ return 3351;
}
}
else
@@ -19333,7 +19421,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1011x1xx1001110xxxxxxxxxx
pmov. */
- return 3344;
+ return 3352;
}
}
else
@@ -19342,7 +19430,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x11x1x1xx1001110xxxxxxxxxx
pmov. */
- return 3345;
+ return 3353;
}
}
}
@@ -19361,7 +19449,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1x01xxxxx001001xxxxxxxxxx
dupq. */
- return 3329;
+ return 3337;
}
else
{
@@ -19369,7 +19457,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1x11xxxxx001001xxxxxxxxxx
extq. */
- return 3333;
+ return 3341;
}
}
else
@@ -19378,7 +19466,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1xx1xxxxx001101xxxxxxxxxx
tbxq. */
- return 3332;
+ return 3340;
}
}
else
@@ -20981,7 +21069,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101100xxxxxxxxxx
luti2. */
- return 3415;
+ return 3423;
}
}
else
@@ -20990,7 +21078,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x10xxxxxxxxxx
luti2. */
- return 3416;
+ return 3424;
}
}
else
@@ -21003,7 +21091,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101001xxxxxxxxxx
luti4. */
- return 3417;
+ return 3425;
}
else
{
@@ -21011,7 +21099,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101101xxxxxxxxxx
luti4. */
- return 3418;
+ return 3426;
}
}
else
@@ -21020,7 +21108,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x11xxxxxxxxxx
luti4. */
- return 3419;
+ return 3427;
}
}
}
@@ -21971,7 +22059,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x00xxxxxxxxxx
f1cvt. */
- return 3377;
+ return 3385;
}
else
{
@@ -21979,7 +22067,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x10xxxxxxxxxx
bf1cvt. */
- return 3373;
+ return 3381;
}
}
else
@@ -21990,7 +22078,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x01xxxxxxxxxx
f2cvt. */
- return 3378;
+ return 3386;
}
else
{
@@ -21998,7 +22086,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x11xxxxxxxxxx
bf2cvt. */
- return 3374;
+ return 3382;
}
}
}
@@ -22043,7 +22131,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x00xxxxxxxxxx
fcvtn. */
- return 3382;
+ return 3390;
}
else
{
@@ -22051,7 +22139,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x10xxxxxxxxxx
bfcvtn. */
- return 3381;
+ return 3389;
}
}
else
@@ -22062,7 +22150,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x01xxxxxxxxxx
fcvtnb. */
- return 3383;
+ return 3391;
}
else
{
@@ -22070,7 +22158,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x11xxxxxxxxxx
fcvtnt. */
- return 3384;
+ return 3392;
}
}
}
@@ -22131,7 +22219,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x00xxxxxxxxxx
f1cvtlt. */
- return 3379;
+ return 3387;
}
else
{
@@ -22139,7 +22227,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x10xxxxxxxxxx
bf1cvtlt. */
- return 3375;
+ return 3383;
}
}
else
@@ -22150,7 +22238,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x01xxxxxxxxxx
f2cvtlt. */
- return 3380;
+ return 3388;
}
else
{
@@ -22158,7 +22246,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x11xxxxxxxxxx
bf2cvtlt. */
- return 3376;
+ return 3384;
}
}
}
@@ -23484,7 +23572,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x01xxxx111xxxxxxxxxxxxx
ld3q. */
- return 3348;
+ return 3356;
}
else
{
@@ -23492,7 +23580,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x01xxxx111xxxxxxxxxxxxx
ld4q. */
- return 3349;
+ return 3357;
}
}
}
@@ -24665,7 +24753,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x1xxxxx100xxxxxxxxxxxxx
ld3q. */
- return 3351;
+ return 3359;
}
else
{
@@ -24673,7 +24761,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x1xxxxx100xxxxxxxxxxxxx
ld4q. */
- return 3352;
+ return 3360;
}
}
else
@@ -26738,7 +26826,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110100xxxxxxxx100xxxxxxxxxx
luti2. */
- return 3411;
+ return 3419;
}
}
}
@@ -26752,7 +26840,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxxxx000xxxxxxxxxx
luti4. */
- return 3413;
+ return 3421;
}
else
{
@@ -26760,7 +26848,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxxxx100xxxxxxxxxx
luti4. */
- return 3414;
+ return 3422;
}
}
else
@@ -26769,7 +26857,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110110xxxxxxxxx00xxxxxxxxxx
luti2. */
- return 3412;
+ return 3420;
}
}
}
@@ -26885,7 +26973,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx10001xxxxxxxxxx
fmlallbb. */
- return 3435;
+ return 3443;
}
else
{
@@ -26893,7 +26981,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx10001xxxxxxxxxx
fmlalltb. */
- return 3437;
+ return 3445;
}
}
else
@@ -26904,7 +26992,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x10xxxxxx10001xxxxxxxxxx
fmlallbt. */
- return 3436;
+ return 3444;
}
else
{
@@ -26912,7 +27000,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x10xxxxxx10001xxxxxxxxxx
fmlalltt. */
- return 3438;
+ return 3446;
}
}
}
@@ -27000,7 +27088,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3368;
+ return 3376;
}
else
{
@@ -27008,7 +27096,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx11101xxxxxxxxxx
fcvtn2. */
- return 3369;
+ return 3377;
}
}
else
@@ -27017,7 +27105,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x10xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3370;
+ return 3378;
}
}
}
@@ -27160,7 +27248,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x00xxxxxx11111xxxxxxxxxx
fdot. */
- return 3427;
+ return 3435;
}
else
{
@@ -27170,7 +27258,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxx11111xxxxxxxxxx
fdot. */
- return 3429;
+ return 3437;
}
else
{
@@ -27180,7 +27268,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110110xxxxxx11111xxxxxxxxxx
fmlalb. */
- return 3431;
+ return 3439;
}
else
{
@@ -27188,7 +27276,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110110xxxxxx11111xxxxxxxxxx
fmlalt. */
- return 3432;
+ return 3440;
}
}
}
@@ -27462,7 +27550,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx101110110xxxxx0x1111xxxxxxxxxx
fscale. */
- return 3371;
+ return 3379;
}
}
}
@@ -28854,7 +28942,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110001xxxx1011110xxxxxxxxxx
f1cvtl. */
- return 3364;
+ return 3372;
}
else
{
@@ -28862,7 +28950,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110001xxxx1011110xxxxxxxxxx
f1cvtl2. */
- return 3365;
+ return 3373;
}
}
else
@@ -28873,7 +28961,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110101xxxx1011110xxxxxxxxxx
bf1cvtl. */
- return 3360;
+ return 3368;
}
else
{
@@ -28881,7 +28969,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110101xxxx1011110xxxxxxxxxx
bf1cvtl2. */
- return 3361;
+ return 3369;
}
}
}
@@ -28895,7 +28983,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110011xxxx1011110xxxxxxxxxx
f2cvtl. */
- return 3366;
+ return 3374;
}
else
{
@@ -28903,7 +28991,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110011xxxx1011110xxxxxxxxxx
f2cvtl2. */
- return 3367;
+ return 3375;
}
}
else
@@ -28914,7 +29002,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110111xxxx1011110xxxxxxxxxx
bf2cvtl. */
- return 3362;
+ return 3370;
}
else
{
@@ -28922,7 +29010,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110111xxxx1011110xxxxxxxxxx
bf2cvtl2. */
- return 3363;
+ return 3371;
}
}
}
@@ -30921,7 +31009,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx1011101x1xxxxx111111xxxxxxxxxx
fscale. */
- return 3372;
+ return 3380;
}
}
}
@@ -32637,7 +32725,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111100xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3428;
+ return 3436;
}
else
{
@@ -32667,7 +32755,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111101xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3430;
+ return 3438;
}
else
{
@@ -32677,7 +32765,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x000111111xxxxxx0000x0xxxxxxxxxx
fmlalb. */
- return 3433;
+ return 3441;
}
else
{
@@ -32685,7 +32773,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x100111111xxxxxx0000x0xxxxxxxxxx
fmlalt. */
- return 3434;
+ return 3442;
}
}
}
@@ -33227,7 +33315,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010111100xxxxxx1000x0xxxxxxxxxx
fmlallbb. */
- return 3439;
+ return 3447;
}
else
{
@@ -33235,7 +33323,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x110111100xxxxxx1000x0xxxxxxxxxx
fmlalltb. */
- return 3441;
+ return 3449;
}
}
else
@@ -33266,7 +33354,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101111x1xxxxxx1000x0xxxxxxxxxx
fmlallbt. */
- return 3440;
+ return 3448;
}
else
{
@@ -33274,7 +33362,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101111x1xxxxxx1000x0xxxxxxxxxx
fmlalltt. */
- return 3442;
+ return 3450;
}
}
}
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v1 0/6] Binutils] aarch64: Add support for sme2p1 instructions.
2024-07-08 15:36 [PATCH v1 0/6] Binutils] aarch64: Add support for sme2p1 instructions Srinath Parvathaneni
` (5 preceding siblings ...)
2024-07-08 15:36 ` [PATCH v1 6/6] aarch64: Add support for sme2.1 zero instructions (regenerated files) Srinath Parvathaneni
@ 2024-07-12 14:47 ` Richard Earnshaw (lists)
6 siblings, 0 replies; 10+ messages in thread
From: Richard Earnshaw (lists) @ 2024-07-12 14:47 UTC (permalink / raw)
To: Srinath Parvathaneni, binutils; +Cc: nickc
On 08/07/2024 16:36, Srinath Parvathaneni wrote:
> Hi,
>
> This patch series adds the support for aarch64 sme2p1 instructions
> and the spec can be found here [1].
>
> Srinath Parvathaneni (6):
> aarch64: Add support for sme2.1 luti2 and luti4 instructions.
> aarch64: Add support for sme2.1 luti2 and luti4 instructions (regenerated files).
> aarch64: Add support for sme2.1 movaz instructions.
> aarch64: Add support for sme2.1 movaz instructions (regenerated files).
> aarch64: Add support for sme2.1 zero instructions.
> aarch64: Add support for sme2.1 zero instructions (regenerated files).
>
> [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
>
> Ok for binutils-master?
>
> Regards,
> Srinath.
>
> gas/config/tc-aarch64.c | 1 +
> gas/testsuite/gas/aarch64/sme-4-illegal.l | 2 +-
> gas/testsuite/gas/aarch64/sme2p1-2-bad.d | 4 +
> gas/testsuite/gas/aarch64/sme2p1-2-bad.l | 62 ++
> gas/testsuite/gas/aarch64/sme2p1-2-bad.s | 48 ++
> gas/testsuite/gas/aarch64/sme2p1-2.d | 87 +++
> gas/testsuite/gas/aarch64/sme2p1-2.s | 87 +++
> gas/testsuite/gas/aarch64/sme2p1-3-bad.d | 4 +
> gas/testsuite/gas/aarch64/sme2p1-3-bad.l | 30 +
> gas/testsuite/gas/aarch64/sme2p1-3-bad.s | 20 +
> gas/testsuite/gas/aarch64/sme2p1-3.d | 26 +
> gas/testsuite/gas/aarch64/sme2p1-3.s | 19 +
> gas/testsuite/gas/aarch64/sme2p1-4-bad.d | 4 +
> gas/testsuite/gas/aarch64/sme2p1-4-bad.l | 76 +++
> gas/testsuite/gas/aarch64/sme2p1-4-bad.s | 48 ++
> gas/testsuite/gas/aarch64/sme2p1-4.d | 53 ++
> gas/testsuite/gas/aarch64/sme2p1-4.s | 48 ++
> gas/testsuite/gas/aarch64/sme2p1-5-bad.d | 4 +
> gas/testsuite/gas/aarch64/sme2p1-5-bad.l | 103 +++
> gas/testsuite/gas/aarch64/sme2p1-5-bad.s | 54 ++
> gas/testsuite/gas/aarch64/sme2p1-5.d | 54 ++
> gas/testsuite/gas/aarch64/sme2p1-5.s | 54 ++
> include/opcode/aarch64.h | 13 +-
> opcodes/aarch64-asm-2.c | 94 +--
> opcodes/aarch64-asm.c | 47 ++
> opcodes/aarch64-asm.h | 1 +
> opcodes/aarch64-dis-2.c | 753 ++++++++++++++--------
> opcodes/aarch64-dis.c | 55 ++
> opcodes/aarch64-dis.h | 1 +
> opcodes/aarch64-opc-2.c | 1 +
> opcodes/aarch64-opc.c | 71 +-
> opcodes/aarch64-opc.h | 4 +
> opcodes/aarch64-tbl.h | 47 ++
> 33 files changed, 1634 insertions(+), 341 deletions(-)
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-2-bad.d
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-2-bad.l
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-2-bad.s
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-2.d
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-2.s
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.d
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.l
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.s
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3.d
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3.s
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-4-bad.d
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-4-bad.l
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-4-bad.s
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-4.d
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-4.s
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-5-bad.d
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-5-bad.l
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-5-bad.s
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-5.d
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-5.s
>
Rebased and pushed.
Thanks
R.
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v1 3/6] aarch64: Add support for sme2.1 movaz instructions.
2024-07-08 15:36 ` [PATCH v1 3/6] aarch64: Add support for sme2.1 movaz instructions Srinath Parvathaneni
@ 2024-07-15 6:14 ` Jan Beulich
2024-07-15 9:21 ` Srinath Parvathaneni
0 siblings, 1 reply; 10+ messages in thread
From: Jan Beulich @ 2024-07-15 6:14 UTC (permalink / raw)
To: Srinath Parvathaneni, richard.earnshaw; +Cc: nickc, binutils
On 08.07.2024 17:36, Srinath Parvathaneni wrote:
>
> This patch adds support for following sme2.1 movaz instructions and
> the spec is available here [1].
>
> 1. MOVAZ (array to vector, two registers).
> 2. MOVAZ (array to vector, four registers).
> 3. MOVAZ (tile to vector, single).
>
> [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en
> ---
> gas/config/tc-aarch64.c | 1 +
> gas/testsuite/gas/aarch64/sme2p1-3-bad.d | 4 ++
> gas/testsuite/gas/aarch64/sme2p1-3-bad.l | 30 ++++++++++
> gas/testsuite/gas/aarch64/sme2p1-3-bad.s | 20 +++++++
> gas/testsuite/gas/aarch64/sme2p1-3.d | 26 ++++++++
> gas/testsuite/gas/aarch64/sme2p1-3.s | 19 ++++++
> gas/testsuite/gas/aarch64/sme2p1-4-bad.d | 4 ++
> gas/testsuite/gas/aarch64/sme2p1-4-bad.l | 76 ++++++++++++++++++++++++
> gas/testsuite/gas/aarch64/sme2p1-4-bad.s | 48 +++++++++++++++
> gas/testsuite/gas/aarch64/sme2p1-4.d | 53 +++++++++++++++++
> gas/testsuite/gas/aarch64/sme2p1-4.s | 48 +++++++++++++++
> include/opcode/aarch64.h | 1 +
> opcodes/aarch64-asm.c | 43 ++++++++++++++
> opcodes/aarch64-asm.h | 1 +
> opcodes/aarch64-dis.c | 49 +++++++++++++++
> opcodes/aarch64-dis.h | 1 +
> opcodes/aarch64-opc.c | 13 +++-
> opcodes/aarch64-opc.h | 4 ++
> opcodes/aarch64-tbl.h | 19 ++++++
> 19 files changed, 459 insertions(+), 1 deletion(-)
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.d
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.l
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.s
> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3.d
In here expectations are for the optional ", VGx..." to be present. Elsewhere
in disassembly I think optional parts are omitted, at least by default. Except
that I notice that this same construct looks to uniformly be there when SME2
(or newer) insns have it. Perhaps I'm unaware of an earlier discussion on this
...
Jan
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v1 3/6] aarch64: Add support for sme2.1 movaz instructions.
2024-07-15 6:14 ` Jan Beulich
@ 2024-07-15 9:21 ` Srinath Parvathaneni
0 siblings, 0 replies; 10+ messages in thread
From: Srinath Parvathaneni @ 2024-07-15 9:21 UTC (permalink / raw)
To: Jan Beulich, richard.earnshaw; +Cc: nickc, binutils
Hi,
On 7/15/24 07:14, Jan Beulich wrote:
> On 08.07.2024 17:36, Srinath Parvathaneni wrote:
>>
>> This patch adds support for following sme2.1 movaz instructions and
>> the spec is available here [1].
>>
>> 1. MOVAZ (array to vector, two registers).
>> 2. MOVAZ (array to vector, four registers).
>> 3. MOVAZ (tile to vector, single).
>>
>> [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en
>> ---
>> gas/config/tc-aarch64.c | 1 +
>> gas/testsuite/gas/aarch64/sme2p1-3-bad.d | 4 ++
>> gas/testsuite/gas/aarch64/sme2p1-3-bad.l | 30 ++++++++++
>> gas/testsuite/gas/aarch64/sme2p1-3-bad.s | 20 +++++++
>> gas/testsuite/gas/aarch64/sme2p1-3.d | 26 ++++++++
>> gas/testsuite/gas/aarch64/sme2p1-3.s | 19 ++++++
>> gas/testsuite/gas/aarch64/sme2p1-4-bad.d | 4 ++
>> gas/testsuite/gas/aarch64/sme2p1-4-bad.l | 76 ++++++++++++++++++++++++
>> gas/testsuite/gas/aarch64/sme2p1-4-bad.s | 48 +++++++++++++++
>> gas/testsuite/gas/aarch64/sme2p1-4.d | 53 +++++++++++++++++
>> gas/testsuite/gas/aarch64/sme2p1-4.s | 48 +++++++++++++++
>> include/opcode/aarch64.h | 1 +
>> opcodes/aarch64-asm.c | 43 ++++++++++++++
>> opcodes/aarch64-asm.h | 1 +
>> opcodes/aarch64-dis.c | 49 +++++++++++++++
>> opcodes/aarch64-dis.h | 1 +
>> opcodes/aarch64-opc.c | 13 +++-
>> opcodes/aarch64-opc.h | 4 ++
>> opcodes/aarch64-tbl.h | 19 ++++++
>> 19 files changed, 459 insertions(+), 1 deletion(-)
>> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.d
>> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.l
>> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3-bad.s
>> create mode 100644 gas/testsuite/gas/aarch64/sme2p1-3.d
>
> In here expectations are for the optional ", VGx..." to be present. Elsewhere
> in disassembly I think optional parts are omitted, at least by default. Except
> that I notice that this same construct looks to uniformly be there when SME2
> (or newer) insns have it. Perhaps I'm unaware of an earlier discussion on this
> ...
>
> Jan
The spec states "The vector group symbol is preferred for disassembly,
but optional in assembler source code.", so we have added the
disassembly with "VGx...".
But with other optional argument cases, as you mentioned if optional
argument is present (and set to default) or ignored in the assembly, we
have dropped the optional argument from the disassembly.
Regards,
Srinath
^ permalink raw reply [flat|nested] 10+ messages in threadend of thread, other threads:[~2024-07-15 9:22 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2024-07-08 15:36 [PATCH v1 0/6] Binutils] aarch64: Add support for sme2p1 instructions Srinath Parvathaneni 2024-07-08 15:36 ` [PATCH v1 1/6] aarch64: Add support for sme2.1 luti2 and luti4 instructions Srinath Parvathaneni 2024-07-08 15:36 ` [PATCH v1 2/6] aarch64: Add support for sme2.1 luti2 and luti4 instructions (regenerated files) Srinath Parvathaneni 2024-07-08 15:36 ` [PATCH v1 3/6] aarch64: Add support for sme2.1 movaz instructions Srinath Parvathaneni 2024-07-15 6:14 ` Jan Beulich 2024-07-15 9:21 ` Srinath Parvathaneni 2024-07-08 15:36 ` [PATCH v1 4/6] aarch64: Add support for sme2.1 movaz instructions (regenerated files) Srinath Parvathaneni 2024-07-08 15:36 ` [PATCH v1 5/6] aarch64: Add support for sme2.1 zero instructions Srinath Parvathaneni 2024-07-08 15:36 ` [PATCH v1 6/6] aarch64: Add support for sme2.1 zero instructions (regenerated files) Srinath Parvathaneni 2024-07-12 14:47 ` [PATCH v1 0/6] Binutils] aarch64: Add support for sme2p1 instructions Richard Earnshaw (lists)
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