diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index ceb0f34c885..929ee3d0245 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10731,6 +10731,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
 			AARCH64_FEATURES (2, FP8, SME2)},
   {"sme-f8f16",		AARCH64_FEATURE (SME_F8F16),
 			AARCH64_FEATURE (SME_F8F32)},
+  {"sme-f16f16",	AARCH64_FEATURE (SME_F16F16), AARCH64_FEATURE (SME2)},
   {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
 };
 
@@ -10749,7 +10750,7 @@ static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = {
   {AARCH64_FEATURE (SSVE_FP8DOT4), AARCH64_FEATURE (FP8DOT4_SVE)},
   {AARCH64_FEATURES (2, FP8DOT2, SVE2), AARCH64_FEATURE (FP8DOT2_SVE)},
   {AARCH64_FEATURE (SSVE_FP8DOT2), AARCH64_FEATURE (FP8DOT2_SVE)},
-  /* TODO: Add SME_F16F16->SME_F16F16_F8F16 when SME_F16F16 is added.  */
+  {AARCH64_FEATURE (SME_F16F16), AARCH64_FEATURE (SME_F16F16_F8F16)},
   {AARCH64_FEATURE (SME_F8F16), AARCH64_FEATURE (SME_F16F16_F8F16)},
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 8e46038a787..010bf032919 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -315,6 +315,8 @@ automatically cause those extensions to be disabled.
  @tab Enable @code{wfet} and @code{wfit} instructions.
 @item @code{xs} @tab
  @tab Enable the XS memory attribute extension.
+@item @code{sme-f16f16} @tab
+ @tab Enable the SME2 F16F16 Extension.
 @end multitable
 
 @multitable @columnfractions .20 .80
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.d b/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.d
new file mode 100644
index 00000000000..2d69c3add1e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.d
@@ -0,0 +1,4 @@
+#name: Test of invalid FEAT_SME_F16F16 fadd and fsub instructions.
+#as: -march=armv9.4-a+sme-f16f16
+#source: sme-f16f16-1-bad.s
+#error_output: sme-f16f16-1-bad.l
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.l b/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.l
new file mode 100644
index 00000000000..18a9c183ccd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.l
@@ -0,0 +1,33 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `fadd za.s\[w8,0,vgx2\],{z0.h-z1.h}'
+.*: Info:    did you mean this\?
+.*: Info:    	fadd za.s\[w8, 0, vgx2\], {z0.s-z1.s}
+.*: Info:    other valid variant\(s\):
+.*: Info:    	fadd za.d\[w8, 0, vgx2\], {z0.d-z1.d}
+.*: Error: too many registers in vector register list at operand 2 -- `fadd za.h\[w13,0,vgx2\],{z1.h-z0.h}'
+.*: Error: invalid vector group size at operand 1 -- `fadd za.h\[w8,11,vgx3\],{z0.h-z1.h}'
+.*: Error: too many registers in vector register list at operand 2 -- `fadd za.h\[w8,0,vgx2\],{z0.h-z4.h}'
+.*: Error: operand mismatch -- `fadd za.s\[w8,0,vgx4\],{z0.h-z3.h}'
+.*: Info:    did you mean this\?
+.*: Info:    	fadd za.s\[w8, 0, vgx4\], {z0.s-z3.s}
+.*: Info:    other valid variant\(s\):
+.*: Info:    	fadd za.d\[w8, 0, vgx4\], {z0.d-z3.d}
+.*: Error: too many registers in vector register list at operand 2 -- `fadd za.h\[w14,0,vgx4\],{z10.h-z3.h}'
+.*: Error: invalid vector group size at operand 1 -- `fadd za.h\[w8,15,vgx1\],{z3.h-z2.h}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fadd za.h\[w8,0,vgx4\],{z30.h-z31.h}'
+.*: Error: operand mismatch -- `fsub za.s\[w8,0,vgx2\],{z0.h-z1.h}'
+.*: Info:    did you mean this\?
+.*: Info:    	fsub za.s\[w8, 0, vgx2\], {z0.s-z1.s}
+.*: Info:    other valid variant\(s\):
+.*: Info:    	fsub za.d\[w8, 0, vgx2\], {z0.d-z1.d}
+.*: Error: too many registers in vector register list at operand 2 -- `fsub za.h\[w13,0,vgx2\],{z1.h-z0.h}'
+.*: Error: invalid vector group size at operand 1 -- `fsub za.h\[w8,11,vgx3\],{z0.h-z1.h}'
+.*: Error: too many registers in vector register list at operand 2 -- `fsub za.h\[w8,0,vgx2\],{z0.h-z4.h}'
+.*: Error: operand mismatch -- `fsub za.s\[w8,0,vgx4\],{z0.h-z3.h}'
+.*: Info:    did you mean this\?
+.*: Info:    	fsub za.s\[w8, 0, vgx4\], {z0.s-z3.s}
+.*: Info:    other valid variant\(s\):
+.*: Info:    	fsub za.d\[w8, 0, vgx4\], {z0.d-z3.d}
+.*: Error: too many registers in vector register list at operand 2 -- `fsub za.h\[w14,0,vgx4\],{z10.h-z3.h}'
+.*: Error: invalid vector group size at operand 1 -- `fsub za.h\[w8,15,vgx1\],{z3.h-z2.h}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fsub za.h\[w8,0,vgx4\],{z30.h-z31.h}'
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.s b/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.s
new file mode 100644
index 00000000000..06fb65022b6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.s
@@ -0,0 +1,21 @@
+/* FADD.  */
+fadd    za.s[w8, 0, vgx2], {z0.h - z1.h}
+fadd    za.h[w13, 0, vgx2], {z1.h - z0.h}
+fadd    za.h[w8, 11, vgx3], {z0.h - z1.h}
+fadd    za.h[w8, 0, vgx2], {z0.h - z4.h}
+
+fadd    za.s[w8, 0, vgx4], {z0.h - z3.h}
+fadd    za.h[w14, 0, vgx4], {z10.h - z3.h}
+fadd    za.h[w8, 15, vgx1], {z3.h - z2.h}
+fadd    za.h[w8, 0, vgx4], {z30.h - z31.h}
+
+/* FSUB.  */
+fsub    za.s[w8, 0, vgx2], {z0.h - z1.h}
+fsub    za.h[w13, 0, vgx2], {z1.h - z0.h}
+fsub    za.h[w8, 11, vgx3], {z0.h - z1.h}
+fsub    za.h[w8, 0, vgx2], {z0.h - z4.h}
+
+fsub    za.s[w8, 0, vgx4], {z0.h - z3.h}
+fsub    za.h[w14, 0, vgx4], {z10.h - z3.h}
+fsub    za.h[w8, 15, vgx1], {z3.h - z2.h}
+fsub    za.h[w8, 0, vgx4], {z30.h - z31.h}
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-1.d b/gas/testsuite/gas/aarch64/sme-f16f16-1.d
new file mode 100644
index 00000000000..7e725711039
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-1.d
@@ -0,0 +1,38 @@
+#name: Test of FEAT_SME_F16F16 fsub and fsub instructions.
+#as: -march=armv9.4-a+sme-f16f16
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*:	c1a41c00 	fadd	za.h\[w8, 0, vgx2\], {z0.h-z1.h}
+.*:	c1a47c00 	fadd	za.h\[w11, 0, vgx2\], {z0.h-z1.h}
+.*:	c1a41c07 	fadd	za.h\[w8, 7, vgx2\], {z0.h-z1.h}
+.*:	c1a41fc0 	fadd	za.h\[w8, 0, vgx2\], {z30.h-z31.h}
+.*:	c1a47fc7 	fadd	za.h\[w11, 7, vgx2\], {z30.h-z31.h}
+.*:	c1a43e03 	fadd	za.h\[w9, 3, vgx2\], {z16.h-z17.h}
+.*:	c1a45d01 	fadd	za.h\[w10, 1, vgx2\], {z8.h-z9.h}
+.*:	c1a51c00 	fadd	za.h\[w8, 0, vgx4\], {z0.h-z3.h}
+.*:	c1a57c00 	fadd	za.h\[w11, 0, vgx4\], {z0.h-z3.h}
+.*:	c1a51c07 	fadd	za.h\[w8, 7, vgx4\], {z0.h-z3.h}
+.*:	c1a51f80 	fadd	za.h\[w8, 0, vgx4\], {z28.h-z31.h}
+.*:	c1a57f87 	fadd	za.h\[w11, 7, vgx4\], {z28.h-z31.h}
+.*:	c1a53d83 	fadd	za.h\[w9, 3, vgx4\], {z12.h-z15.h}
+.*:	c1a55d01 	fadd	za.h\[w10, 1, vgx4\], {z8.h-z11.h}
+.*:	c1a41c08 	fsub	za.h\[w8, 0, vgx2\], {z0.h-z1.h}
+.*:	c1a47c08 	fsub	za.h\[w11, 0, vgx2\], {z0.h-z1.h}
+.*:	c1a41c0f 	fsub	za.h\[w8, 7, vgx2\], {z0.h-z1.h}
+.*:	c1a41fc8 	fsub	za.h\[w8, 0, vgx2\], {z30.h-z31.h}
+.*:	c1a47fcf 	fsub	za.h\[w11, 7, vgx2\], {z30.h-z31.h}
+.*:	c1a43e0b 	fsub	za.h\[w9, 3, vgx2\], {z16.h-z17.h}
+.*:	c1a45d09 	fsub	za.h\[w10, 1, vgx2\], {z8.h-z9.h}
+.*:	c1a51c08 	fsub	za.h\[w8, 0, vgx4\], {z0.h-z3.h}
+.*:	c1a57c08 	fsub	za.h\[w11, 0, vgx4\], {z0.h-z3.h}
+.*:	c1a51c0f 	fsub	za.h\[w8, 7, vgx4\], {z0.h-z3.h}
+.*:	c1a51f88 	fsub	za.h\[w8, 0, vgx4\], {z28.h-z31.h}
+.*:	c1a57f8f 	fsub	za.h\[w11, 7, vgx4\], {z28.h-z31.h}
+.*:	c1a53d8b 	fsub	za.h\[w9, 3, vgx4\], {z12.h-z15.h}
+.*:	c1a55d09 	fsub	za.h\[w10, 1, vgx4\], {z8.h-z11.h}
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-1.s b/gas/testsuite/gas/aarch64/sme-f16f16-1.s
new file mode 100644
index 00000000000..d0ac7f8e908
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-1.s
@@ -0,0 +1,33 @@
+/* FADD.  */
+fadd    za.h[w8, 0, vgx2], {z0.h - z1.h}
+fadd    za.h[w11, 0, vgx2], {z0.h - z1.h}
+fadd    za.h[w8, 7, vgx2], {z0.h - z1.h}
+fadd    za.h[w8, 0, vgx2], {z30.h - z31.h}
+fadd    za.h[w11, 7, vgx2], {z30.h - z31.h}
+fadd    za.h[w9, 3, vgx2], {z16.h - z17.h}
+fadd    za.h[w10, 1], {z8.h - z9.h}
+
+fadd    za.h[w8, 0, vgx4], {z0.h - z3.h}
+fadd    za.h[w11, 0, vgx4], {z0.h - z3.h}
+fadd    za.h[w8, 7, vgx4], {z0.h - z3.h}
+fadd    za.h[w8, 0, vgx4], {z28.h - z31.h}
+fadd    za.h[w11, 7, vgx4], {z28.h - z31.h}
+fadd    za.h[w9, 3, vgx4], {z12.h - z15.h}
+fadd    za.h[w10, 1], {z8.h - z11.h}
+
+/* FSUB.  */
+fsub    za.h[w8, 0, vgx2], {z0.h - z1.h}
+fsub    za.h[w11, 0, vgx2], {z0.h - z1.h}
+fsub    za.h[w8, 7, vgx2], {z0.h - z1.h}
+fsub    za.h[w8, 0, vgx2], {z30.h - z31.h}
+fsub    za.h[w11, 7, vgx2], {z30.h - z31.h}
+fsub    za.h[w9, 3, vgx2], {z16.h - z17.h}
+fsub    za.h[w10, 1], {z8.h - z9.h}
+
+fsub    za.h[w8, 0, vgx4], {z0.h - z3.h}
+fsub    za.h[w11, 0, vgx4], {z0.h - z3.h}
+fsub    za.h[w8, 7, vgx4], {z0.h - z3.h}
+fsub    za.h[w8, 0, vgx4], {z28.h - z31.h}
+fsub    za.h[w11, 7, vgx4], {z28.h - z31.h}
+fsub    za.h[w9, 3, vgx4], {z12.h - z15.h}
+fsub    za.h[w10, 1], {z8.h - z11.h}
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 1b01931b0cb..e2e4c6d0a09 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -264,6 +264,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_SME_F8F32,
   /* SME F8F16 instructions.  */
   AARCH64_FEATURE_SME_F8F16,
+  /* Non-widening half-precision FP16 to FP16 arithmetic for SME2.  */
+  AARCH64_FEATURE_SME_F16F16,
 
   /* Virtual features.  These are used to gate instructions that are enabled
      by either of two (or more) sets of command line flags.  */