From: Jan Beulich <jbeulich@suse.com>
To: "H.J. Lu" <hjl.tools@gmail.com>
Cc: "binutils@sourceware.org" <binutils@sourceware.org>
Subject: Re: [PATCH v5 5/5] x86-64: Intel64 adjustments for insns dealing with far pointers
Date: Wed, 12 Feb 2020 08:11:00 -0000 [thread overview]
Message-ID: <21ce99c2-5dd5-c4cd-ad00-ab91aa2cf551@suse.com> (raw)
In-Reply-To: <CAMe9rOo+T7vephVhjFkQtP-2o+67nu3=5d0e17cS-B+TRc0t=g@mail.gmail.com>
On 11.02.2020 12:52, H.J. Lu wrote:
> On Tue, Feb 11, 2020 at 2:26 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> AMD and Intel differ in their handling of far indirect branches as well
>> as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note
>> how the latter three were hybrids so far, while far branches were fully
>> AMD-like.)
>>
>> gas/
>> 2020-02-XX Jan Beulich <jbeulich@suse.com>
>>
>> PR gas/24546
>> * config/tc-i386-intel.c (i386_intel_operand): Also handle CALL/JMP
>> in O_tbyte_ptr case.
>> * doc/c-i386.texi: Mention far call and full pointer load ISA
>> differences.
>> * testsuite/gas/i386/x86-64-branch-3.s,
>> testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases.
>> * testsuite/gas/i386/x86-64-branch-3.d,
>> testsuite/gas/i386/x86-64-intel64.d: Adjust expectations.
>> * testsuite/gas/i386/x86-64-branch-5.l,
>> testsuite/gas/i386/x86-64-branch-5.s: New.
>> * testsuite/gas/i386/i386.exp: Run new test.
>>
>> opcodes/
>> 2020-02-XX Jan Beulich <jbeulich@suse.com>
>>
>> PR gas/24546
>> * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
>> * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
>> Amd64 and Intel64 templates.
>> (call, jmp): Likewise for far indirect variants. Dro
>> Unspecified.
>> * i386-tbl.h: Re-generate.
>
> OK.
There'll need to be a v6, as I've spotted an issue with non-64-bit
code in -mintel64 mode (which occurred to me only when starting to
deal with the vendor difference also for Jcc). v4 had an adjustment
for this, and I wrongly thought it could be dropped altogether when
re-basing over your Intel64-only change. (On the positive side I
think a few other templates will be able to be folded as a follow-on
to the fix I'm intending to make.)
Jan
prev parent reply other threads:[~2020-02-12 8:11 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-11 10:23 [PATCH v5 0/5] x86: operand size handling improvements Jan Beulich
2020-02-11 10:25 ` [PATCH v5 3/5] x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZX Jan Beulich
2020-02-11 10:25 ` [PATCH v5 1/5] x86: also disallow non-byte/-word registers with byte/word suffix Jan Beulich
2020-02-11 11:27 ` H.J. Lu
2020-02-11 10:25 ` [PATCH v5 2/5] x86: move certain MOVSX/MOVZX tests Jan Beulich
2020-02-11 11:43 ` H.J. Lu
2020-02-11 11:55 ` Jan Beulich
2020-02-11 12:20 ` H.J. Lu
2020-02-11 12:58 ` Jan Beulich
2020-02-11 13:02 ` H.J. Lu
2020-02-11 13:04 ` Jan Beulich
2020-02-11 13:07 ` H.J. Lu
2020-02-11 16:45 ` Jan Beulich
2020-02-11 17:04 ` H.J. Lu
2020-02-11 20:12 ` [PATCH] x86: Remove movsx/movzx with memory operand from AT&T syntax H.J. Lu
2020-02-11 23:34 ` H.J. Lu
2020-02-11 23:52 ` H.J. Lu
2020-02-12 3:19 ` [PATCH] x86: Remove movsx/movzx with 16/32-bit " H.J. Lu
2020-02-12 9:19 ` Jan Beulich
2020-02-11 10:26 ` [PATCH v5 4/5] x86: correct VFPCLASSP{S,D} operand size handling Jan Beulich
2020-02-11 11:50 ` H.J. Lu
2020-02-11 12:49 ` Jan Beulich
2020-02-11 12:56 ` H.J. Lu
2020-02-11 10:27 ` [PATCH v5 5/5] x86-64: Intel64 adjustments for insns dealing with far pointers Jan Beulich
2020-02-11 11:53 ` H.J. Lu
2020-02-12 8:11 ` Jan Beulich [this message]
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