From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23584 invoked by alias); 12 Feb 2020 08:11:04 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 23074 invoked by uid 89); 12 Feb 2020 08:11:04 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-4.5 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.1 spammy=H*i:5d0e17cS-B, H*i:TRc0t, H*i:67nu3, H*f:5d0e17cS-B X-HELO: mx2.suse.de Received: from mx2.suse.de (HELO mx2.suse.de) (195.135.220.15) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 12 Feb 2020 08:11:02 +0000 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 406FFAEF6; Wed, 12 Feb 2020 08:11:00 +0000 (UTC) Subject: Re: [PATCH v5 5/5] x86-64: Intel64 adjustments for insns dealing with far pointers To: "H.J. Lu" Cc: "binutils@sourceware.org" References: <1e1b8eba-93ff-39ed-460a-a922d12af27e@suse.com> From: Jan Beulich Message-ID: <21ce99c2-5dd5-c4cd-ad00-ab91aa2cf551@suse.com> Date: Wed, 12 Feb 2020 08:11:00 -0000 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.4.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2020-02/txt/msg00204.txt.bz2 On 11.02.2020 12:52, H.J. Lu wrote: > On Tue, Feb 11, 2020 at 2:26 AM Jan Beulich wrote: >> >> AMD and Intel differ in their handling of far indirect branches as well >> as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note >> how the latter three were hybrids so far, while far branches were fully >> AMD-like.) >> >> gas/ >> 2020-02-XX Jan Beulich >> >> PR gas/24546 >> * config/tc-i386-intel.c (i386_intel_operand): Also handle CALL/JMP >> in O_tbyte_ptr case. >> * doc/c-i386.texi: Mention far call and full pointer load ISA >> differences. >> * testsuite/gas/i386/x86-64-branch-3.s, >> testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases. >> * testsuite/gas/i386/x86-64-branch-3.d, >> testsuite/gas/i386/x86-64-intel64.d: Adjust expectations. >> * testsuite/gas/i386/x86-64-branch-5.l, >> testsuite/gas/i386/x86-64-branch-5.s: New. >> * testsuite/gas/i386/i386.exp: Run new test. >> >> opcodes/ >> 2020-02-XX Jan Beulich >> >> PR gas/24546 >> * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode. >> * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into >> Amd64 and Intel64 templates. >> (call, jmp): Likewise for far indirect variants. Dro >> Unspecified. >> * i386-tbl.h: Re-generate. > > OK. There'll need to be a v6, as I've spotted an issue with non-64-bit code in -mintel64 mode (which occurred to me only when starting to deal with the vendor difference also for Jcc). v4 had an adjustment for this, and I wrongly thought it could be dropped altogether when re-basing over your Intel64-only change. (On the positive side I think a few other templates will be able to be folded as a follow-on to the fix I'm intending to make.) Jan