From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 78479 invoked by alias); 1 May 2019 17:46:17 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 78331 invoked by uid 89); 1 May 2019 17:46:17 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.8 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3 autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 01 May 2019 17:46:15 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 514EA80D for ; Wed, 1 May 2019 10:46:14 -0700 (PDT) Received: from [10.2.207.62] (e107157-lin.cambridge.arm.com [10.2.207.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EF90C3F719 for ; Wed, 1 May 2019 10:46:13 -0700 (PDT) Subject: [PATCH 48/57][Arm][OBJDUMP] Add support for MVE instructions: vddup, vdwdup, vidup and viwdup To: binutils@sourceware.org References: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> From: "Andre Vieira (lists)" Message-ID: <29527687-aefb-ec31-ac00-a5487266683d@arm.com> Date: Wed, 01 May 2019 17:46:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> Content-Type: multipart/mixed; boundary="------------461E06D6DF9A04588A9E27B0" X-IsSubscribed: yes X-SW-Source: 2019-05/txt/msg00078.txt.bz2 This is a multi-part message in MIME format. --------------461E06D6DF9A04588A9E27B0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 434 Hello, This patch adds support for MVE instructions: VDDUP, VDWDUP, VIDUP, and VIWDUP. opcodes/ChangeLog: 2019-05-01 Andre Vieira Michael Collison * arm-dis.c (enum mve_instructions): Add new instructions. (is_mve_encoding_conflict): Handle new instructions. (is_mve_unpredictable): Likewise. (print_mve_size): Likewise. (print_insn_mve): Likewise. --------------461E06D6DF9A04588A9E27B0 Content-Type: text/x-patch; name="48.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="48.patch" Content-length: 4183 diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 006475d40046fc75df94ce29b595f220fda1c3ee..1dae51d8a0889e288e85876be280bfaea2a4c785 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -175,6 +175,10 @@ enum mve_instructions MVE_VQRDMULH_T2, MVE_VQDMULH_T3, MVE_VQRDMULH_T4, + MVE_VDDUP, + MVE_VDWDUP, + MVE_VIWDUP, + MVE_VIDUP, MVE_NONE }; @@ -1957,9 +1961,12 @@ static const struct opcode32 neon_opcodes[] = UNPREDICTABLE %s print size for vector predicate & non VMOV instructions %i print immediate for vstr/vldr reg +/- imm + %h print high half of 64-bit destination reg %k print immediate for vector conversion instruction + %l print low half of 64-bit destination reg + %u print immediate value for vddup/vdwdup %x print the bitfield in hex. - */ + */ static const struct mopcode32 mve_opcodes[] = { @@ -2182,6 +2189,30 @@ static const struct mopcode32 mve_opcodes[] = 0xffb30040, 0xffb31c51, "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"}, + /* Vector VDDUP. */ + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_VDDUP, + 0xee011f6e, 0xff811f7e, + "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"}, + + /* Vector VDWDUP. */ + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_VDWDUP, + 0xee011f60, 0xff811f70, + "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"}, + + /* Vector VIWDUP. */ + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_VIWDUP, + 0xee010f60, 0xff811f70, + "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"}, + + /* Vector VIDUP. */ + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_VIDUP, + 0xee010f6e, 0xff811f7e, + "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"}, + /* Vector VLD2. */ {ARM_FEATURE_COPROC (FPU_MVE), MVE_VLD2, @@ -4667,6 +4698,8 @@ is_mve_encoding_conflict (unsigned long given, else return FALSE; + case MVE_VDDUP: + case MVE_VIDUP: case MVE_VQRDMLADH: case MVE_VQDMLAH: case MVE_VQRDMLAH: @@ -4797,6 +4830,14 @@ is_mve_encoding_conflict (unsigned long given, else return FALSE; + case MVE_VDWDUP: + case MVE_VIWDUP: + if ((arm_decode_field (given, 20, 21) == 3) + || (arm_decode_field (given, 1, 3) == 7)) + return TRUE; + else + return FALSE; + default: return FALSE; @@ -5548,6 +5589,16 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn, else return FALSE; + case MVE_VDWDUP: + case MVE_VIWDUP: + if (arm_decode_field (given, 1, 3) == 6) + { + *unpredictable_code = UNPRED_R13; + return TRUE; + } + else + return FALSE; + default: return FALSE; } @@ -6184,10 +6235,14 @@ print_mve_size (struct disassemble_info *info, case MVE_VCMP_VEC_T4: case MVE_VCMP_VEC_T5: case MVE_VCMP_VEC_T6: + case MVE_VDDUP: + case MVE_VDWDUP: case MVE_VHADD_T1: case MVE_VHADD_T2: case MVE_VHSUB_T1: case MVE_VHSUB_T2: + case MVE_VIDUP: + case MVE_VIWDUP: case MVE_VLD2: case MVE_VLD4: case MVE_VLDRB_GATHER_T1: @@ -7951,6 +8006,12 @@ print_insn_mve (struct disassemble_info *info, long given) if (value == 1) func (stream, "a"); break; + case 'h': + { + unsigned int odd_reg = (value << 1) | 1; + func (stream, "%s", arm_regnames[odd_reg]); + } + break; case 'i': { unsigned long imm @@ -7978,6 +8039,31 @@ print_insn_mve (struct disassemble_info *info, long given) case 'k': func (stream, "%lu", 64 - value); break; + case 'l': + { + unsigned int even_reg = value << 1; + func (stream, "%s", arm_regnames[even_reg]); + } + break; + case 'u': + switch (value) + { + case 0: + func (stream, "1"); + break; + case 1: + func (stream, "2"); + break; + case 2: + func (stream, "4"); + break; + case 3: + func (stream, "8"); + break; + default: + break; + } + break; case 'r': func (stream, "%s", arm_regnames[value]); break; --------------461E06D6DF9A04588A9E27B0--