Re: [PATCH v6 1/4] gas, aarch64: Add AdvSIMD lut extension

[Andrew Carlotti <andrew.carlotti@arm.com>]

On Thu, May 23, 2024 at 02:50:16PM +0100, Saurabh Jha wrote:
> 
> Introduces instructions for the Advanced SIMD lut extension for AArch64. They are documented in the following links:
> * luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en
> * luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en
> 
> These instructions needed definition of some new operands. We will first
> discuss operands for the third operand of the instructions and then
> discuss a vector register list operand needed for the second operand.
> 
> The third operands are vectors with bit indices and without type
> qualifiers. They are called Em_INDEX1_14, Em_INDEX2_13, and Em_INDEX3_12
> and they have 1 bit, 2 bit, and 3 bit indices respectively. For these
> new operands, we defined new parsing case branch and a new instruction
> class. The lsb and width of these operands are the same as many existing
> but the convention is to give different names to fields that serve
> different purpose so we introduced new fields in aarch64-opc.c and
> aarch64-opc.h for these new operands.
> 
> For the second operand of these instructions, we introduced a new
> operand called LVn_LUT. This represents a vector register list with
> stride 1. We defined new inserter and extractor for this new operand and
> it is encoded in FLD_Rn. We are enforcing the number of registers in the
> reglist using opcode flag rather than operand flag as this is what other
> SIMD vector register list operands are doing. The disassembly also uses
> opcode flag to print the correct number of registers.
> ---
> Hi,
> 
> Regression tested for aarch64-none-elf and found no regressions.
> 
> Ok for binutils-master? I don't have commit access so can someone please commit on my behalf?
> 
> Regards,
> Saurabh
...
> diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
> index 5a55ca2f86d..338ed54165d 100644
> --- a/opcodes/aarch64-asm.c
> +++ b/opcodes/aarch64-asm.c
> @@ -168,6 +168,27 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
>        assert (reglane_index < 4);
>        insert_field (FLD_SM3_imm2, code, reglane_index, 0);
>      }
> +  else if (inst->opcode->iclass == lut)
> +    {
> +      unsigned reglane_index = info->reglane.index;
> +      switch (info->type)
> +	{
> +	case AARCH64_OPND_Em_INDEX1_14:
> +	  assert (reglane_index < 2);
> +	  insert_field (FLD_imm1_14, code, reglane_index, 0);
> +	  break;
> +	case AARCH64_OPND_Em_INDEX2_13:
> +	  assert (reglane_index < 4);
> +	  insert_field (FLD_imm2_13, code, reglane_index, 0);
> +	  break;
> +	case AARCH64_OPND_Em_INDEX3_12:
> +	  assert (reglane_index < 8);
> +	  insert_field (FLD_imm3_12, code, reglane_index, 0);
> +	  break;
> +	default:
> +	  return false;
> +	}
> +    }
>    else
>      {
>        /* index for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]

This hunk should be dropped now that these operands use the simple_index inserter/extractor.