From: "Andre Vieira (lists)" <andre.simoesdiasvieira@arm.com>
To: binutils@sourceware.org
Subject: [PATCH 19/57][Arm][GAS] Add support for MVE instructions: vmax[nm][a] and vmin[nm][a]
Date: Wed, 01 May 2019 17:12:00 -0000 [thread overview]
Message-ID: <2a328096-ec13-2e4e-07e6-2f820bd06b6b@arm.com> (raw)
In-Reply-To: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com>
[-- Attachment #1: Type: text/plain, Size: 1087 bytes --]
Hi,
This patch adds support for MVE instructions VMAX, VMAXA, VMAXNM,
VMAXNMA, VMIN, VMINA, VMINNM, and VMINNMA.
gas/ChangeLog:
2019-05-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vmaxa_vmina): New encoding function.
(do_mve_vmaxnma_vminnma): Likewise.
(do_neon_dyadic_if_su): Change to support MVE variants.
(do_vmaxnm): Likewise.
(insns): Change to accept MVE variants and add new.
* testsuite/gas/arm/mve-vmax-vmin-bad.d: New test.
* testsuite/gas/arm/mve-vmax-vmin-bad.l: New test.
* testsuite/gas/arm/mve-vmax-vmin-bad.s: New test.
* testsuite/gas/arm/mve-vmaxa-vmina-bad.d: New test.
* testsuite/gas/arm/mve-vmaxa-vmina-bad.l: New test.
* testsuite/gas/arm/mve-vmaxa-vmina-bad.s: New test.
* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.d: New test.
* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.l: New test.
* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.s: New test.
* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.d: New test.
* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.l: New test.
* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.s: New test.
[-- Attachment #2: 19.patch --]
[-- Type: text/x-patch, Size: 19032 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index de3c8b69b767a9232488129985ebb540b08c2192..f490b91b685d4c0089bd8c4ad055b534d389aa8b 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -15593,6 +15593,26 @@ do_mve_vcmp (void)
return;
}
+static void
+do_mve_vmaxa_vmina (void)
+{
+ if (inst.cond > COND_ALWAYS)
+ inst.pred_insn_type = INSIDE_VPT_INSN;
+ else
+ inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
+
+ enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
+ struct neon_type_el et
+ = neon_check_type (2, rs, N_EQK, N_KEY | N_S8 | N_S16 | N_S32);
+
+ inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+ inst.instruction |= neon_logbits (et.size) << 18;
+ inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+ inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+ inst.instruction |= LOW4 (inst.operands[1].reg);
+ inst.is_neon = 1;
+}
+
static void
do_mve_vfmas (void)
{
@@ -15662,6 +15682,26 @@ do_mve_viddup (void)
inst.is_neon = 1;
}
+static void
+do_mve_vmaxnma_vminnma (void)
+{
+ enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
+ struct neon_type_el et
+ = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
+
+ if (inst.cond > COND_ALWAYS)
+ inst.pred_insn_type = INSIDE_VPT_INSN;
+ else
+ inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
+
+ inst.instruction |= (et.size == 16) << 28;
+ inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+ inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+ inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+ inst.instruction |= LOW4 (inst.operands[1].reg);
+ inst.is_neon = 1;
+}
+
static void
do_mve_vcmul (void)
{
@@ -16704,6 +16744,11 @@ do_neon_dyadic_if_su (void)
struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
N_SUF_32 | N_KEY);
+ constraint ((inst.instruction == ((unsigned) N_MNEM_vmax)
+ || inst.instruction == ((unsigned) N_MNEM_vmin))
+ && et.type == NT_float
+ && !ARM_CPU_HAS_FEATURE (cpu_variant,fpu_neon_ext_v1), BAD_FPU);
+
if (check_simd_pred_availability (et.type == NT_float,
NEON_CHECK_ARCH | NEON_CHECK_CC))
return;
@@ -19746,12 +19791,13 @@ do_vsel (void)
static void
do_vmaxnm (void)
{
- set_pred_insn_type (OUTSIDE_PRED_INSN);
+ if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
+ set_pred_insn_type (OUTSIDE_PRED_INSN);
if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
return;
- if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
+ if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH8))
return;
neon_dyadic_misc (NT_untyped, N_F_16_32, 0);
@@ -22954,8 +23000,6 @@ static const struct asm_opcode insns[] =
nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
- nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
- nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
@@ -23674,9 +23718,7 @@ static const struct asm_opcode insns[] =
NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
/* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
- nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
- nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
/* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
back to neon_dyadic_if_su. */
@@ -24373,11 +24415,15 @@ static const struct asm_opcode insns[] =
mCEF(vdwdup, _vdwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
mCEF(vidup, _vidup, 3, (RMQ, RRe, EXPi), mve_viddup),
mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
+ mToC("vmaxa", ee330e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
+ mToC("vmina", ee331e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
#undef THUMB_VARIANT
#define THUMB_VARIANT & mve_fp_ext
mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas),
+ mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
+ mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_vfp_ext_v1
@@ -24421,6 +24467,8 @@ static const struct asm_opcode insns[] =
mnUF(vcvtp, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtp),
mnUF(vcvtn, _vcvta, 3, (RNSDQMQ, oRNSDQMQ, oI32z), neon_cvtn),
mnUF(vcvtm, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtm),
+ mnUF(vmaxnm, _vmaxnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
+ mnUF(vminnm, _vminnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_neon_ext_v1
@@ -24439,6 +24487,8 @@ static const struct asm_opcode insns[] =
MNUF(vhadd, 00000000, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
MNUF(vrhadd, 00000100, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_i_su),
MNUF(vhsub, 00000200, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
+ mnUF(vmin, _vmin, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
+ mnUF(vmax, _vmax, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_v8_3
diff --git a/gas/testsuite/gas/arm/mve-vmax-vmin-bad.d b/gas/testsuite/gas/arm/mve-vmax-vmin-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..9ffbca4becedc3882251c5c4341d0cafb81f8ff3
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vmax-vmin-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VMAX and VMIN instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vmax-vmin-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vmax-vmin-bad.l b/gas/testsuite/gas/arm/mve-vmax-vmin-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..17d5c74602151bc387d082a95cc050d5ab3e565f
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vmax-vmin-bad.l
@@ -0,0 +1,27 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vmax.s64 q0,q1,q2'
+[^:]*:11: Error: selected FPU does not support instruction -- `vmax.f16 q0,q1,q2'
+[^:]*:12: Error: bad type in SIMD instruction -- `vmax.u64 q0,q1,q2'
+[^:]*:13: Error: selected FPU does not support instruction -- `vmax.f32 q0,q1,q2'
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Error: syntax error -- `vmaxeq.s16 q0,q1,q2'
+[^:]*:18: Error: syntax error -- `vmaxeq.s16 q0,q1,q2'
+[^:]*:20: Error: syntax error -- `vmaxeq.s16 q0,q1,q2'
+[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxt.s16 q0,q1,q2'
+[^:]*:23: Error: instruction missing MVE vector predication code -- `vmax.s16 q0,q1,q2'
+[^:]*:25: Error: syntax error -- `vmineq.u32 q0,q1,q2'
+[^:]*:26: Error: syntax error -- `vmineq.u32 q0,q1,q2'
+[^:]*:28: Error: syntax error -- `vmineq.u32 q0,q1,q2'
+[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vmint.u32 q0,q1,q2'
+[^:]*:31: Error: instruction missing MVE vector predication code -- `vmin.u32 q0,q1,q2'
diff --git a/gas/testsuite/gas/arm/mve-vmax-vmin-bad.s b/gas/testsuite/gas/arm/mve-vmax-vmin-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..b7b92427c2235574efba55eb2539d39b2ded1c65
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vmax-vmin-bad.s
@@ -0,0 +1,31 @@
+.macro cond, op
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().s8 q0, q1, q2
+.endr
+.endm
+
+.syntax unified
+.thumb
+vmax.s64 q0, q1, q2
+vmax.f16 q0, q1, q2
+vmax.u64 q0, q1, q2
+vmax.f32 q0, q1, q2
+cond vmax
+cond vmin
+it eq
+vmaxeq.s16 q0, q1, q2
+vmaxeq.s16 q0, q1, q2
+vpst
+vmaxeq.s16 q0, q1, q2
+vmaxt.s16 q0, q1, q2
+vpst
+vmax.s16 q0, q1, q2
+it eq
+vmineq.u32 q0, q1, q2
+vmineq.u32 q0, q1, q2
+vpst
+vmineq.u32 q0, q1, q2
+vmint.u32 q0, q1, q2
+vpst
+vmin.u32 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.d b/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..11105db987b6239c556005557d1d9a074059a785
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VMAXA and VMINA instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vmaxa-vmina-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.l b/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..0e2ffed6d54de7a829c33b291aa42069734827c4
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.l
@@ -0,0 +1,29 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vmaxa.u8 q0,q1'
+[^:]*:11: Error: bad type in SIMD instruction -- `vmaxa.s64 q0,q1'
+[^:]*:12: Error: bad type in SIMD instruction -- `vmaxa.f16 q0,q1'
+[^:]*:13: Error: bad type in SIMD instruction -- `vmina.u8 q0,q1'
+[^:]*:14: Error: bad type in SIMD instruction -- `vmina.s64 q0,q1'
+[^:]*:15: Error: bad type in SIMD instruction -- `vmina.f16 q0,q1'
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Error: syntax error -- `vmaxaeq.s8 q0,q1'
+[^:]*:20: Error: syntax error -- `vmaxaeq.s8 q0,q1'
+[^:]*:22: Error: syntax error -- `vmaxaeq.s8 q0,q1'
+[^:]*:23: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxat.s8 q0,q1'
+[^:]*:25: Error: instruction missing MVE vector predication code -- `vmaxa.s8 q0,q1'
+[^:]*:27: Error: syntax error -- `vminaeq.s8 q0,q1'
+[^:]*:28: Error: syntax error -- `vminaeq.s8 q0,q1'
+[^:]*:30: Error: syntax error -- `vminaeq.s8 q0,q1'
+[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vminat.s8 q0,q1'
+[^:]*:33: Error: instruction missing MVE vector predication code -- `vmina.s8 q0,q1'
diff --git a/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.s b/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..08cc60a2baca34108d4003fb658dc25afc36081b
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.s
@@ -0,0 +1,33 @@
+.macro cond, op
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().s8 q0, q1
+.endr
+.endm
+
+.syntax unified
+.thumb
+vmaxa.u8 q0, q1
+vmaxa.s64 q0, q1
+vmaxa.f16 q0, q1
+vmina.u8 q0, q1
+vmina.s64 q0, q1
+vmina.f16 q0, q1
+cond vmaxa
+cond vmina
+it eq
+vmaxaeq.s8 q0, q1
+vmaxaeq.s8 q0, q1
+vpst
+vmaxaeq.s8 q0, q1
+vmaxat.s8 q0, q1
+vpst
+vmaxa.s8 q0, q1
+it eq
+vminaeq.s8 q0, q1
+vminaeq.s8 q0, q1
+vpst
+vminaeq.s8 q0, q1
+vminat.s8 q0, q1
+vpst
+vmina.s8 q0, q1
diff --git a/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.d b/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..4617cd4c3dc2e0bb9420d60e160ff2026ce59442
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VMAXNM and VMINNM instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vmaxnm-vminnm-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.l b/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..012ab35bf18d2908f61dfdbc8c3028bd113d06ce
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.l
@@ -0,0 +1,27 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vmaxnm.f64 q0,q1,q2'
+[^:]*:11: Error: bad type in SIMD instruction -- `vmaxnm.i16 q0,q1,q2'
+[^:]*:12: Error: bad type in SIMD instruction -- `vminnm.f64 q0,q1,q2'
+[^:]*:13: Error: bad type in SIMD instruction -- `vminnm.i16 q0,q1,q2'
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Error: syntax error -- `vmaxnmeq.f32 q0,q1,q2'
+[^:]*:18: Error: syntax error -- `vmaxnmeq.f32 q0,q1,q2'
+[^:]*:20: Error: syntax error -- `vmaxnmeq.f32 q0,q1,q2'
+[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxnmt.f32 q0,q1,q2'
+[^:]*:23: Error: instruction missing MVE vector predication code -- `vmaxnm.f32 q0,q1,q2'
+[^:]*:25: Error: syntax error -- `vminnmeq.f32 q0,q1,q2'
+[^:]*:26: Error: syntax error -- `vminnmeq.f32 q0,q1,q2'
+[^:]*:28: Error: syntax error -- `vminnmeq.f32 q0,q1,q2'
+[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vminnmt.f32 q0,q1,q2'
+[^:]*:31: Error: instruction missing MVE vector predication code -- `vminnm.f32 q0,q1,q2'
diff --git a/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.s b/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..2b6436cc6a27d51d3a01eafbb2de10afe76f3eb6
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.s
@@ -0,0 +1,31 @@
+.macro cond, op
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().f16 q0, q1, q2
+.endr
+.endm
+
+.syntax unified
+.thumb
+vmaxnm.f64 q0, q1, q2
+vmaxnm.i16 q0, q1, q2
+vminnm.f64 q0, q1, q2
+vminnm.i16 q0, q1, q2
+cond vmaxnm
+cond vminnm
+it eq
+vmaxnmeq.f32 q0, q1, q2
+vmaxnmeq.f32 q0, q1, q2
+vpst
+vmaxnmeq.f32 q0, q1, q2
+vmaxnmt.f32 q0, q1, q2
+vpst
+vmaxnm.f32 q0, q1, q2
+it eq
+vminnmeq.f32 q0, q1, q2
+vminnmeq.f32 q0, q1, q2
+vpst
+vminnmeq.f32 q0, q1, q2
+vminnmt.f32 q0, q1, q2
+vpst
+vminnm.f32 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.d b/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..5d11eee34c4040fbef21c0c3799e3c98d75ca123
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VMAXNMA and VMINNMA instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vmaxnma-vminnma-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.l b/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..fdc8aac7a80bc41229f9965e5fa65b68bbb19799
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.l
@@ -0,0 +1,27 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vmaxnma.f64 q0,q1'
+[^:]*:11: Error: bad type in SIMD instruction -- `vmaxnma.i16 q0,q1'
+[^:]*:12: Error: bad type in SIMD instruction -- `vminnma.f64 q0,q1'
+[^:]*:13: Error: bad type in SIMD instruction -- `vminnma.i16 q0,q1'
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Error: syntax error -- `vmaxnmaeq.f32 q0,q1'
+[^:]*:18: Error: syntax error -- `vmaxnmaeq.f32 q0,q1'
+[^:]*:20: Error: syntax error -- `vmaxnmaeq.f32 q0,q1'
+[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxnmat.f32 q0,q1'
+[^:]*:23: Error: instruction missing MVE vector predication code -- `vmaxnma.f32 q0,q1'
+[^:]*:25: Error: syntax error -- `vminnmaeq.f32 q0,q1'
+[^:]*:26: Error: syntax error -- `vminnmaeq.f32 q0,q1'
+[^:]*:28: Error: syntax error -- `vminnmaeq.f32 q0,q1'
+[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vminnmat.f32 q0,q1'
+[^:]*:31: Error: instruction missing MVE vector predication code -- `vminnma.f32 q0,q1'
diff --git a/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.s b/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..43f6dce36a45a7c8f572e4eb1c3c5503db8649d8
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.s
@@ -0,0 +1,31 @@
+.macro cond, op
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().f16 q0, q1
+.endr
+.endm
+
+.syntax unified
+.thumb
+vmaxnma.f64 q0, q1
+vmaxnma.i16 q0, q1
+vminnma.f64 q0, q1
+vminnma.i16 q0, q1
+cond vmaxnma
+cond vminnma
+it eq
+vmaxnmaeq.f32 q0, q1
+vmaxnmaeq.f32 q0, q1
+vpst
+vmaxnmaeq.f32 q0, q1
+vmaxnmat.f32 q0, q1
+vpst
+vmaxnma.f32 q0, q1
+it eq
+vminnmaeq.f32 q0, q1
+vminnmaeq.f32 q0, q1
+vpst
+vminnmaeq.f32 q0, q1
+vminnmat.f32 q0, q1
+vpst
+vminnma.f32 q0, q1
next prev parent reply other threads:[~2019-05-01 17:12 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-01 16:51 [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 16:53 ` [PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fp Andre Vieira (lists)
2019-05-01 16:55 ` [PATCH 2/57][Arm][GAS] Add support for MVE instructions: vpst, vadd, vsub and vabd Andre Vieira (lists)
2019-05-02 10:56 ` Nick Clifton
2019-05-13 13:42 ` Andre Vieira (lists)
[not found] ` <98e50dc4-7b0e-d727-0c20-34711be86533@redhat.com>
[not found] ` <4e56a5f3-bcde-f4cd-21d4-35cc3f11b5e8@arm.com>
2019-05-14 16:53 ` Nick Clifton
2019-05-14 16:54 ` Nick Clifton
2019-05-01 16:56 ` [PATCH 3/57][Arm][GAS] Add support for MVE instructions: vabs and vneg Andre Vieira (lists)
2019-05-01 16:57 ` [PATCH 4/57][Arm][GAS] Add support for MVE instructions: vabav, vmladav and vmlsdav Andre Vieira (lists)
2019-05-01 16:59 ` [PATCH 5/57][Arm][GAS] Add support for MVE instructions: vmull{b,t} Andre Vieira (lists)
2019-05-01 17:00 ` [PATCH 6/57][Arm][GAS] Add support for MVE instructions: vst/vld{2,4} Andre Vieira (lists)
2019-05-01 17:01 ` [PATCH 7/57][Arm][GAS] Add support for MVE instructions: vstr/vldr Andre Vieira (lists)
2019-05-01 17:02 ` [PATCH 8/57][Arm][GAS] Add support for MVE instructions: vcvt Andre Vieira (lists)
2019-05-01 17:03 ` [PATCH 9/57][Arm][GAS] Add support for MVE instructions: vmov Andre Vieira (lists)
2019-05-01 17:03 ` [PATCH 10/57][Arm][GAS] Add support for MVE instructions: vcmp and vpt Andre Vieira (lists)
2019-05-01 17:05 ` [PATCH 11/57][Arm][GAS] Add support for MVE instructions: vadc, vsbc and vbrsr Andre Vieira (lists)
2019-05-01 17:06 ` [PATCH 12/57][Arm][GAS] Add support for MVE instructions: vaddlv and vaddv Andre Vieira (lists)
2019-05-01 17:07 ` [PATCH 13/57][Arm][GAS] Add support for MVE instructions: vand, vbic, vorr, vorn and veor Andre Vieira (lists)
2019-05-01 17:08 ` [PATCH 14/57][Arm][GAS] Add support for MVE instructions: vcadd, vcmla and vcmul Andre Vieira (lists)
2019-05-01 17:09 ` [PATCH 16/57][Arm][GAS] Add support for MVE instructions: vdup, vddup, vdwdup, vidup and viwdup Andre Vieira (lists)
2019-05-01 17:09 ` [PATCH 15/57][Arm][GAS] Add support for MVE instructions: vcls, vclz and vfmas Andre Vieira (lists)
2019-05-01 17:11 ` [PATCH 17/57][Arm][GAS] Add support for MVE instructions: vfma and vfms Andre Vieira (lists)
2019-05-01 17:12 ` [PATCH 18/57][Arm][GAS] Add support for MVE instructions: vhcadd, vhadd, vhsub and vrhadd Andre Vieira (lists)
2019-05-01 17:12 ` Andre Vieira (lists) [this message]
2019-05-01 17:13 ` [PATCH 20/57][Arm][GAS] Add support for MVE instructions: vmaxnmv, vmaxnmav, vminnmv and vminnmav Andre Vieira (lists)
2019-05-01 17:13 ` [PATCH 21/57][Arm][GAS] Add support for MVE instructions: vmaxv, vmaxav, vminv and vminav Andre Vieira (lists)
2019-05-01 17:15 ` [PATCH 23/57][Arm][GAS] Add support for MVE instructions: vmla, vmul, vqadd and vqsub Andre Vieira (lists)
2019-05-01 17:15 ` [PATCH 22/57][Arm][GAS] Add support for MVE instructions: vmlaldav, vmlalv, vmlsldav, vrmlaldavh, vrmlalvh and vrmlsldavh Andre Vieira (lists)
2019-05-01 17:16 ` [PATCH 24/57][Arm][GAS] Add support for MVE instructions: vmlas, vmulh and vrmulh Andre Vieira (lists)
2019-05-01 17:17 ` [PATCH 26/57][Arm][GAS] Add support for MVE instructions: vpnot and vpsel Andre Vieira (lists)
2019-05-01 17:17 ` [PATCH 25/57][Arm][GAS] Add support for MVE instruction: vmvn, vqabs and vqneg Andre Vieira (lists)
2019-05-01 17:18 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 17:19 ` [PATCH 28/57][Arm][GAS] Add support for MVE instructions: vqdmlah, vqrdmlah, vqdmlash, vqrdmlash, vqdmulh and vqrdmulh Andre Vieira (lists)
2019-05-01 17:30 ` [PATCH 27/57][Arm][GAS] Add support for MVE instructions: vqdmladh, vqrdmladh, vqdmlsdh and vqrdmlsdh Andre Vieira (lists)
2019-05-01 17:31 ` [PATCH 29/57][Arm][GAS] Add support for MVE instructions: vqdmullt and vqdmullb Andre Vieira (lists)
2019-05-01 17:32 ` [PATCH 31/57][Arm][GAS] Add support for MVE instructions: vshrn[tb], vrshrn[tb], vqshrn[tb], vqshrun[tb], vqrshrn[tb] and vqrshrun[tb] Andre Vieira (lists)
2019-05-01 17:32 ` [PATCH 30/57][Arm][GAS] Add support for MVE instructions: vqmovnt, vqmovnb, vqmovunt, vqmovunb, vqrshl and vrshl Andre Vieira (lists)
2019-05-01 17:33 ` [PATCH 32/57][Arm][GAS] Add support for MVE instructions: vrintn, vrintx, vrinta, vrintz, vrintm and vrintp Andre Vieira (lists)
2019-05-01 17:34 ` [PATCH 34/57][Arm][GAS] Add support for MVE instructions: vshl and vqshl Andre Vieira (lists)
2019-05-01 17:34 ` [PATCH 33/57][Arm][GAS] Add support for MVE instructions: vshr, vrshr, vsli, vsri, vrev16, vrev32 and vrev64 Andre Vieira (lists)
2019-05-01 17:36 ` [PATCH 35/57][Arm][GAS] Add support for MVE instructions: vshlc and vshll Andre Vieira (lists)
2019-05-01 17:36 ` [PATCH 36/57][Arm][GAS] Add support for MVE instructions: wlstp, dlstp, letp and lctp Andre Vieira (lists)
2019-05-01 17:38 ` [PATCH 37/57][Arm][OBJDUMP] Add framework for MVE instructions Andre Vieira (lists)
2019-05-01 17:38 ` [PATCH 38/57][Arm][OBJDUMP] Disable the use of MVE reserved coproc numbers in coprocessor instructions Andre Vieira (lists)
2019-05-01 17:39 ` [PATCH 39/57][Arm][OBJDUMP] Add support for MVE instructions: vpt, vpst and vcmp Andre Vieira (lists)
2019-05-01 17:40 ` [PATCH 40/57][Arm][OBJDUMP] Add support for MVE instructions: vdup, veor, vfma, vfms, vhadd, vhsub and vrhadd Andre Vieira (lists)
2019-05-01 17:40 ` [PATCH 41/57][Arm][OBJDUMP] Add support for MVE instructions: vld[24] and vst[24] Andre Vieira (lists)
2019-05-01 17:41 ` [PATCH 42/57][Arm][OBJDUMP] Add support for MVE instructions: vldr[bhw] and vstr[bhw] Andre Vieira (lists)
2019-05-01 17:42 ` [PATCH 43/57][Arm][OBJDUMP] Add support for MVE instructions: scatter stores and gather loads Andre Vieira (lists)
2019-05-01 17:43 ` [PATCH 44/57][Arm][OBJDUMP] Add support for MVE instructions: vcvt and vrint Andre Vieira (lists)
2019-05-02 9:54 ` Nick Clifton
2019-05-13 13:38 ` Andre Vieira (lists)
2019-05-01 17:44 ` [PATCH 46/57][Arm][OBJDUMP] Add support for MVE instructions: vmovl, vmull, vqdmull, vqmovn, vqmovun and vmovn Andre Vieira (lists)
2019-05-01 17:44 ` [PATCH 45/57][Arm][OBJDUMP] Add support for MVE instructions: vmov, vmvn, vorr, vorn, vmovx and vbic Andre Vieira (lists)
2019-05-01 17:45 ` [PATCH 47/57][Arm][OBJDUMP] Add support for MVE instructions: vaddv, vmlaldav, vmladav, vmlas, vrmlsldavh, vmlsldav, vmlsdav, vrmlaldavh, vqdmlah, vqrdmlash, vqrdmlash, vqdmlsdh, vqrdmlsdh, vqdmulh and vqrdmulh Andre Vieira (lists)
2019-05-01 17:46 ` [PATCH 49/57][Arm][OBJDUMP] Add support for MVE complex number instructions Andre Vieira (lists)
2019-05-01 17:46 ` [PATCH 48/57][Arm][OBJDUMP] Add support for MVE instructions: vddup, vdwdup, vidup and viwdup Andre Vieira (lists)
2019-05-01 17:47 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 17:48 ` [PATCH 51/57][Arm][OBJDUMP] Add support for MVE instructions: lctp, letp, wlstp and dlstp Andre Vieira (lists)
2019-05-01 17:48 ` [PATCH 52/57][Arm][OBJDUMP] Add support for MVE instructions: vadc, vabav, vabd, vabs, vadd, vsbc and vsub Andre Vieira (lists)
2019-05-01 17:49 ` [PATCH 53/57][Arm][OBJDUMP] Add support for MVE instructions: vand, vbrsr, vcls, vclz and vctp Andre Vieira (lists)
2019-05-01 17:50 ` [PATCH 54/57][Arm][OBJDUMP] Add support for MVE instructions: vmax(a), vmax(a)v, vmaxnm(a), vmaxnm(a)v, vmin(a), vmin(a)v, vminnm(a), vminnm(a)v and vmla Andre Vieira (lists)
2019-05-01 17:50 ` [PATCH 55/57][Arm][OBJDUMP] Add support for MVE instructions: vmul, vmulh, vrmulh and vneg Andre Vieira (lists)
2019-05-01 17:51 ` [PATCH 56/57][Arm][OBJDUMP] Add support for MVE instructions: vpnot, vpsel, vqabs, vqadd, vqsub, vqneg and vrev Andre Vieira (lists)
2019-05-01 18:23 ` [PATCH 57/57][Arm][GAS] MVE Tests Andre Vieira (lists)
2019-05-01 18:24 ` Andre Vieira (lists)
2019-05-01 18:25 ` Andre Vieira (lists)
2019-05-01 18:25 ` Andre Vieira (lists)
2019-05-02 10:03 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Nick Clifton
2019-05-02 10:18 ` Nick Clifton
2019-05-13 13:39 ` [PATCH, binutils, Arm] Add Armv8.1-M Mainline and MVE enablement to NEWS Andre Vieira (lists)
2019-05-02 13:39 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Nick Clifton
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=2a328096-ec13-2e4e-07e6-2f820bd06b6b@arm.com \
--to=andre.simoesdiasvieira@arm.com \
--cc=binutils@sourceware.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).