diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index de3c8b69b767a9232488129985ebb540b08c2192..f490b91b685d4c0089bd8c4ad055b534d389aa8b 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -15593,6 +15593,26 @@ do_mve_vcmp (void) return; } +static void +do_mve_vmaxa_vmina (void) +{ + if (inst.cond > COND_ALWAYS) + inst.pred_insn_type = INSIDE_VPT_INSN; + else + inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; + + enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL); + struct neon_type_el et + = neon_check_type (2, rs, N_EQK, N_KEY | N_S8 | N_S16 | N_S32); + + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= neon_logbits (et.size) << 18; + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[1].reg) << 5; + inst.instruction |= LOW4 (inst.operands[1].reg); + inst.is_neon = 1; +} + static void do_mve_vfmas (void) { @@ -15662,6 +15682,26 @@ do_mve_viddup (void) inst.is_neon = 1; } +static void +do_mve_vmaxnma_vminnma (void) +{ + enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL); + struct neon_type_el et + = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY); + + if (inst.cond > COND_ALWAYS) + inst.pred_insn_type = INSIDE_VPT_INSN; + else + inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; + + inst.instruction |= (et.size == 16) << 28; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[1].reg) << 5; + inst.instruction |= LOW4 (inst.operands[1].reg); + inst.is_neon = 1; +} + static void do_mve_vcmul (void) { @@ -16704,6 +16744,11 @@ do_neon_dyadic_if_su (void) struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK, N_SUF_32 | N_KEY); + constraint ((inst.instruction == ((unsigned) N_MNEM_vmax) + || inst.instruction == ((unsigned) N_MNEM_vmin)) + && et.type == NT_float + && !ARM_CPU_HAS_FEATURE (cpu_variant,fpu_neon_ext_v1), BAD_FPU); + if (check_simd_pred_availability (et.type == NT_float, NEON_CHECK_ARCH | NEON_CHECK_CC)) return; @@ -19746,12 +19791,13 @@ do_vsel (void) static void do_vmaxnm (void) { - set_pred_insn_type (OUTSIDE_PRED_INSN); + if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) + set_pred_insn_type (OUTSIDE_PRED_INSN); if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS) return; - if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL) + if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH8)) return; neon_dyadic_misc (NT_untyped, N_F_16_32, 0); @@ -22954,8 +23000,6 @@ static const struct asm_opcode insns[] = nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel), nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel), nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel), - nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm), - nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm), nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr), nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz), nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx), @@ -23674,9 +23718,7 @@ static const struct asm_opcode insns[] = NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */ nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), - nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), - nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall back to neon_dyadic_if_su. */ @@ -24373,11 +24415,15 @@ static const struct asm_opcode insns[] = mCEF(vdwdup, _vdwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup), mCEF(vidup, _vidup, 3, (RMQ, RRe, EXPi), mve_viddup), mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup), + mToC("vmaxa", ee330e81, 2, (RMQ, RMQ), mve_vmaxa_vmina), + mToC("vmina", ee331e81, 2, (RMQ, RMQ), mve_vmaxa_vmina), #undef THUMB_VARIANT #define THUMB_VARIANT & mve_fp_ext mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul), mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas), + mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma), + mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma), #undef ARM_VARIANT #define ARM_VARIANT & fpu_vfp_ext_v1 @@ -24421,6 +24467,8 @@ static const struct asm_opcode insns[] = mnUF(vcvtp, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtp), mnUF(vcvtn, _vcvta, 3, (RNSDQMQ, oRNSDQMQ, oI32z), neon_cvtn), mnUF(vcvtm, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtm), + mnUF(vmaxnm, _vmaxnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm), + mnUF(vminnm, _vminnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm), #undef ARM_VARIANT #define ARM_VARIANT & fpu_neon_ext_v1 @@ -24439,6 +24487,8 @@ static const struct asm_opcode insns[] = MNUF(vhadd, 00000000, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su), MNUF(vrhadd, 00000100, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_i_su), MNUF(vhsub, 00000200, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su), + mnUF(vmin, _vmin, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su), + mnUF(vmax, _vmax, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su), #undef ARM_VARIANT #define ARM_VARIANT & arm_ext_v8_3 diff --git a/gas/testsuite/gas/arm/mve-vmax-vmin-bad.d b/gas/testsuite/gas/arm/mve-vmax-vmin-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..9ffbca4becedc3882251c5c4341d0cafb81f8ff3 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmax-vmin-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE VMAX and VMIN instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vmax-vmin-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vmax-vmin-bad.l b/gas/testsuite/gas/arm/mve-vmax-vmin-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..17d5c74602151bc387d082a95cc050d5ab3e565f --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmax-vmin-bad.l @@ -0,0 +1,27 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vmax.s64 q0,q1,q2' +[^:]*:11: Error: selected FPU does not support instruction -- `vmax.f16 q0,q1,q2' +[^:]*:12: Error: bad type in SIMD instruction -- `vmax.u64 q0,q1,q2' +[^:]*:13: Error: selected FPU does not support instruction -- `vmax.f32 q0,q1,q2' +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Error: syntax error -- `vmaxeq.s16 q0,q1,q2' +[^:]*:18: Error: syntax error -- `vmaxeq.s16 q0,q1,q2' +[^:]*:20: Error: syntax error -- `vmaxeq.s16 q0,q1,q2' +[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxt.s16 q0,q1,q2' +[^:]*:23: Error: instruction missing MVE vector predication code -- `vmax.s16 q0,q1,q2' +[^:]*:25: Error: syntax error -- `vmineq.u32 q0,q1,q2' +[^:]*:26: Error: syntax error -- `vmineq.u32 q0,q1,q2' +[^:]*:28: Error: syntax error -- `vmineq.u32 q0,q1,q2' +[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vmint.u32 q0,q1,q2' +[^:]*:31: Error: instruction missing MVE vector predication code -- `vmin.u32 q0,q1,q2' diff --git a/gas/testsuite/gas/arm/mve-vmax-vmin-bad.s b/gas/testsuite/gas/arm/mve-vmax-vmin-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..b7b92427c2235574efba55eb2539d39b2ded1c65 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmax-vmin-bad.s @@ -0,0 +1,31 @@ +.macro cond, op +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().s8 q0, q1, q2 +.endr +.endm + +.syntax unified +.thumb +vmax.s64 q0, q1, q2 +vmax.f16 q0, q1, q2 +vmax.u64 q0, q1, q2 +vmax.f32 q0, q1, q2 +cond vmax +cond vmin +it eq +vmaxeq.s16 q0, q1, q2 +vmaxeq.s16 q0, q1, q2 +vpst +vmaxeq.s16 q0, q1, q2 +vmaxt.s16 q0, q1, q2 +vpst +vmax.s16 q0, q1, q2 +it eq +vmineq.u32 q0, q1, q2 +vmineq.u32 q0, q1, q2 +vpst +vmineq.u32 q0, q1, q2 +vmint.u32 q0, q1, q2 +vpst +vmin.u32 q0, q1, q2 diff --git a/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.d b/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..11105db987b6239c556005557d1d9a074059a785 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE VMAXA and VMINA instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vmaxa-vmina-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.l b/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..0e2ffed6d54de7a829c33b291aa42069734827c4 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.l @@ -0,0 +1,29 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vmaxa.u8 q0,q1' +[^:]*:11: Error: bad type in SIMD instruction -- `vmaxa.s64 q0,q1' +[^:]*:12: Error: bad type in SIMD instruction -- `vmaxa.f16 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vmina.u8 q0,q1' +[^:]*:14: Error: bad type in SIMD instruction -- `vmina.s64 q0,q1' +[^:]*:15: Error: bad type in SIMD instruction -- `vmina.f16 q0,q1' +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:19: Error: syntax error -- `vmaxaeq.s8 q0,q1' +[^:]*:20: Error: syntax error -- `vmaxaeq.s8 q0,q1' +[^:]*:22: Error: syntax error -- `vmaxaeq.s8 q0,q1' +[^:]*:23: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxat.s8 q0,q1' +[^:]*:25: Error: instruction missing MVE vector predication code -- `vmaxa.s8 q0,q1' +[^:]*:27: Error: syntax error -- `vminaeq.s8 q0,q1' +[^:]*:28: Error: syntax error -- `vminaeq.s8 q0,q1' +[^:]*:30: Error: syntax error -- `vminaeq.s8 q0,q1' +[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vminat.s8 q0,q1' +[^:]*:33: Error: instruction missing MVE vector predication code -- `vmina.s8 q0,q1' diff --git a/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.s b/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..08cc60a2baca34108d4003fb658dc25afc36081b --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmaxa-vmina-bad.s @@ -0,0 +1,33 @@ +.macro cond, op +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().s8 q0, q1 +.endr +.endm + +.syntax unified +.thumb +vmaxa.u8 q0, q1 +vmaxa.s64 q0, q1 +vmaxa.f16 q0, q1 +vmina.u8 q0, q1 +vmina.s64 q0, q1 +vmina.f16 q0, q1 +cond vmaxa +cond vmina +it eq +vmaxaeq.s8 q0, q1 +vmaxaeq.s8 q0, q1 +vpst +vmaxaeq.s8 q0, q1 +vmaxat.s8 q0, q1 +vpst +vmaxa.s8 q0, q1 +it eq +vminaeq.s8 q0, q1 +vminaeq.s8 q0, q1 +vpst +vminaeq.s8 q0, q1 +vminat.s8 q0, q1 +vpst +vmina.s8 q0, q1 diff --git a/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.d b/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..4617cd4c3dc2e0bb9420d60e160ff2026ce59442 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE VMAXNM and VMINNM instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vmaxnm-vminnm-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.l b/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..012ab35bf18d2908f61dfdbc8c3028bd113d06ce --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.l @@ -0,0 +1,27 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vmaxnm.f64 q0,q1,q2' +[^:]*:11: Error: bad type in SIMD instruction -- `vmaxnm.i16 q0,q1,q2' +[^:]*:12: Error: bad type in SIMD instruction -- `vminnm.f64 q0,q1,q2' +[^:]*:13: Error: bad type in SIMD instruction -- `vminnm.i16 q0,q1,q2' +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Error: syntax error -- `vmaxnmeq.f32 q0,q1,q2' +[^:]*:18: Error: syntax error -- `vmaxnmeq.f32 q0,q1,q2' +[^:]*:20: Error: syntax error -- `vmaxnmeq.f32 q0,q1,q2' +[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxnmt.f32 q0,q1,q2' +[^:]*:23: Error: instruction missing MVE vector predication code -- `vmaxnm.f32 q0,q1,q2' +[^:]*:25: Error: syntax error -- `vminnmeq.f32 q0,q1,q2' +[^:]*:26: Error: syntax error -- `vminnmeq.f32 q0,q1,q2' +[^:]*:28: Error: syntax error -- `vminnmeq.f32 q0,q1,q2' +[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vminnmt.f32 q0,q1,q2' +[^:]*:31: Error: instruction missing MVE vector predication code -- `vminnm.f32 q0,q1,q2' diff --git a/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.s b/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..2b6436cc6a27d51d3a01eafbb2de10afe76f3eb6 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmaxnm-vminnm-bad.s @@ -0,0 +1,31 @@ +.macro cond, op +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().f16 q0, q1, q2 +.endr +.endm + +.syntax unified +.thumb +vmaxnm.f64 q0, q1, q2 +vmaxnm.i16 q0, q1, q2 +vminnm.f64 q0, q1, q2 +vminnm.i16 q0, q1, q2 +cond vmaxnm +cond vminnm +it eq +vmaxnmeq.f32 q0, q1, q2 +vmaxnmeq.f32 q0, q1, q2 +vpst +vmaxnmeq.f32 q0, q1, q2 +vmaxnmt.f32 q0, q1, q2 +vpst +vmaxnm.f32 q0, q1, q2 +it eq +vminnmeq.f32 q0, q1, q2 +vminnmeq.f32 q0, q1, q2 +vpst +vminnmeq.f32 q0, q1, q2 +vminnmt.f32 q0, q1, q2 +vpst +vminnm.f32 q0, q1, q2 diff --git a/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.d b/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..5d11eee34c4040fbef21c0c3799e3c98d75ca123 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE VMAXNMA and VMINNMA instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vmaxnma-vminnma-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.l b/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..fdc8aac7a80bc41229f9965e5fa65b68bbb19799 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.l @@ -0,0 +1,27 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vmaxnma.f64 q0,q1' +[^:]*:11: Error: bad type in SIMD instruction -- `vmaxnma.i16 q0,q1' +[^:]*:12: Error: bad type in SIMD instruction -- `vminnma.f64 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vminnma.i16 q0,q1' +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Error: syntax error -- `vmaxnmaeq.f32 q0,q1' +[^:]*:18: Error: syntax error -- `vmaxnmaeq.f32 q0,q1' +[^:]*:20: Error: syntax error -- `vmaxnmaeq.f32 q0,q1' +[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxnmat.f32 q0,q1' +[^:]*:23: Error: instruction missing MVE vector predication code -- `vmaxnma.f32 q0,q1' +[^:]*:25: Error: syntax error -- `vminnmaeq.f32 q0,q1' +[^:]*:26: Error: syntax error -- `vminnmaeq.f32 q0,q1' +[^:]*:28: Error: syntax error -- `vminnmaeq.f32 q0,q1' +[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vminnmat.f32 q0,q1' +[^:]*:31: Error: instruction missing MVE vector predication code -- `vminnma.f32 q0,q1' diff --git a/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.s b/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..43f6dce36a45a7c8f572e4eb1c3c5503db8649d8 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmaxnma-vminnma-bad.s @@ -0,0 +1,31 @@ +.macro cond, op +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().f16 q0, q1 +.endr +.endm + +.syntax unified +.thumb +vmaxnma.f64 q0, q1 +vmaxnma.i16 q0, q1 +vminnma.f64 q0, q1 +vminnma.i16 q0, q1 +cond vmaxnma +cond vminnma +it eq +vmaxnmaeq.f32 q0, q1 +vmaxnmaeq.f32 q0, q1 +vpst +vmaxnmaeq.f32 q0, q1 +vmaxnmat.f32 q0, q1 +vpst +vmaxnma.f32 q0, q1 +it eq +vminnmaeq.f32 q0, q1 +vminnmaeq.f32 q0, q1 +vpst +vminnmaeq.f32 q0, q1 +vminnmat.f32 q0, q1 +vpst +vminnma.f32 q0, q1