From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 079813858403 for ; Mon, 12 Sep 2022 20:09:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 079813858403 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0187473.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28CIrnN6015935 for ; Mon, 12 Sep 2022 20:09:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : mime-version : to : from : subject : content-type : content-transfer-encoding; s=pp1; bh=YabTPlT7GYJOBrhyUWpXvWQPS3CWxrpjLJNKgS4xiyU=; b=o9a/4R/8orqA6ElBWaKSfqbdTyjqtHCUuSyuj1wMcVvepuqxv/PANVn2MatZnOs/T+Bx 6LjC1HdO+Xt/O0lqwBfyMXGctFKiQ6z+nPTVpN/UytV9ZotOHTPmBzXA6Ee2XktgxJza wkmc9nBfdyW/xiqk0Benwx8ezq65qjfb2f9lRY5Jy//uf7SHZQSsr5pG6AP4Qmv1wjk0 VB2VYQrpjOJzUlunsKNKajrFvljirtSgbzDqrbieTbYTOKfzGzi132fatqcRvoQQ1C3b eTs3uIewnEi0dZ0ip0x5CeBsH7a3yr53JhBaXz/hXv3Liz0JMoKp5a1qgm47xw5pDhYV Vg== Received: from ppma03dal.us.ibm.com (b.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.11]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3jjaewt7s9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 12 Sep 2022 20:08:59 +0000 Received: from pps.filterd (ppma03dal.us.ibm.com [127.0.0.1]) by ppma03dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 28CK4kic022573 for ; Mon, 12 Sep 2022 20:08:59 GMT Received: from b01cxnp22034.gho.pok.ibm.com (b01cxnp22034.gho.pok.ibm.com [9.57.198.24]) by ppma03dal.us.ibm.com with ESMTP id 3jgj7a3fub-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 12 Sep 2022 20:08:59 +0000 Received: from b01ledav001.gho.pok.ibm.com (b01ledav001.gho.pok.ibm.com [9.57.199.106]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 28CK8weH3736290 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Mon, 12 Sep 2022 20:08:58 GMT Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3E60628059 for ; Mon, 12 Sep 2022 20:08:58 +0000 (GMT) Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0DCDB28058 for ; Mon, 12 Sep 2022 20:08:58 +0000 (GMT) Received: from [9.160.112.244] (unknown [9.160.112.244]) by b01ledav001.gho.pok.ibm.com (Postfix) with ESMTP for ; Mon, 12 Sep 2022 20:08:57 +0000 (GMT) Message-ID: <2ffb1e07-8c9e-c739-d652-16f53454eaa2@linux.ibm.com> Date: Mon, 12 Sep 2022 15:08:57 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Content-Language: en-US To: Binutils From: Peter Bergner Subject: [PATCH,pushed] ppc: Document the -mfuture and -Mfuture options and make them usable Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: V86OO0mBx16rVSv4kiBC08xdh4cVjEY8 X-Proofpoint-GUID: V86OO0mBx16rVSv4kiBC08xdh4cVjEY8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-12_14,2022-09-12_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 adultscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 suspectscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2209120067 X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The -mfuture and -Mfuture options which are used for adding potential new ISA instructions were not documented. They also lacked a bitmask so new instructions could not be enabled by those options. Fixed. Committed and pushed. Peter binutils/ * doc/binutils.texi: Document -Mfuture. gas/ * config/tc-ppc.c: Document -mfuture * doc/c-ppc.texi: Likewise. include/ * opcode/ppc.h (PPC_OPCODE_FUTURE): Define. opcodes/ * ppc-dis.c (ppc_opts) : Use it. * ppc-opc.c (FUTURE): Define. --- binutils/doc/binutils.texi | 2 +- gas/config/tc-ppc.c | 2 ++ gas/doc/c-ppc.texi | 3 +++ include/opcode/ppc.h | 3 +++ opcodes/ppc-dis.c | 3 ++- opcodes/ppc-opc.c | 1 + 6 files changed, 12 insertions(+), 2 deletions(-) diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi index f61a619ec78..1499db5728c 100644 --- a/binutils/doc/binutils.texi +++ b/binutils/doc/binutils.texi @@ -2638,7 +2638,7 @@ rather than @code{li}. All of the @option{-m} arguments for @option{ppc32}, @option{ppc64}, @option{ppc64bridge}, @option{ppcps}, @option{pwr}, @option{pwr2}, @option{pwr4}, @option{pwr5}, @option{pwr5x}, @option{pwr6}, @option{pwr7}, @option{pwr8}, @option{pwr9}, @option{pwr10}, -@option{pwrx}, @option{titan}, and @option{vle}. +@option{pwrx}, @option{titan}, @option{vle}, and @option{future}. @option{32} and @option{64} modify the default or a prior CPU selection, disabling and enabling 64-bit insns respectively. In addition, @option{altivec}, @option{any}, @option{htm}, @option{vsx}, diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c index b5aad4b6e3e..37a8b54a28f 100644 --- a/gas/config/tc-ppc.c +++ b/gas/config/tc-ppc.c @@ -1384,6 +1384,8 @@ PowerPC options:\n")); fprintf (stream, _("\ -mlibresoc generate code for Libre-SOC architecture\n")); fprintf (stream, _("\ +-mfuture generate code for 'future' architecture\n")); + fprintf (stream, _("\ -mcell generate code for Cell Broadband Engine architecture\n")); fprintf (stream, _("\ -mcom generate code for Power/PowerPC common instructions\n")); diff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi index 81254935239..2986d3de7f8 100644 --- a/gas/doc/c-ppc.texi +++ b/gas/doc/c-ppc.texi @@ -150,6 +150,9 @@ Generate code for Power9 architecture. @item -mpower10, -mpwr10 Generate code for Power10 architecture. +@item -mfuture +Generate code for 'future' architecture. + @item -mcell @item -mcell Generate code for Cell Broadband Engine architecture. diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index 3578f0d218d..c5d96a265a8 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -240,6 +240,9 @@ extern const unsigned int spe2_num_opcodes; /* Opcode is only supported by SVP64 extensions (LibreSOC architecture). */ #define PPC_OPCODE_SVP64 0x800000000000ull +/* Opcode is only supported by 'future' architecture. */ +#define PPC_OPCODE_FUTURE 0x1000000000000ull + /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index 97f2e201e9a..3ba06274b21 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -208,7 +208,8 @@ struct ppc_mopt ppc_opts[] = { { "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 - | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), + | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX + | PPC_OPCODE_FUTURE), 0 }, { "ppc", PPC_OPCODE_PPC, 0 }, diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 934b1bf4e85..25c96ba87b7 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -4847,6 +4847,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) #define POWER8 PPC_OPCODE_POWER8 #define POWER9 PPC_OPCODE_POWER9 #define POWER10 PPC_OPCODE_POWER10 +#define FUTURE PPC_OPCODE_FUTURE #define CELL PPC_OPCODE_CELL #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \