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Received: from DU2PR04MB8790.eurprd04.prod.outlook.com (2603:10a6:10:2e1::23) by VI1PR04MB7181.eurprd04.prod.outlook.com (2603:10a6:800:12a::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6699.20; Fri, 18 Aug 2023 06:53:57 +0000 Received: from DU2PR04MB8790.eurprd04.prod.outlook.com ([fe80::79a:54ba:8003:fbe7]) by DU2PR04MB8790.eurprd04.prod.outlook.com ([fe80::79a:54ba:8003:fbe7%6]) with mapi id 15.20.6678.029; Fri, 18 Aug 2023 06:53:57 +0000 Message-ID: <3058d69f-9822-f30b-5669-d9329573a665@suse.com> Date: Fri, 18 Aug 2023 08:53:55 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.14.0 Subject: Re: [PATCH v2] Support Intel AVX10.1 Content-Language: en-US To: "Jiang, Haochen" Cc: "binutils@sourceware.org" , "hjl.tools@gmail.com" References: <5eb31b18-e1ba-dbf1-bddb-ff03b61b25de@suse.com> <20230814064535.3228154-1-haochen.jiang@intel.com> <4c47b6af-ed3f-ec3f-4a28-cd6e052470f9@suse.com> <93eedcac-d2b5-578e-0630-2ed71bf5ddae@suse.com> From: Jan Beulich In-Reply-To: Content-Type: text/plain; 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See the uses of EVex, for example. As said above, I think >>>> maximum vector width and ISA extensions want dealing with separately, >>>> and only the latter would generally qualify for Cpu* flags. Furthermore >>>> recall that the attribute wants widening sooner or later, and Cpu* >>>> flags are uniformly boolean. Only attributes may have numeric values. >>> >>> After I checked code, I still miss the point here. >>> >>> My concern is how to actually disable the zmm registers for AVX10/256 >>> and ymm registers for theoretical AVX10/128. >> >> That's the easy part: That'll want doing in check_register(). The issue >> is with insns which do 512-bit operation despite not using zmm registers >> (think of vfpclassp* with memory operand). >> >>> I suppose i386_opcode_modifier >>> is more related to building up the whole encoding. But each AVX10.X/256 is an >>> actual arch. >> >> I wouldn't agree with the last sentence, but ... >> >>> Adding a feature in i386_opcode_modifier can indicate what is the maximum >>> vector length the instruction is allowed on all archs but has nothing to do with >>> disabling zmm registers on an 256-bit only arch. >> >> ... you still have a point here. Maybe it only wants to be a boolean, >> indicating that an insn is vector-length sensitive. Yet re-using the >> EVex attribute continues to be an option: With vector length >> constrained to 256 (or 128) bits, EVEX512 (or EVEX256) simply become >> unavailable for encoding, and EVEXDYN would be equally constrained. >> And if re-using that attribute continues to be an option, adding a >> new non-boolean attribute clearly is also possible. >> >> So I guess there may have been a slight misunderstanding: I was >> suggesting an attribute expressing permissible vector lengths (hence >> the consideration of re-using EVex), which would then be checked >> against the established (through whatever directive / command line >> option) maximum vector length. I did not suggest a new "max vector >> length" attribute. > > Just to mention it: I've meanwhile realized that re-using EVex here will > collide with APX introducing EVEX-encoded KMOV*. So it'll need to be a > very similar but distinct attribute. And if it turned out that the > attribute then is really only needed on the mask insns (using EVex > elsewhere), it could equally well be a "permitted vector lengths" or a > "maximum vector length" one, as both are then equal. Question is what > AVX10/128 would mean for VEX-encoded insns. It seems likely that 256-bit > forms wouldn't be permitted there either then, in which case applicable > VEX-encoded insns would then need to gain such attributes as well. In > that case it would of course be more logical to stick to "permitted > vector lengths". Sorry, yet another update. For one it can't be "maximum", but only "minimum". And I meanwhile think "permitted" along the lines of EVex won't catch it either. I guess I will want to take a stab myself ... Jan