[PATCH v2] x86: Support Zhaoxin PadLock RNG2 instruction

[Mayshao-oc <Mayshao-oc@zhaoxin.com>]

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Hi all:
     This patch adds support for Zhaoxin PadLock RNG2 instruction, the
CPUID EDX bit[23] indicates its enablement, it includes REP XRNG2
instruction.
     Test ok, ok for trunk?

Changes in V2:
1. Change the indenting correctly and change the boolean expression in output_insn()
2. Rename RNG2 to PadLockRNG2
3. Add PadLockRNG2 to dependency table.

BR
MayShao

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From 0c006e2ae64b9217b20d76911d248b4c98ae191e Mon Sep 17 00:00:00 2001
From: MayShao-oc <MayShao-oc@zhaoxin.com>
Date: Wed, 8 Jan 2025 16:16:20 +0800
Subject: [PATCH v2] x86: Support x86 Zhaoxin PadLockRNG2 instruction
Hi all:
     This patch adds support for Zhaoxin PadLock RNG2 instruction, the
CPUID EDX bit[23] indicates its enablement, it includes REP XRNG2
instruction.
     Test ok, ok for trunk?
BR
MayShao

gas/ChangeLog:

	* NEWS: Support Zhaoxin PadLock RNG2 instruction.
	* config/tc-i386.c (add_branch_prefix_frag_p): Don't add prefix to
	PadLock RNG2 instruction.
	(output_insn): Handle PadLock RNG2 instruction.
	* doc/c-i386.texi: Document PadLock RNG2.
	* testsuite/gas/i386/i386.exp: Add PadLock RNG2 test.
	* testsuite/gas/i386/padlock_rng2.d: Ditto.
	* testsuite/gas/i386/padlock_rng2.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c: Add PadLockRNG2.
	* i386-gen.c: Ditto
	* i386-opc.h (CpuPadLockRNG2): New.
	* i386-opc.tbl: Add Zhaoxin PadLock RNG2 instruction.
	* i386-tbl.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-init.h: Ditto.

---
 gas/NEWS                              |  2 ++
 gas/config/tc-i386.c                  |  7 +++++--
 gas/doc/c-i386.texi                   |  5 +++--
 gas/testsuite/gas/i386/i386.exp       |  1 +
 gas/testsuite/gas/i386/padlockrng2.d | 11 +++++++++++
 gas/testsuite/gas/i386/padlockrng2.s |  7 +++++++
 opcodes/i386-dis.c                    |  1 +
 opcodes/i386-gen.c                    |  3 +++
 opcodes/i386-opc.h                    |  5 ++++-
 opcodes/i386-opc.tbl                  |  5 ++++-
 10 files changed, 41 insertions(+), 6 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/padlockrng2.d
 create mode 100644 gas/testsuite/gas/i386/padlockrng2.s

diff --git a/gas/NEWS b/gas/NEWS
index 2b31fdb1515..be4afb65fa3 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Add support for the x86 Zhaoxin PadLock RNG2 instruction.
+
 * Add support for the x86 Intel AVX10.2 instructions.
 
 * Add support for the x86 Intel SM4 AVX10.2 instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index e659d6841cb..21ea8588d9b 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1224,6 +1224,7 @@ static const arch_entry cpu_arch[] =
   VECARCH (avx10.2, AVX10_2, ANY_AVX10_2, set),
   SUBARCH (gmi, GMI, GMI, false),
   SUBARCH (msr_imm, MSR_IMM, MSR_IMM, false),
+  SUBARCH (padlockrng2, PADLOCKRNG2, PADLOCKRNG2, false),
 };
 
 #undef SUBARCH
@@ -12024,11 +12025,13 @@ static int
 add_branch_prefix_frag_p (const struct last_insn *last_insn)
 {
   /* NB: Don't work with COND_JUMP86 without i386.  Don't add prefix
-     to PadLock instructions since they include prefixes in opcode.  */
+     to PadLock instructions and PadLock RNG2 instruction since they include prefixes
+     in opcode. */
   if (!align_branch_power
       || !align_branch_prefix_size
       || now_seg == absolute_section
       || is_cpu (&i.tm, CpuPadLock)
+      || is_cpu (&i.tm, CpuPadLockRNG2)
       || !cpu_arch_flags.bitfield.cpui386)
     return 0;
 
@@ -12403,7 +12406,7 @@ output_insn (const struct last_insn *last_insn)
 	      add_prefix (0xf2);
 	      break;
 	    case PREFIX_0XF3:
-	      if (!is_cpu (&i.tm, CpuPadLock)
+	      if ((!is_cpu (&i.tm, CpuPadLock) && !is_cpu (&i.tm, CpuPadLockRNG2))
 		  || (i.prefix[REP_PREFIX] != 0xf3))
 		add_prefix (0xf3);
 	      break;
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 8832af8a631..6a86e7ca09d 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -278,7 +278,8 @@ accept various extension mnemonics.  For example,
 @code{invlpgb},
 @code{tlbsync},
 @code{svme},
-@code{gmi} and
+@code{gmi},
+@code{padlockrng2} and
 @code{padlock}.
 Note that these extension mnemonics can be prefixed with @code{no} to revoke
 the respective (and any dependent) functionality.  Note further that the
@@ -1710,7 +1711,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
 @item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb}
-@item @samp{.tlbsync} @tab @samp{.apx_f} @tab @samp{.gmi}
+@item @samp{.tlbsync} @tab @samp{.apx_f} @tab @samp{.gmi} @tab @samp{.padlockrng2}
 
 @end multitable
 
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 650729d8b5b..2ba0def9547 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -115,6 +115,7 @@ if [gas_32_check] then {
     run_dump_test "unary"
     run_dump_test "padlock"
     run_dump_test "gmi"
+    run_dump_test "padlockrng2"
     run_dump_test "crx"
     run_list_test "cr-err" ""
     run_dump_test "cdr"
diff --git a/gas/testsuite/gas/i386/padlockrng2.d b/gas/testsuite/gas/i386/padlockrng2.d
new file mode 100644
index 00000000000..14187228a4a
--- /dev/null
+++ b/gas/testsuite/gas/i386/padlockrng2.d
@@ -0,0 +1,11 @@
+#objdump: -dw
+#name: Zhaoxin PadLock RNG2
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+   0:[	 ]*f3 0f a7 f8 [	 ]*repz xrng2
+   4:[	 ]*f3 0f a7 f8 [	 ]*repz xrng2
+#pass
diff --git a/gas/testsuite/gas/i386/padlockrng2.s b/gas/testsuite/gas/i386/padlockrng2.s
new file mode 100644
index 00000000000..019bb3b3bfa
--- /dev/null
+++ b/gas/testsuite/gas/i386/padlockrng2.s
@@ -0,0 +1,7 @@
+# Zhaoxin PadLock RNG2 instruction
+
+	.text
+foo:
+	xrng2
+	rep xrng2
+	.p2align 4,0
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 8e71c1bdda8..6f4c74f67ae 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -2947,6 +2947,7 @@ static const struct dis386 reg_table[][8] = {
     { "xcrypt-cfb",	{ { OP_0f07, 0 } }, 0 },
     { "xcrypt-ofb",	{ { OP_0f07, 0 } }, 0 },
     { PREFIX_TABLE (PREFIX_0FA7_REG_6) },
+    { "xrng2",		{ { OP_0f07, 0 } }, 0 },
   },
   /* REG_0FAE */
   {
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index ed47a0cedd2..472fe1e6fa4 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -289,6 +289,8 @@ static const dependency isa_dependencies[] =
     "64" },
   { "APX_F",
     "XSAVE|64" },
+  { "PadLockRNG2",
+    "PadLock" },
 };
 
 /* This array is populated as process_i386_initializers() walks cpu_flags[].  */
@@ -343,6 +345,7 @@ static bitfield cpu_flags[] =
   BITFIELD (3dnowA),
   BITFIELD (PadLock),
   BITFIELD (GMI),
+  BITFIELD (PadLockRNG2),
   BITFIELD (SVME),
   BITFIELD (VMX),
   BITFIELD (SMX),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index cf7aa3dcb30..80eef398442 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -66,8 +66,10 @@ enum i386_cpu
   CpuSSE3,
   /* VIA PadLock required */
   CpuPadLock,
-  /* ZHAOXIN GMI required */
+  /* Zhaoxin GMI required */
   CpuGMI,
+  /* Zhaoxin PadLock RNG2 required */
+  CpuPadLockRNG2,
   /* AMD Secure Virtual Machine Ext-s required */
   CpuSVME,
   /* VMX Instructions required */
@@ -411,6 +413,7 @@ typedef union i386_cpu_flags
       unsigned int cpusse3:1;
       unsigned int cpupadlock:1;
       unsigned int cpugmi:1;
+      unsigned int cpupadlockrng2:1;
       unsigned int cpusvme:1;
       unsigned int cpuvmx:1;
       unsigned int cpusmx:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 59eed7bb08d..b299147b5e1 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2134,11 +2134,14 @@ xcryptofb, 0xf30fa7e8, PadLock, NoSuf|RepPrefixOk, {}
 // Alias for xstore-rng.
 xstore, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {}
 
-// ZHAOXIN GMI instructions
+// Zhaoxin GMI instructions
 sm2, 0xf20fa6c0, GMI, NoSuf, {}
 sm3, 0xf30fa6e8, GMI, NoSuf, {}
 sm4, 0xf30fa7f0, GMI, NoSuf, {}
 
+// Zhaoxin PadLock RNG2 instruction
+xrng2, 0xf30fa7f8, PadLockRNG2, NoSuf|RepPrefixOk, {}
+
 // Multy-precision Add Carry, rdseed instructions.
 <adx:pfx, c:66, o:f3>
 ad<adx>x, 0x<adx:pfx>66, ADX&APX_F, C|Modrm|CheckOperandSize|No_bSuf|No_wSuf|No_sSuf|DstVVVV|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
-- 
2.27.0