* [PATCH]: binutils patch for maxq target.
@ 2004-12-28 14:09 Inderpreet Singh Baweja
2005-01-05 9:48 ` Nick Clifton
0 siblings, 1 reply; 4+ messages in thread
From: Inderpreet Singh Baweja @ 2004-12-28 14:09 UTC (permalink / raw)
To: binutils; +Cc: Naveen Sharma, Noida
[-- Attachment #1: Type: text/plain, Size: 2403 bytes --]
Hi,
I am attaching a patch for the maxq-target with the following changes:
1. Added variants support for the target maxq10 and maxq20.
2. Fixed problem with relative address handling.
3. Testcases fix for the above problem.
I am also including a patch for the config.sub file as I require
This to bring the binutils in sync. With the gcc port for maxq.
This is the third time I am posting this patch.
I have even tried Sending mails with this patch to
config-patches@gnu.org
But have received no reply or even a commit verification
Please commit t <<patch-binutils-27122004>> hese changes.
And can anyone please tell me what needs to be done if I want my name in
the
Maintainers list for the maxq port?
**************************************** Change Log
****************************************************
2004-12-28 Inderpreet Singh <inderpreetb@noida.hcltech.com>
* config.sub: new target maxq added
bfd/
* archures.c: define bfd_mach_maxq10 and bfd_mach_maxq20.
* bfd-in2.h: Likewise.
* coff-maxq.c(coff_maxq20_reloc): check added for undefined
symbol
and relative jump addresses fixed.
(bfd_coff_maxq_swap_table): swap table defined for maxq-coff.
* coffcode.h: added check for machine type differentiation.
* cpu-maxq.c: arch_info_type defined for maxq10 and maxq20.
gas/config
* tc-maxq.c(maxq_end): defined to set machine arch.
(tc_gen_reloc): local variables initialized.
(md_estimate_size_before_reloc): relative jumps fixed.
(md_convert_frag): Same.
(md_apply_fix3): fixed frag handling for pfx0.
(maxq20_immediate): increased temp array size.
(output_disp): relative addresses fixed.
call to write_pfx added.
(output_data): call to write_pfx added.
(md_begin): call to maxq_end() added.
*gas/testsuite/gas/maxq10/call.d: testcases fixed for the
relative addresses.
to be decremented by 1.
*gas/testsuite/gas/maxq10/jump.d: Likewise.
*gas/testsuite/gas/maxq20/call.d: Likewise.
*gas/testsuite/gas/maxq20/jump.d: Likewise.
include/coff/
* maxq.h: Added machine flags F_MAXQ10, F_MAXQ20 and F_MACHMASK
ld/scripttempl/
* maxqcoff.sc: updated default linker script.
opcodes/
* maxq-dis.c(get_group): Replace magic numbers.
(print_insn): warning fixed due to extra argument to fprintf.
Thanks,
Inder.
[-- Attachment #2: patch-binutils-27122004 --]
[-- Type: application/octet-stream, Size: 38918 bytes --]
Index: config.sub
===================================================================
RCS file: /cvs/src/src/config.sub,v
retrieving revision 1.49
diff -c -3 -p -r1.49 config.sub
*** config.sub 16 Nov 2004 01:18:39 -0000 1.49
--- config.sub 27 Dec 2004 08:38:38 -0000
*************** case $basic_machine in
*** 237,243 ****
| h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \
| i370 | i860 | i960 | ia64 \
| ip2k | iq2000 \
! | m32r | m32rle | m68000 | m68k | m88k | mcore \
| mips | mipsbe | mipseb | mipsel | mipsle \
| mips16 \
| mips64 | mips64el \
--- 237,243 ----
| h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \
| i370 | i860 | i960 | ia64 \
| ip2k | iq2000 \
! | m32r | m32rle | m68000 | m68k | m88k | maxq | mcore \
| mips | mipsbe | mipseb | mipsel | mipsle \
| mips16 \
| mips64 | mips64el \
*************** case $basic_machine in
*** 311,317 ****
| m32r-* | m32rle-* \
| m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \
| m88110-* | m88k-* | mcore-* \
! | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \
| mips16-* \
| mips64-* | mips64el-* \
| mips64vr-* | mips64vrel-* \
--- 311,317 ----
| m32r-* | m32rle-* \
| m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \
| m88110-* | m88k-* | mcore-* \
! | maxq-* | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \
| mips16-* \
| mips64-* | mips64el-* \
| mips64vr-* | mips64vrel-* \
*************** case $basic_machine in
*** 646,651 ****
--- 646,654 ----
m88k-omron*)
basic_machine=m88k-omron
;;
+ maxq)
+ basic_machine=maxq
+ ;;
magnum | m3230)
basic_machine=mips-mips
os=-sysv
Index: bfd/bfd-in2.h
===================================================================
RCS file: /cvs/src/src/bfd/bfd-in2.h,v
retrieving revision 1.311
diff -c -3 -p -r1.311 bfd-in2.h
*** bfd/bfd-in2.h 22 Dec 2004 14:25:42 -0000 1.311
--- bfd/bfd-in2.h 27 Dec 2004 08:38:39 -0000
*************** enum bfd_architecture
*** 1807,1812 ****
--- 1807,1814 ----
bfd_arch_xtensa, /* Tensilica's Xtensa cores. */
#define bfd_mach_xtensa 1
bfd_arch_maxq, /* Dallas MAXQ 10/20 */
+ #define bfd_mach_maxq10 10
+ #define bfd_mach_maxq20 20
bfd_arch_last
};
Index: bfd/coff-maxq.c
===================================================================
RCS file: /cvs/src/src/bfd/coff-maxq.c,v
retrieving revision 1.1
diff -c -3 -p -r1.1 coff-maxq.c
*** bfd/coff-maxq.c 8 Nov 2004 13:17:36 -0000 1.1
--- bfd/coff-maxq.c 27 Dec 2004 08:38:39 -0000
***************
*** 26,31 ****
--- 26,32 ----
#include "sysdep.h"
#include "libbfd.h"
#include "coff/maxq.h"
+ #include "coff/external.h"
#include "coff/internal.h"
#include "libcoff.h"
#include "libiberty.h"
*************** coff_maxq20_reloc (bfd * abfd,
*** 79,85 ****
asymbol * symbol_in,
void * data,
asection * input_section ATTRIBUTE_UNUSED,
! bfd * output_bfd ATTRIBUTE_UNUSED,
char ** error_message ATTRIBUTE_UNUSED)
{
reloc_howto_type *howto = NULL;
--- 80,86 ----
asymbol * symbol_in,
void * data,
asection * input_section ATTRIBUTE_UNUSED,
! bfd * output_bfd ,
char ** error_message ATTRIBUTE_UNUSED)
{
reloc_howto_type *howto = NULL;
*************** coff_maxq20_reloc (bfd * abfd,
*** 92,98 ****
/* If this is an undefined symbol, return error. */
if (symbol_in->section == &bfd_und_section
&& (symbol_in->flags & BSF_WEAK) == 0)
! return bfd_reloc_continue;
if (data && reloc_entry)
{
--- 93,99 ----
/* If this is an undefined symbol, return error. */
if (symbol_in->section == &bfd_und_section
&& (symbol_in->flags & BSF_WEAK) == 0)
! return output_bfd ? bfd_reloc_continue:bfd_reloc_undefined;
if (data && reloc_entry)
{
*************** coff_maxq20_reloc (bfd * abfd,
*** 121,127 ****
else if (addend < 0)
call_addr = call_addr + addend;
! diff = ((call_addr << 1) - (reloc_entry->address << 1));
if (!IS_SJUMP_RANGE (diff))
{
--- 122,128 ----
else if (addend < 0)
call_addr = call_addr + addend;
! diff = (((call_addr << 1) - (reloc_entry->address << 1)) - 1);
if (!IS_SJUMP_RANGE (diff))
{
*************** maxq_reloc_type_lookup (bfd * abfd ATTRI
*** 436,448 ****
return NULL;
}
#define coff_bfd_reloc_type_lookup maxq_reloc_type_lookup
/* Perform any necessary magic to the addend in a reloc entry. */
#define CALC_ADDEND(abfd, symbol, ext_reloc, cache_ptr) \
cache_ptr->addend = ext_reloc.r_offset;
- #include "coffcode.h"
#ifndef TARGET_UNDERSCORE
#define TARGET_UNDERSCORE 1
--- 437,449 ----
return NULL;
}
+
#define coff_bfd_reloc_type_lookup maxq_reloc_type_lookup
/* Perform any necessary magic to the addend in a reloc entry. */
#define CALC_ADDEND(abfd, symbol, ext_reloc, cache_ptr) \
cache_ptr->addend = ext_reloc.r_offset;
#ifndef TARGET_UNDERSCORE
#define TARGET_UNDERSCORE 1
*************** maxq_reloc_type_lookup (bfd * abfd ATTRI
*** 452,458 ****
#define EXTRA_S_FLAGS 0
#endif
/* Forward declaration for use initialising alternative_target field. */
CREATE_LITTLE_COFF_TARGET_VEC (maxqcoff_vec, "coff-maxq", 0, EXTRA_S_FLAGS,
! TARGET_UNDERSCORE, NULL, COFF_SWAP_TABLE);
--- 453,507 ----
#define EXTRA_S_FLAGS 0
#endif
+
+
+ #include "coffcode.h"
+
+
+ /* This is copied from bfd_coff_std_swap_table so that we can change
+ the default section alignment power. */
+ static const bfd_coff_backend_data bfd_coff_maxq_swap_table =
+ {
+ coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in,
+ coff_swap_aux_out, coff_swap_sym_out,
+ coff_swap_lineno_out, coff_swap_reloc_out,
+ coff_swap_filehdr_out, coff_swap_aouthdr_out,
+ coff_swap_scnhdr_out,
+ FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN,
+ #ifdef COFF_LONG_FILENAMES
+ TRUE,
+ #else
+ FALSE,
+ #endif
+ #ifdef COFF_LONG_SECTION_NAMES
+ TRUE,
+ #else
+ FALSE,
+ #endif
+ 0,
+ #ifdef COFF_FORCE_SYMBOLS_IN_STRINGS
+ TRUE,
+ #else
+ FALSE,
+ #endif
+ #ifdef COFF_DEBUG_STRING_WIDE_PREFIX
+ 4,
+ #else
+ 2,
+ #endif
+ coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in,
+ coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook,
+ coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
+ coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook,
+ coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate,
+ coff_classify_symbol, coff_compute_section_file_positions,
+ coff_start_final_link, coff_relocate_section, coff_rtype_to_howto,
+ coff_adjust_symndx, coff_link_add_one_symbol,
+ coff_link_output_has_begun, coff_final_link_postscript
+ };
+
+
/* Forward declaration for use initialising alternative_target field. */
CREATE_LITTLE_COFF_TARGET_VEC (maxqcoff_vec, "coff-maxq", 0, EXTRA_S_FLAGS,
! TARGET_UNDERSCORE, NULL, &bfd_coff_maxq_swap_table);
Index: bfd/coffcode.h
===================================================================
RCS file: /cvs/src/src/bfd/coffcode.h,v
retrieving revision 1.114
diff -c -3 -p -r1.114 coffcode.h
*** bfd/coffcode.h 8 Nov 2004 13:17:32 -0000 1.114
--- bfd/coffcode.h 27 Dec 2004 08:38:40 -0000
*************** coff_set_arch_mach_hook (abfd, filehdr)
*** 1987,1996 ****
break;
#endif
#ifdef MAXQ20MAGIC
! case MAXQ20MAGIC:
arch = bfd_arch_maxq;
! machine = 0;
! break;
#endif
#ifdef MC88MAGIC
case MC88MAGIC:
--- 1987,2003 ----
break;
#endif
#ifdef MAXQ20MAGIC
! case MAXQ20MAGIC:
arch = bfd_arch_maxq;
! switch (internal_f->f_flags & F_MACHMASK)
! {
! case F_MAXQ10:
! machine = bfd_mach_maxq10;
! break;
! case F_MAXQ20:
! machine = bfd_mach_maxq20;
! break;
! default: return FALSE; } break;
#endif
#ifdef MC88MAGIC
case MC88MAGIC:
*************** coff_set_flags (abfd, magicp, flagsp)
*** 2926,2935 ****
#endif
#ifdef MAXQ20MAGIC
! case bfd_arch_maxq:
! *magicp = MAXQ20MAGIC;
! return TRUE;
! break;
#endif
default: /* Unknown architecture. */
--- 2933,2953 ----
#endif
#ifdef MAXQ20MAGIC
! case bfd_arch_maxq:
! *magicp = MAXQ20MAGIC;
! switch(bfd_get_mach (abfd))
! {
! case bfd_mach_maxq10:
! *flagsp = F_MAXQ10;
! break;
! case bfd_mach_maxq20:
! *flagsp=F_MAXQ20;
! break;
! default:
! return FALSE;
! }
! return TRUE;
! break;
#endif
default: /* Unknown architecture. */
Index: bfd/cpu-maxq.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-maxq.c,v
retrieving revision 1.1
diff -c -3 -p -r1.1 cpu-maxq.c
*** bfd/cpu-maxq.c 8 Nov 2004 13:17:36 -0000 1.1
--- bfd/cpu-maxq.c 27 Dec 2004 08:38:40 -0000
***************
*** 24,29 ****
--- 24,47 ----
#include "sysdep.h"
#include "libbfd.h"
+
+ /* This routine is provided two arch_infos and returns whether
+ they'd be compatible */
+
+ static const bfd_arch_info_type *
+ compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
+ {
+ if (a->arch != b->arch || a->mach != b->mach)
+ return NULL;
+ return a;
+ }
+
+ static const bfd_arch_info_type arch_info_struct[] =
+ {
+ { 16, 16, 8, bfd_arch_maxq, bfd_mach_maxq10, "maxq", "maxq10", 0, TRUE,
+ bfd_default_compatible, bfd_default_scan, NULL }
+ };
+
/* MAXQ Archtecture info. */
const bfd_arch_info_type bfd_maxq_arch =
{
*************** const bfd_arch_info_type bfd_maxq_arch =
*** 31,42 ****
16, /* 16 bits in an address */
8, /* 16 bits in a byte */
bfd_arch_maxq, /* enum bfd_archtecture arch */
! 0, /* only 1 machine */
"maxq", /* arch_name */
! "maxq", /* printable name */
0, /* section align power */
TRUE, /* the_default: if this is the machine */
bfd_default_compatible, /* bfd_arch_info */
bfd_default_scan,
! NULL
};
--- 49,60 ----
16, /* 16 bits in an address */
8, /* 16 bits in a byte */
bfd_arch_maxq, /* enum bfd_archtecture arch */
! bfd_mach_maxq20, /* only 1 machine */
"maxq", /* arch_name */
! "maxq20", /* printable name */
0, /* section align power */
TRUE, /* the_default: if this is the machine */
bfd_default_compatible, /* bfd_arch_info */
bfd_default_scan,
! &arch_info_struct[0]
};
Index: gas/config/tc-maxq.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-maxq.c,v
retrieving revision 1.1
diff -c -3 -p -r1.1 tc-maxq.c
*** gas/config/tc-maxq.c 8 Nov 2004 13:17:22 -0000 1.1
--- gas/config/tc-maxq.c 27 Dec 2004 08:38:41 -0000
***************
*** 4,11 ****
Contributed by HCL Technologies Pvt. Ltd.
! Author: Vineet Sharma(vineets@noida.hcltech.com) Inderpreet
! S.(inderpreetb@noida.hcltech.com)
This file is part of GAS.
--- 4,11 ----
Contributed by HCL Technologies Pvt. Ltd.
! Author: Vineet Sharma(vineets@noida.hcltech.com)
! Inderpreet S.(inderpreetb@noida.hcltech.com)
This file is part of GAS.
*************** unsigned int max_version = 20;
*** 74,79 ****
--- 74,83 ----
const char *default_arch = DEFAULT_ARCH;
+ /* Function Declarations. */
+ static void write_pfx (char *);
+
+
/* Type of the operand: Register,Immediate,Memory access,flag or bit. */
union _maxq20_op
*************** maxq20_mach (void)
*** 233,238 ****
--- 237,255 ----
return 1;
}
+ void
+ maxq_end()
+ {
+ if(max_version==10)
+ {
+ bfd_set_arch_mach (stdoutput, bfd_arch_maxq,bfd_mach_maxq10);
+ }
+ else
+ {
+ bfd_set_arch_mach (stdoutput, bfd_arch_maxq,bfd_mach_maxq20);
+ }
+
+ }
arelent *
tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
{
*************** tc_gen_reloc (asection *section ATTRIBUT
*** 307,312 ****
--- 324,333 ----
int
md_estimate_size_before_relax (fragS *fragP, segT segment)
{
+ unsigned long instr=0;
+ unsigned long call_addr=0;
+ long diff=0;
+
/* Check whether the symbol has been resolved or not.
Otherwise we will have to generate a fixup. */
if ((S_GET_SEGMENT (fragP->fr_symbol) != segment)
*************** md_estimate_size_before_relax (fragS *fr
*** 355,363 ****
if (fragP->fr_subtype == NO_PREFIX || fragP->fr_subtype == LONG_PREFIX)
{
- unsigned long instr;
- unsigned long call_addr;
- long diff;
fragS *f;
diff = diff ^ diff;;
call_addr = call_addr ^ call_addr;
--- 376,381 ----
*************** md_estimate_size_before_relax (fragS *fr
*** 367,375 ****
/* segment_info_type *seginfo = seg_info (segment); */
instr = fragP->fr_address + fragP->fr_fix - 2;
! /* This is the offset if it is a PC relative jump. */
! call_addr = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
! diff = (call_addr - instr);
if (diff >= (-128 * 2) && diff <= (2 * 127))
{
--- 385,394 ----
/* segment_info_type *seginfo = seg_info (segment); */
instr = fragP->fr_address + fragP->fr_fix - 2;
! /* This is the offset if it is a PC relative jump. As the
! PC points to the Next instruction so the difference decremented by 1. */
! call_addr = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset ;
! diff = (call_addr - instr)-1 ;
if (diff >= (-128 * 2) && diff <= (2 * 127))
{
*************** md_convert_frag (object_headers * header
*** 503,509 ****
(fragP->fr_address / MAXQ_OCTETS_PER_BYTE) +
((fragP->fr_fix - 2) / MAXQ_OCTETS_PER_BYTE);
! displacement_from_opcode_start = (target_address - opcode_address);
if ((displacement_from_opcode_start >= -128
&& displacement_from_opcode_start <= 127)
--- 522,530 ----
(fragP->fr_address / MAXQ_OCTETS_PER_BYTE) +
((fragP->fr_fix - 2) / MAXQ_OCTETS_PER_BYTE);
! /* This is to produce relative jumps as PC points to the
! next IP Address. */
! displacement_from_opcode_start = ((target_address - opcode_address) - 1);
if ((displacement_from_opcode_start >= -128
&& displacement_from_opcode_start <= 127)
*************** maxq_number_to_chars (char *buf, valueT
*** 585,590 ****
--- 606,612 ----
void
md_apply_fix3 (fixS *fixP, valueT *valT, segT seg ATTRIBUTE_UNUSED)
{
+ char pfx_v=0;
char *p = fixP->fx_frag->fr_literal + fixP->fx_where;
char *frag_to_fix_at =
fixP->fx_frag->fr_literal + fixP->fx_frag->fr_fix - 2;
*************** md_apply_fix3 (fixS *fixP, valueT *valT,
*** 609,616 ****
if ((fixP->fx_frag->fr_subtype == ABSOLUTE_ADDR_FOR_DATA)
|| (fixP->fx_frag->fr_subtype == LONG_PREFIX))
{
! *(frag_to_fix_at + 1) = *(p + 1);
! maxq_number_to_chars (p + 1, PFX0, 1);
}
#ifdef BFD_ASSEMBLER
--- 631,642 ----
if ((fixP->fx_frag->fr_subtype == ABSOLUTE_ADDR_FOR_DATA)
|| (fixP->fx_frag->fr_subtype == LONG_PREFIX))
{
! pfx_v=*(frag_to_fix_at+1);
! if(pfx_v==0)
! pfx_v=PFX0;
! *(frag_to_fix_at + 1) = *(p + 1);
! maxq_number_to_chars (p + 1, pfx_v, 1);
!
}
#ifdef BFD_ASSEMBLER
*************** maxq20_immediate (char *imm_start)
*** 1178,1184 ****
int val = 0, val_pfx = 0;
char sign_val = 0;
int k = 0, j;
! int temp[4] = { 0 };
imm_start++;
--- 1204,1210 ----
int val = 0, val_pfx = 0;
char sign_val = 0;
int k = 0, j;
! int temp[10] = { 0 };
imm_start++;
*************** output_disp (fragS *insn_start_frag, off
*** 2757,2763 ****
((((expressionS *) symbol_get_value_expression (sym))->
X_add_number) - insn_start_off);
! diff = diff / MAXQ_OCTETS_PER_BYTE;
if (diff >= -128 && diff <= 127)
{
--- 2783,2790 ----
((((expressionS *) symbol_get_value_expression (sym))->
X_add_number) - insn_start_off);
! /* As the PC points to the next instruction, we decrement it by 1. */
! diff = (diff / MAXQ_OCTETS_PER_BYTE) - 1;
if (diff >= -128 && diff <= 127)
{
*************** output_disp (fragS *insn_start_frag, off
*** 2785,2790 ****
--- 2812,2819 ----
off = 0;
}
+ write_pfx(p+2);
+
/* Vineet : This has been added for md_estimate_size_before_relax to
estimate the correct size. */
if (subtype != SHORT_PREFIX)
*************** output_data (fragS *insn_start_frag, off
*** 2802,2810 ****
relax_substateT subtype;
symbolS *sym;
offsetT off;
- int diff;
- diff = 0;
off = 0;
insn_start_frag = frag_now;
insn_start_off = frag_now_fix ();
--- 2831,2837 ----
*************** output_data (fragS *insn_start_frag, off
*** 2828,2836 ****
--- 2855,2879 ----
need to convert it from expression to symbol. */
off = 0;
+ write_pfx(p+2);
+
frag_var (rs_machine_dependent, 2, i.reloc[this_operand], subtype, sym, off, p);
}
+ /* Write the Correct Value of PFX */
+ void write_pfx(ptr)
+ char* ptr;
+ {
+ char* p=ptr;
+
+ /* Check whether the prefix instruction has to be written */
+ if (strcmp (PFX_INSN, ""))
+ {
+ *p++ = PFX_INSN[1];
+ *p = PFX_INSN[0];
+ }
+ }
+
static void
output_insn (void)
{
*************** md_begin (void)
*** 3116,3121 ****
--- 3159,3166 ----
for (p = operand_special_chars; *p != '\0'; p++)
operand_chars[(unsigned char) *p] = (unsigned char) *p;
+
+ maxq_end();
}
/* md_assemble - Parse Instr - Seprate menmonics and operands - lookup the
Index: gas/testsuite/gas/maxq10/call.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/maxq10/call.d,v
retrieving revision 1.2
diff -c -3 -p -r1.2 call.d
*** gas/testsuite/gas/maxq10/call.d 18 Nov 2004 16:20:11 -0000 1.2
--- gas/testsuite/gas/maxq10/call.d 27 Dec 2004 08:38:42 -0000
***************
*** 5,11 ****
Disassembly of section .text:
0+000 <foo>:
! 0: 03 3d [ ]*CALL #03h
2: 04 0b [ ]*MOVE PFX\[0\], #04h
4: 28 3d [ ]*CALL #28h
0+6 <SmallCall>:
--- 5,11 ----
Disassembly of section .text:
0+000 <foo>:
! 0: 02 3d [ ]*CALL #02h
2: 04 0b [ ]*MOVE PFX\[0\], #04h
4: 28 3d [ ]*CALL #28h
0+6 <SmallCall>:
*************** Disassembly of section .text:
*** 21,31 ****
18: 8d cc [ ]*RETI S
1a: 10 7d [ ]*MOVE LC\[1\], #10h
0+1c <LoopTop>:
! 1c: 00 3d [ ]*CALL #00h
! 1e: ff 5d [ ]*DJNZ LC\[1\], #ffh
20: 10 7d [ ]*MOVE LC\[1\], #10h
0+22 <LoopTop1>:
! 22: 00 3d [ ]*CALL #00h
...
424: 00 0b [ ]*MOVE PFX\[0\], #00h
426: 1c 5d [ ]*DJNZ LC\[1\], #1ch
--- 21,31 ----
18: 8d cc [ ]*RETI S
1a: 10 7d [ ]*MOVE LC\[1\], #10h
0+1c <LoopTop>:
! 1c: ff 3d [ ]*CALL #ffh
! 1e: fe 5d [ ]*DJNZ LC\[1\], #feh
20: 10 7d [ ]*MOVE LC\[1\], #10h
0+22 <LoopTop1>:
! 22: ff 3d [ ]*CALL #ffh
...
424: 00 0b [ ]*MOVE PFX\[0\], #00h
426: 1c 5d [ ]*DJNZ LC\[1\], #1ch
Index: gas/testsuite/gas/maxq10/jump.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/maxq10/jump.d,v
retrieving revision 1.1
diff -c -3 -p -r1.1 jump.d
*** gas/testsuite/gas/maxq10/jump.d 8 Nov 2004 13:17:42 -0000 1.1
--- gas/testsuite/gas/maxq10/jump.d 27 Dec 2004 08:38:42 -0000
***************
*** 5,49 ****
Disassembly of section .text:
0+000 <LableStart>:
! 0: 00 0c [ ]*JUMP #00h
! 2: ff 2c [ ]*JUMP C , #ffh
4: 09 ac [ ]*JUMP C , A\[0\]
6: 19 ac [ ]*JUMP C , A\[1\]
! 8: fc 6c [ ]*JUMP NC , #fch
a: 09 ec [ ]*JUMP NC , A\[0\]
c: 19 ec [ ]*JUMP NC , A\[1\]
! e: f9 4c [ ]*JUMP S , #f9h
10: 09 cc [ ]*JUMP S , A\[0\]
12: 19 cc [ ]*JUMP S , A\[1\]
! 14: f6 1c [ ]*JUMP Z , #f6h
16: 09 9c [ ]*JUMP Z , A\[0\]
18: 19 9c [ ]*JUMP Z , A\[1\]
! 1a: f3 5c [ ]*JUMP NZ , #f3h
1c: 09 dc [ ]*JUMP NZ , A\[0\]
1e: 19 dc [ ]*JUMP NZ , A\[1\]
! 20: f0 3c [ ]*JUMP E , #f0h
! 22: ef 7c [ ]*JUMP NE , #efh
! 24: 01 7c [ ]*JUMP NE , #01h
0+026 <Lable1>:
! 26: 00 0c [ ]*JUMP #00h
! 28: ff 2c [ ]*JUMP C , #ffh
2a: 09 ac [ ]*JUMP C , A\[0\]
2c: 19 ac [ ]*JUMP C , A\[1\]
! 2e: fc 6c [ ]*JUMP NC , #fch
30: 09 ec [ ]*JUMP NC , A\[0\]
32: 19 ec [ ]*JUMP NC , A\[1\]
! 34: f9 4c [ ]*JUMP S , #f9h
36: 09 cc [ ]*JUMP S , A\[0\]
38: 19 cc [ ]*JUMP S , A\[1\]
! 3a: f6 1c [ ]*JUMP Z , #f6h
3c: 09 9c [ ]*JUMP Z , A\[0\]
3e: 19 9c [ ]*JUMP Z , A\[1\]
! 40: f3 5c [ ]*JUMP NZ , #f3h
42: 09 dc [ ]*JUMP NZ , A\[0\]
44: 19 dc [ ]*JUMP NZ , A\[1\]
! 46: f0 3c [ ]*JUMP E , #f0h
! 48: ef 7c [ ]*JUMP NE , #efh
4a: 04 0b [ ]*MOVE PFX\[0\], #04h
4c: c6 0c [ ]*JUMP #c6h
4e: 04 0b [ ]*MOVE PFX\[0\], #04h
--- 5,49 ----
Disassembly of section .text:
0+000 <LableStart>:
! 0: ff 0c [ ]*JUMP #ffh
! 2: fe 2c [ ]*JUMP C , #feh
4: 09 ac [ ]*JUMP C , A\[0\]
6: 19 ac [ ]*JUMP C , A\[1\]
! 8: fb 6c [ ]*JUMP NC , #fbh
a: 09 ec [ ]*JUMP NC , A\[0\]
c: 19 ec [ ]*JUMP NC , A\[1\]
! e: f8 4c [ ]*JUMP S , #f8h
10: 09 cc [ ]*JUMP S , A\[0\]
12: 19 cc [ ]*JUMP S , A\[1\]
! 14: f5 1c [ ]*JUMP Z , #f5h
16: 09 9c [ ]*JUMP Z , A\[0\]
18: 19 9c [ ]*JUMP Z , A\[1\]
! 1a: f2 5c [ ]*JUMP NZ , #f2h
1c: 09 dc [ ]*JUMP NZ , A\[0\]
1e: 19 dc [ ]*JUMP NZ , A\[1\]
! 20: ef 3c [ ]*JUMP E , #efh
! 22: ee 7c [ ]*JUMP NE , #eeh
! 24: 00 7c [ ]*JUMP NE , #00h
0+026 <Lable1>:
! 26: ff 0c [ ]*JUMP #ffh
! 28: fe 2c [ ]*JUMP C , #feh
2a: 09 ac [ ]*JUMP C , A\[0\]
2c: 19 ac [ ]*JUMP C , A\[1\]
! 2e: fb 6c [ ]*JUMP NC , #fbh
30: 09 ec [ ]*JUMP NC , A\[0\]
32: 19 ec [ ]*JUMP NC , A\[1\]
! 34: f8 4c [ ]*JUMP S , #f8h
36: 09 cc [ ]*JUMP S , A\[0\]
38: 19 cc [ ]*JUMP S , A\[1\]
! 3a: f5 1c [ ]*JUMP Z , #f5h
3c: 09 9c [ ]*JUMP Z , A\[0\]
3e: 19 9c [ ]*JUMP Z , A\[1\]
! 40: f2 5c [ ]*JUMP NZ , #f2h
42: 09 dc [ ]*JUMP NZ , A\[0\]
44: 19 dc [ ]*JUMP NZ , A\[1\]
! 46: ef 3c [ ]*JUMP E , #efh
! 48: ee 7c [ ]*JUMP NE , #eeh
4a: 04 0b [ ]*MOVE PFX\[0\], #04h
4c: c6 0c [ ]*JUMP #c6h
4e: 04 0b [ ]*MOVE PFX\[0\], #04h
Index: gas/testsuite/gas/maxq20/call.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/maxq20/call.d,v
retrieving revision 1.2
diff -c -3 -p -r1.2 call.d
*** gas/testsuite/gas/maxq20/call.d 18 Nov 2004 16:20:11 -0000 1.2
--- gas/testsuite/gas/maxq20/call.d 27 Dec 2004 08:38:42 -0000
***************
*** 5,11 ****
Disassembly of section .text:
0+000 <foo>:
! 0: 03 3d [ ]*CALL #03h
2: 04 0b [ ]*MOVE PFX\[0\], #04h
4: 28 3d [ ]*CALL #28h
--- 5,11 ----
Disassembly of section .text:
0+000 <foo>:
! 0: 02 3d [ ]*CALL #02h
2: 04 0b [ ]*MOVE PFX\[0\], #04h
4: 28 3d [ ]*CALL #28h
*************** Disassembly of section .text:
*** 23,34 ****
1a: 10 7d [ ]*MOVE LC\[1\], #10h
0+01c <LoopTop>:
! 1c: 00 3d [ ]*CALL #00h
! 1e: ff 5d [ ]*DJNZ LC\[1\], #ffh
20: 10 7d [ ]*MOVE LC\[1\], #10h
0+022 <LoopTop1>:
! 22: 00 3d [ ]*CALL #00h
...
424: 00 0b [ ]*MOVE PFX\[0\], #00h
426: 1c 5d [ ]*DJNZ LC\[1\], #1ch
--- 23,34 ----
1a: 10 7d [ ]*MOVE LC\[1\], #10h
0+01c <LoopTop>:
! 1c: ff 3d [ ]*CALL #ffh
! 1e: fe 5d [ ]*DJNZ LC\[1\], #feh
20: 10 7d [ ]*MOVE LC\[1\], #10h
0+022 <LoopTop1>:
! 22: ff 3d [ ]*CALL #ffh
...
424: 00 0b [ ]*MOVE PFX\[0\], #00h
426: 1c 5d [ ]*DJNZ LC\[1\], #1ch
Index: gas/testsuite/gas/maxq20/jump.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/maxq20/jump.d,v
retrieving revision 1.1
diff -c -3 -p -r1.1 jump.d
*** gas/testsuite/gas/maxq20/jump.d 8 Nov 2004 13:17:43 -0000 1.1
--- gas/testsuite/gas/maxq20/jump.d 27 Dec 2004 08:38:42 -0000
***************
*** 5,49 ****
Disassembly of section .text:
0+000 <LableStart>:
! 0: 00 0c [ ]*JUMP #00h
! 2: ff 2c [ ]*JUMP C , #ffh
4: 09 ac [ ]*JUMP C , A\[0\]
6: 19 ac [ ]*JUMP C , A\[1\]
! 8: fc 6c [ ]*JUMP NC , #fch
a: 09 ec [ ]*JUMP NC , A\[0\]
c: 19 ec [ ]*JUMP NC , A\[1\]
! e: f9 4c [ ]*JUMP S , #f9h
10: 09 cc [ ]*JUMP S , A\[0\]
12: 19 cc [ ]*JUMP S , A\[1\]
! 14: f6 1c [ ]*JUMP Z , #f6h
16: 09 9c [ ]*JUMP Z , A\[0\]
18: 19 9c [ ]*JUMP Z , A\[1\]
! 1a: f3 5c [ ]*JUMP NZ , #f3h
1c: 09 dc [ ]*JUMP NZ , A\[0\]
1e: 19 dc [ ]*JUMP NZ , A\[1\]
! 20: f0 3c [ ]*JUMP E , #f0h
! 22: ef 7c [ ]*JUMP NE , #efh
! 24: 01 7c [ ]*JUMP NE , #01h
0+026 <Lable1>:
! 26: 00 0c [ ]*JUMP #00h
! 28: ff 2c [ ]*JUMP C , #ffh
2a: 09 ac [ ]*JUMP C , A\[0\]
2c: 19 ac [ ]*JUMP C , A\[1\]
! 2e: fc 6c [ ]*JUMP NC , #fch
30: 09 ec [ ]*JUMP NC , A\[0\]
32: 19 ec [ ]*JUMP NC , A\[1\]
! 34: f9 4c [ ]*JUMP S , #f9h
36: 09 cc [ ]*JUMP S , A\[0\]
38: 19 cc [ ]*JUMP S , A\[1\]
! 3a: f6 1c [ ]*JUMP Z , #f6h
3c: 09 9c [ ]*JUMP Z , A\[0\]
3e: 19 9c [ ]*JUMP Z , A\[1\]
! 40: f3 5c [ ]*JUMP NZ , #f3h
42: 09 dc [ ]*JUMP NZ , A\[0\]
44: 19 dc [ ]*JUMP NZ , A\[1\]
! 46: f0 3c [ ]*JUMP E , #f0h
! 48: ef 7c [ ]*JUMP NE , #efh
4a: 04 0b [ ]*MOVE PFX\[0\], #04h
4c: c6 0c [ ]*JUMP #c6h
4e: 04 0b [ ]*MOVE PFX\[0\], #04h
--- 5,49 ----
Disassembly of section .text:
0+000 <LableStart>:
! 0: ff 0c [ ]*JUMP #ffh
! 2: fe 2c [ ]*JUMP C , #feh
4: 09 ac [ ]*JUMP C , A\[0\]
6: 19 ac [ ]*JUMP C , A\[1\]
! 8: fb 6c [ ]*JUMP NC , #fbh
a: 09 ec [ ]*JUMP NC , A\[0\]
c: 19 ec [ ]*JUMP NC , A\[1\]
! e: f8 4c [ ]*JUMP S , #f8h
10: 09 cc [ ]*JUMP S , A\[0\]
12: 19 cc [ ]*JUMP S , A\[1\]
! 14: f5 1c [ ]*JUMP Z , #f5h
16: 09 9c [ ]*JUMP Z , A\[0\]
18: 19 9c [ ]*JUMP Z , A\[1\]
! 1a: f2 5c [ ]*JUMP NZ , #f2h
1c: 09 dc [ ]*JUMP NZ , A\[0\]
1e: 19 dc [ ]*JUMP NZ , A\[1\]
! 20: ef 3c [ ]*JUMP E , #efh
! 22: ee 7c [ ]*JUMP NE , #eeh
! 24: 00 7c [ ]*JUMP NE , #00h
0+026 <Lable1>:
! 26: ff 0c [ ]*JUMP #ffh
! 28: fe 2c [ ]*JUMP C , #feh
2a: 09 ac [ ]*JUMP C , A\[0\]
2c: 19 ac [ ]*JUMP C , A\[1\]
! 2e: fb 6c [ ]*JUMP NC , #fbh
30: 09 ec [ ]*JUMP NC , A\[0\]
32: 19 ec [ ]*JUMP NC , A\[1\]
! 34: f8 4c [ ]*JUMP S , #f8h
36: 09 cc [ ]*JUMP S , A\[0\]
38: 19 cc [ ]*JUMP S , A\[1\]
! 3a: f5 1c [ ]*JUMP Z , #f5h
3c: 09 9c [ ]*JUMP Z , A\[0\]
3e: 19 9c [ ]*JUMP Z , A\[1\]
! 40: f2 5c [ ]*JUMP NZ , #f2h
42: 09 dc [ ]*JUMP NZ , A\[0\]
44: 19 dc [ ]*JUMP NZ , A\[1\]
! 46: ef 3c [ ]*JUMP E , #efh
! 48: ee 7c [ ]*JUMP NE , #eeh
4a: 04 0b [ ]*MOVE PFX\[0\], #04h
4c: c6 0c [ ]*JUMP #c6h
4e: 04 0b [ ]*MOVE PFX\[0\], #04h
Index: include/coff/maxq.h
===================================================================
RCS file: /cvs/src/src/include/coff/maxq.h,v
retrieving revision 1.1
diff -c -3 -p -r1.1 maxq.h
*** include/coff/maxq.h 8 Nov 2004 13:17:39 -0000 1.1
--- include/coff/maxq.h 27 Dec 2004 08:38:43 -0000
***************
*** 25,38 ****
/* Bits for f_flags: F_RELFLG relocation info stripped from file F_EXEC file
is executable (no unresolved external references) F_LNNO line numbers
! stripped from file F_LSYMS local symbols stripped from file F_AR32WR file
! has byte ordering of an AR32WR machine (e.g. vax). */
#define F_RELFLG (0x0001)
#define F_EXEC (0x0002)
#define F_LNNO (0x0004)
#define F_LSYMS (0x0008)
/* Magic numbers for maxq. */
#define MAXQ20MAGIC 0xa0
#define MAXQ20BADMAG(x) (((x).f_magic != MAXQ20MAGIC))
--- 25,43 ----
/* Bits for f_flags: F_RELFLG relocation info stripped from file F_EXEC file
is executable (no unresolved external references) F_LNNO line numbers
! stripped from file F_LSYMS local symbols stripped from file. */
#define F_RELFLG (0x0001)
#define F_EXEC (0x0002)
#define F_LNNO (0x0004)
#define F_LSYMS (0x0008)
+ /* Variant Specific Flags for MAXQ10 and MAXQ20. */
+ #define F_MAXQ10 (0x0030)
+ #define F_MAXQ20 (0x0040)
+
+ #define F_MACHMASK (0x00F0)
+
/* Magic numbers for maxq. */
#define MAXQ20MAGIC 0xa0
#define MAXQ20BADMAG(x) (((x).f_magic != MAXQ20MAGIC))
Index: ld/scripttempl/maxqcoff.sc
===================================================================
RCS file: /cvs/src/src/ld/scripttempl/maxqcoff.sc,v
retrieving revision 1.1
diff -c -3 -p -r1.1 maxqcoff.sc
*** ld/scripttempl/maxqcoff.sc 8 Nov 2004 13:17:24 -0000 1.1
--- ld/scripttempl/maxqcoff.sc 27 Dec 2004 08:38:44 -0000
*************** cat <<EOF
*** 3,36 ****
OUTPUT_FORMAT("${OUTPUT_FORMAT}")
${LIB_SEARCH_DIRS}
ENTRY(${ENTRY})
- MEMORY
- {
- rom (rx) : ORIGIN = 0, LENGTH = 0x7FFE
- ram (!rx) : org = 0x0A000, l = 0x5FFF
- }
SECTIONS
{
! .text ${RELOCATING+ 0x0000}:
! {
! *(.text)
! } >rom
!
! .data ${RELOCATING}:
{
*(.data)
*(.rodata)
! *(.bss)
! *(COMMON)
! ${RELOCATING+ edata = .};
! }>ram
! /* .bss ${RELOCATING+ SIZEOF(.data) + 0x0000} :
! {
! *(.bss)
! *(COMMON)
}
! */
.stab 0 ${RELOCATING+(NOLOAD)} :
{
[ .stab ]
--- 3,29 ----
OUTPUT_FORMAT("${OUTPUT_FORMAT}")
${LIB_SEARCH_DIRS}
ENTRY(${ENTRY})
SECTIONS
{
! .data ${RELOCATING+0x0000}:
{
*(.data)
*(.rodata)
! }
! .bss ${RELOCATING+SIZEOF(.data)}:
! {
! *(.bss)
! *(COMMON)
! ${RELOCATING+ edata = .};
! }=0x00000000
!
! .text ${RELOCATING+SIZEOF(.bss)+SIZEOF(.data)}:
! {
! *(.text)
}
!
.stab 0 ${RELOCATING+(NOLOAD)} :
{
[ .stab ]
Index: opcodes/maxq-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/maxq-dis.c,v
retrieving revision 1.2
diff -c -3 -p -r1.2 maxq-dis.c
*** opcodes/maxq-dis.c 19 Nov 2004 12:34:13 -0000 1.2
--- opcodes/maxq-dis.c 27 Dec 2004 08:38:46 -0000
*************** typedef struct _group_info group_info;
*** 99,105 ****
#define SIM_ALU_DECODE_IGE_BIT_POS 0x1
/* Number Of Op-code Groups. */
! unsigned char const SIM_ALU_DECODE_OPCODE_GROUPS = 11;
/* Op-code Groups. */
unsigned char const SIM_ALU_DECODE_LOGICAL_XCHG_OP_GROUP = 1;
--- 99,105 ----
#define SIM_ALU_DECODE_IGE_BIT_POS 0x1
/* Number Of Op-code Groups. */
! unsigned char const SIM_ALU_DECODE_OPCODE_GROUPS = 13;
/* Op-code Groups. */
unsigned char const SIM_ALU_DECODE_LOGICAL_XCHG_OP_GROUP = 1;
*************** static unsigned char
*** 354,395 ****
get_group (const unsigned int insn)
{
if (check_move ((insn >> 8), (insn & _DECODE_LOWBYTE)))
! return 8;
if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0A00)
{
/* && condition with sec part added on 26 May for resolving 2 & 3 grp
! conflict. */
if (((insn & _DECODE_LOWNIB_LOWBYTE) == 0x000A)
&& ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
{
if ((insn & _DECODE_HIGHNIB_HIGHBYTE) == 0x8000)
! return 2;
else
! return 3;
}
! return 1;
}
else if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0C00)
{
! if (((insn & _DECODE_LOWBYTE) == 0x000D) && JUMP_CHECK (insn)
! && ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
! return 6;
! else if ((insn & _DECODE_LOWBYTE) == 0x008D)
! return 7;
!
! return 5;
}
else if (((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0D00)
&& (((insn & _DECODE_4TO6_HIGHBYTE) == 0x3000)
|| ((insn & _DECODE_4TO6_HIGHBYTE) == 0x4000)
|| ((insn & _DECODE_4TO6_HIGHBYTE) == 0x5000)
|| ((insn & _DECODE_4TO6_HIGHBYTE) == 0x0000)))
! return 10;
else if ((insn & _DECODE_LOWBYTE) == 0x000D)
! return 11;
else if ((insn & _DECODE_LOWBYTE) == 0x008D)
return 12;
--- 354,397 ----
get_group (const unsigned int insn)
{
if (check_move ((insn >> 8), (insn & _DECODE_LOWBYTE)))
! return SIM_ALU_DECODE_SET_SRC_BIT_GROUP;
if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0A00)
{
/* && condition with sec part added on 26 May for resolving 2 & 3 grp
! conflict. */
if (((insn & _DECODE_LOWNIB_LOWBYTE) == 0x000A)
&& ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
{
if ((insn & _DECODE_HIGHNIB_HIGHBYTE) == 0x8000)
! return SIM_ALU_DECODE_AND_OR_ADD_SUB_OP_GROUP;
else
! return SIM_ALU_DECODE_BIT_OP_GROUP;
}
! return SIM_ALU_DECODE_LOGICAL_XCHG_OP_GROUP;
}
else if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0C00)
{
! if (((insn & _DECODE_LOWBYTE) == 0x000D ) && JUMP_CHECK (insn)
! && ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
! return SIM_ALU_DECODE_RET_OP_GROUP;
!
! else if ((insn & _DECODE_LOWBYTE) == 0x008D &&
! (JUMP_CHECK(insn)) && ((insn&0x8000)==0x8000))
! return SIM_ALU_DECODE_MOVE_SRC_DST_GROUP;
!
! return SIM_ALU_DECODE_JUMP_OP_GROUP;
}
else if (((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0D00)
&& (((insn & _DECODE_4TO6_HIGHBYTE) == 0x3000)
|| ((insn & _DECODE_4TO6_HIGHBYTE) == 0x4000)
|| ((insn & _DECODE_4TO6_HIGHBYTE) == 0x5000)
|| ((insn & _DECODE_4TO6_HIGHBYTE) == 0x0000)))
! return SIM_ALU_DECODE_POP_OP_GROUP;
else if ((insn & _DECODE_LOWBYTE) == 0x000D)
! return SIM_ALU_DECODE_CMP_SRC_OP_GROUP;
else if ((insn & _DECODE_LOWBYTE) == 0x008D)
return 12;
*************** get_group (const unsigned int insn)
*** 398,410 ****
return 13;
else if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0700)
! return 9;
else if (((insn & _DECODE_LOWNIB_LOWBYTE) == 0x0007)
&& ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
! return 4;
! return 8;
}
static void
--- 400,412 ----
return 13;
else if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0700)
! return SIM_ALU_DECODE_DJNZ_CALL_PUSH_OP_GROUP;
else if (((insn & _DECODE_LOWNIB_LOWBYTE) == 0x0007)
&& ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
! return SIM_ALU_DECODE_SET_DEST_BIT_GROUP;
! return SIM_ALU_DECODE_SET_SRC_BIT_GROUP;
}
static void
*************** print_insn (bfd_vma memaddr, struct disa
*** 652,659 ****
grp.bit_no);
}
else
! info->fprintf_func (info->stream, " %s",
! get_reg_name (grp.dst, (type1) 0));
}
/* SRC is ABSENT in the grp. */
--- 654,660 ----
grp.bit_no);
}
else
! info->fprintf_func (info->stream, " %s", get_reg_name (grp.dst, (type1) 0));
}
/* SRC is ABSENT in the grp. */
*************** print_insn (bfd_vma memaddr, struct disa
*** 683,689 ****
grp.bit_no);
if (format == 0)
info->fprintf_func (info->stream, " #%02xh.%d",
! grp.src, grp.bit_no);
}
else
{
--- 684,690 ----
grp.bit_no);
if (format == 0)
info->fprintf_func (info->stream, " #%02xh.%d",
! (grp.src, SRC), grp.bit_no);
}
else
{
*************** print_insn (bfd_vma memaddr, struct disa
*** 693,703 ****
format = grp.fbit;
if (format == 1)
info->fprintf_func (info->stream, " %s",
! get_reg_name (grp.src,
! (type1) 1 /*SRC*/));
if (format == 0)
info->fprintf_func (info->stream, " #%02xh",
! (grp.src));
}
}
--- 694,704 ----
format = grp.fbit;
if (format == 1)
info->fprintf_func (info->stream, " %s",
! get_reg_name (grp.src,
! (type1) 1 /*SRC*/));
if (format == 0)
info->fprintf_func (info->stream, " #%02xh",
! (grp.src));
}
}
*************** print_insn (bfd_vma memaddr, struct disa
*** 706,712 ****
}
info->fprintf_func (info->stream, "Unable to Decode : %02x %02x",
! insn[0], insn[1]);
return 2;
}
--- 707,713 ----
}
info->fprintf_func (info->stream, "Unable to Decode : %02x %02x",
! insn[0], insn[1]);
return 2;
}
*************** print_insn_maxq_little (bfd_vma memaddr,
*** 715,717 ****
--- 716,719 ----
{
return print_insn (memaddr, info, BFD_ENDIAN_LITTLE);
}
+
Index: archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.100
diff -c -3 -p -r1.100 archures.c
*** archures.c 9 Dec 2004 06:08:45 -0000 1.100
--- archures.c 28 Dec 2004 12:35:02 -0000
*************** DESCRIPTION
*** 356,361 ****
--- 356,363 ----
. bfd_arch_xtensa, {* Tensilica's Xtensa cores. *}
.#define bfd_mach_xtensa 1
. bfd_arch_maxq, {* Dallas MAXQ 10/20 *}
+ .#define bfd_mach_maxq10 10
+ .#define bfd_mach_maxq20 20
. bfd_arch_last
. };
*/
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH]: binutils patch for maxq target.
2004-12-28 14:09 [PATCH]: binutils patch for maxq target Inderpreet Singh Baweja
@ 2005-01-05 9:48 ` Nick Clifton
0 siblings, 0 replies; 4+ messages in thread
From: Nick Clifton @ 2005-01-05 9:48 UTC (permalink / raw)
To: Inderpreet Singh Baweja; +Cc: binutils, Naveen Sharma, Noida
Hi Inderpreet,
> I am also including a patch for the config.sub file as I require
> This to bring the binutils in sync. With the gcc port for maxq.
> This is the third time I am posting this patch.
> I have even tried Sending mails with this patch to
> config-patches@gnu.org
> But have received no reply or even a commit verification
Sorry - but we (binutils) cannot accept or commit the patch to the top
level configure files. You will have to keep trying the
config-patches@gnu.org address.
> And can anyone please tell me what needs to be done if I want my name in
> the Maintainers list for the maxq port?
Essentially you need to demonstrate three things:
a) A willingness to take on the responsibility
b) Knowledge of the particular target
c) The programming skills to produce good code that conforms to the
GNU Coding Standard
Thanks for generating this patch. There are several problems with it
however:
*) The patch fixes a problem and adds a new feature. We really
prefer patches to just do one thing - fix one problem, add one new
feature, etc. It makes hunting down problems with patches much easier
if they just do one thing.
*) You added an inclusion of "coff/external.h" to the file
bfd/coff-maxq.c but you did not update the dependency description in
bfd/Makefile.am. Thus if someone modifies coff/external.h at a later
date coff-maxq.o will not (automatically) be rebuilt which could lead to
problems.
*) There are still places where the GNU Coding Standard is not being
followed. In particular you should always leave a single white space
between a control operator and the opening parenthesis of its argument
list. So for example this:
switch(bfd_get_mach (abfd))
should be:
switch (bfd_get_mach (abfd))
One section was particularly bad. The new function maxq_end() in
gas/config/tc-maxq.c was provided as:
+ void
+ maxq_end()
+ {
+ if(max_version==10)
+ {
+ bfd_set_arch_mach (stdoutput, bfd_arch_maxq,bfd_mach_maxq10);
+ }
+ else
+ {
+ bfd_set_arch_mach (stdoutput, bfd_arch_maxq,bfd_mach_maxq20);
+ }
+
+ }
arelent *
This should have been:
+ void
+ maxq_end (void)
+ {
+ if (max_version == 10)
+ bfd_set_arch_mach (stdoutput, bfd_arch_maxq, bfd_mach_maxq10);
+ else
+ bfd_set_arch_mach (stdoutput, bfd_arch_maxq, bfd_mach_maxq20);
+ }
+
arelent *
Note the extra whitespaces helping to separate out the code into various
regions as well as the removal of the redundant curly braces.
*) It adds a static function "compatible" to the file bfd/cpu-maxq.c,
but this function is never used. In addition the field "the_default" of
the new maxq10 bfd_arch_info structure definition is set to TRUE when it
should be FALSE.
*) The patch to include/coff/maxq.h defines new flags for the MAXQ10
and MAXQ20 processors. It seems strange however that the value for
F_MAXQ10 should be set to 0x0030 rather than just a single bit. Is this
deliberate ? If so, there ought to be a comment explaining why.
*) The change to one of the lines in opcodes/maxq-dis.c looks very
strange:
info->fprintf_func (info->stream, " #%02xh.%d",
! grp.src, grp.bit_no);
--- 684,690 ----
info->fprintf_func (info->stream, " #%02xh.%d",
! (grp.src, SRC), grp.bit_no);
What is the purpose of evaluating grp.src only to ignore its value
and instead use the constant SRC ?
I hope that you will consider these comments and produce a revised patch.
Cheers
Nick
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH]: binutils patch for maxq target.
2005-01-06 9:58 Inderpreet Singh Baweja
@ 2005-01-10 16:36 ` Nick Clifton
0 siblings, 0 replies; 4+ messages in thread
From: Nick Clifton @ 2005-01-10 16:36 UTC (permalink / raw)
To: Inderpreet Singh Baweja; +Cc: binutils, Naveen Sharma, Noida
Hi Inderpreet,
> Thanks for reviewing my patch and I do appreciate you for pointing
> Out my mistakes. Thanks for that.
>
> Here I have separated down individual patches this will be the
> first of the series.
>
> This patch will enable the maxq target to
> differentiate between machine types( MAXQ10 and MAXQ20 ).
Thanks - I have applied this patch but I still had to fix up a few problems:
1) You did not supply a ChangeLog entry for the changes to the
include/coff/maxq.h file.
2) You added a function called "compatible" in bfd/cpu-maxq.c that is
not used.
3) The field "the_default" for the maxq10 architecture description in
bfd/cpu-maxq.c was set to true even when in fact it is not the default.
Cheers
Nick
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH]: binutils patch for maxq target.
@ 2005-01-06 9:58 Inderpreet Singh Baweja
2005-01-10 16:36 ` Nick Clifton
0 siblings, 1 reply; 4+ messages in thread
From: Inderpreet Singh Baweja @ 2005-01-06 9:58 UTC (permalink / raw)
To: Nick Clifton; +Cc: binutils, Naveen Sharma, Noida
[-- Attachment #1: Type: text/plain, Size: 852 bytes --]
Hi Nick,
Thanks for reviewing my patch and I do appreciate you for pointing
Out my mistakes. Thanks for that.
Here I have separated down individual patches this will be the
first of the series.
This patch will enable the maxq target to
differentiate between machine types( MAXQ10 and MAXQ20 ).
----------- Change Log ---------------------------------
2004-12-28 Inderpreet Singh <inderpreetb@noida.hcltech.com>
bfd/
* archures.c: define bfd_mach_maxq10 and bfd_mach_maxq20.
* bfd-in2.h: Likewise.
* coffcode.h: Likewise.
* cpu-maxq.c: arch_info_type defined for maxq10 and maxq20.
gas/config
* tc-maxq.c (md_pseudo_table): added new pseudo ops for maxq10
and maxq20.
(maxq_target): added function to set the arch. type.
--------------------------------------------------------------
Thanks,
Inder
[-- Attachment #2: patch-06012005 --]
[-- Type: application/octet-stream, Size: 10179 bytes --]
Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.100
diff -c -3 -p -r1.100 archures.c
*** bfd/archures.c 9 Dec 2004 06:08:45 -0000 1.100
--- bfd/archures.c 6 Jan 2005 09:38:58 -0000
*************** DESCRIPTION
*** 356,361 ****
--- 356,363 ----
. bfd_arch_xtensa, {* Tensilica's Xtensa cores. *}
.#define bfd_mach_xtensa 1
. bfd_arch_maxq, {* Dallas MAXQ 10/20 *}
+ .#define bfd_mach_maxq10 10
+ .#define bfd_mach_maxq20 20
. bfd_arch_last
. };
*/
Index: bfd/bfd-in2.h
===================================================================
RCS file: /cvs/src/src/bfd/bfd-in2.h,v
retrieving revision 1.312
diff -c -3 -p -r1.312 bfd-in2.h
*** bfd/bfd-in2.h 31 Dec 2004 00:43:58 -0000 1.312
--- bfd/bfd-in2.h 6 Jan 2005 09:39:01 -0000
*************** enum bfd_architecture
*** 1807,1812 ****
--- 1807,1814 ----
bfd_arch_xtensa, /* Tensilica's Xtensa cores. */
#define bfd_mach_xtensa 1
bfd_arch_maxq, /* Dallas MAXQ 10/20 */
+ #define bfd_mach_maxq10 10
+ #define bfd_mach_maxq20 20
bfd_arch_last
};
Index: bfd/coffcode.h
===================================================================
RCS file: /cvs/src/src/bfd/coffcode.h,v
retrieving revision 1.114
diff -c -3 -p -r1.114 coffcode.h
*** bfd/coffcode.h 8 Nov 2004 13:17:32 -0000 1.114
--- bfd/coffcode.h 6 Jan 2005 09:39:07 -0000
*************** coff_set_arch_mach_hook (abfd, filehdr)
*** 1987,1995 ****
break;
#endif
#ifdef MAXQ20MAGIC
! case MAXQ20MAGIC:
arch = bfd_arch_maxq;
! machine = 0;
break;
#endif
#ifdef MC88MAGIC
--- 1987,2005 ----
break;
#endif
#ifdef MAXQ20MAGIC
! case MAXQ20MAGIC:
arch = bfd_arch_maxq;
! switch (internal_f->f_flags & F_MACHMASK)
! {
! case F_MAXQ10:
! machine = bfd_mach_maxq10;
! break;
! case F_MAXQ20:
! machine = bfd_mach_maxq20;
! break;
! default:
! return FALSE;
! }
break;
#endif
#ifdef MC88MAGIC
*************** coff_set_flags (abfd, magicp, flagsp)
*** 2926,2933 ****
#endif
#ifdef MAXQ20MAGIC
! case bfd_arch_maxq:
! *magicp = MAXQ20MAGIC;
return TRUE;
break;
#endif
--- 2936,2954 ----
#endif
#ifdef MAXQ20MAGIC
! case bfd_arch_maxq:
! *magicp = MAXQ20MAGIC;
! switch (bfd_get_mach (abfd))
! {
! case bfd_mach_maxq10:
! *flagsp = F_MAXQ10;
! break;
! case bfd_mach_maxq20:
! *flagsp=F_MAXQ20;
! break;
! default:
! return FALSE;
! }
return TRUE;
break;
#endif
Index: bfd/cpu-maxq.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-maxq.c,v
retrieving revision 1.1
diff -c -3 -p -r1.1 cpu-maxq.c
*** bfd/cpu-maxq.c 8 Nov 2004 13:17:36 -0000 1.1
--- bfd/cpu-maxq.c 6 Jan 2005 09:39:08 -0000
***************
*** 24,29 ****
--- 24,47 ----
#include "sysdep.h"
#include "libbfd.h"
+
+ /* This routine is provided two arch_infos and returns whether
+ they'd be compatible */
+
+ static const bfd_arch_info_type *
+ compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
+ {
+ if (a->arch != b->arch || a->mach != b->mach)
+ return NULL;
+ return a;
+ }
+
+ static const bfd_arch_info_type arch_info_struct[] =
+ {
+ { 16, 16, 8, bfd_arch_maxq, bfd_mach_maxq10, "maxq", "maxq10", 0, TRUE,
+ bfd_default_compatible, bfd_default_scan, NULL }
+ };
+
/* MAXQ Archtecture info. */
const bfd_arch_info_type bfd_maxq_arch =
{
*************** const bfd_arch_info_type bfd_maxq_arch =
*** 31,42 ****
16, /* 16 bits in an address */
8, /* 16 bits in a byte */
bfd_arch_maxq, /* enum bfd_archtecture arch */
! 0, /* only 1 machine */
"maxq", /* arch_name */
! "maxq", /* printable name */
0, /* section align power */
TRUE, /* the_default: if this is the machine */
bfd_default_compatible, /* bfd_arch_info */
bfd_default_scan,
! NULL
};
--- 49,60 ----
16, /* 16 bits in an address */
8, /* 16 bits in a byte */
bfd_arch_maxq, /* enum bfd_archtecture arch */
! bfd_mach_maxq20,
"maxq", /* arch_name */
! "maxq20", /* printable name */
0, /* section align power */
TRUE, /* the_default: if this is the machine */
bfd_default_compatible, /* bfd_arch_info */
bfd_default_scan,
! &arch_info_struct[0]
};
Index: gas/config/tc-maxq.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-maxq.c,v
retrieving revision 1.1
diff -c -3 -p -r1.1 tc-maxq.c
*** gas/config/tc-maxq.c 8 Nov 2004 13:17:22 -0000 1.1
--- gas/config/tc-maxq.c 6 Jan 2005 09:39:13 -0000
***************
*** 70,76 ****
#define PFX0 0x0b
/* Set default to MAXQ20. */
! unsigned int max_version = 20;
const char *default_arch = DEFAULT_ARCH;
--- 70,76 ----
#define PFX0 0x0b
/* Set default to MAXQ20. */
! unsigned int max_version = bfd_mach_maxq20;
const char *default_arch = DEFAULT_ARCH;
*************** md_undefined_symbol (char * name ATTRIBU
*** 186,191 ****
--- 186,199 ----
return NULL;
}
+ void
+ maxq_target (target)
+ int target;
+ {
+ max_version = target;
+ bfd_set_arch_mach (stdoutput, bfd_arch_maxq, max_version);
+ }
+
int
md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
{
*************** md_parse_option (int c, char *arg ATTRIB
*** 193,202 ****
switch (c)
{
case MAXQ_10:
! max_version = 10;
break;
case MAXQ_20:
! max_version = 20;
break;
default:
--- 201,210 ----
switch (c)
{
case MAXQ_10:
! max_version = bfd_mach_maxq10;
break;
case MAXQ_20:
! max_version = bfd_mach_maxq20;
break;
default:
*************** const pseudo_typeS md_pseudo_table[] =
*** 717,722 ****
--- 725,732 ----
{
{"int", cons, 2}, /* size of 'int' has been changed to 1 word
(i.e) 16 bits. */
+ {"maxq10", maxq_target, bfd_mach_maxq10},
+ {"maxq20", maxq_target, bfd_mach_maxq20},
{NULL, 0, 0},
};
*************** md_begin (void)
*** 2948,2954 ****
core_optab->end = optab;
#ifdef MAXQ10S
! if (max_version == 10)
{
if (((optab - 1)->arch == MAXQ10) || ((optab - 1)->arch == MAX))
{
--- 2958,2964 ----
core_optab->end = optab;
#ifdef MAXQ10S
! if (max_version == bfd_mach_maxq10 )
{
if (((optab - 1)->arch == MAXQ10) || ((optab - 1)->arch == MAX))
{
*************** md_begin (void)
*** 2957,2963 ****
(PTR) core_optab);
}
}
! else if (max_version == 20)
{
/* MAXQ20 */
if (((optab - 1)->arch == MAXQ20) || ((optab - 1)->arch == MAX))
--- 2967,2973 ----
(PTR) core_optab);
}
}
! else if (max_version == bfd_mach_maxq20)
{
/* MAXQ20 */
if (((optab - 1)->arch == MAXQ20) || ((optab - 1)->arch == MAX))
*************** md_begin (void)
*** 2993,3004 ****
#if MAXQ10S
switch (max_version)
{
! case 10: /* MAXQ10 */
if ((reg_tab->arch == MAXQ10) || (reg_tab->arch == MAX))
hash_err = hash_insert (reg_hash, reg_tab->reg_name, (PTR) reg_tab);
break;
! case 20: /* MAXQ20 */
if ((reg_tab->arch == MAXQ20) || (reg_tab->arch == MAX))
{
#endif
--- 3003,3014 ----
#if MAXQ10S
switch (max_version)
{
! case bfd_mach_maxq10 : /* MAXQ10 */
if ((reg_tab->arch == MAXQ10) || (reg_tab->arch == MAX))
hash_err = hash_insert (reg_hash, reg_tab->reg_name, (PTR) reg_tab);
break;
! case bfd_mach_maxq20: /* MAXQ20 */
if ((reg_tab->arch == MAXQ20) || (reg_tab->arch == MAX))
{
#endif
*************** md_begin (void)
*** 3116,3121 ****
--- 3126,3134 ----
for (p = operand_special_chars; *p != '\0'; p++)
operand_chars[(unsigned char) *p] = (unsigned char) *p;
+
+ /* Set the maxq arch type. */
+ maxq_target (max_version);
}
/* md_assemble - Parse Instr - Seprate menmonics and operands - lookup the
Index: include/coff/maxq.h
===================================================================
RCS file: /cvs/src/src/include/coff/maxq.h,v
retrieving revision 1.1
diff -c -3 -p -r1.1 maxq.h
*** include/coff/maxq.h 8 Nov 2004 13:17:39 -0000 1.1
--- include/coff/maxq.h 6 Jan 2005 09:39:18 -0000
***************
*** 25,38 ****
/* Bits for f_flags: F_RELFLG relocation info stripped from file F_EXEC file
is executable (no unresolved external references) F_LNNO line numbers
! stripped from file F_LSYMS local symbols stripped from file F_AR32WR file
! has byte ordering of an AR32WR machine (e.g. vax). */
#define F_RELFLG (0x0001)
#define F_EXEC (0x0002)
#define F_LNNO (0x0004)
#define F_LSYMS (0x0008)
/* Magic numbers for maxq. */
#define MAXQ20MAGIC 0xa0
#define MAXQ20BADMAG(x) (((x).f_magic != MAXQ20MAGIC))
--- 25,43 ----
/* Bits for f_flags: F_RELFLG relocation info stripped from file F_EXEC file
is executable (no unresolved external references) F_LNNO line numbers
! stripped from file F_LSYMS local symbols stripped from file. */
#define F_RELFLG (0x0001)
#define F_EXEC (0x0002)
#define F_LNNO (0x0004)
#define F_LSYMS (0x0008)
+ /* Variant Specific Flags for MAXQ10 and MAXQ20. */
+ #define F_MAXQ10 (0x0030)
+ #define F_MAXQ20 (0x0040)
+
+ #define F_MACHMASK (0x00F0)
+
/* Magic numbers for maxq. */
#define MAXQ20MAGIC 0xa0
#define MAXQ20BADMAG(x) (((x).f_magic != MAXQ20MAGIC))
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2005-01-10 16:36 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2004-12-28 14:09 [PATCH]: binutils patch for maxq target Inderpreet Singh Baweja
2005-01-05 9:48 ` Nick Clifton
2005-01-06 9:58 Inderpreet Singh Baweja
2005-01-10 16:36 ` Nick Clifton
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