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From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Cc: "H.J. Lu" <hjl.tools@gmail.com>
Subject: [PATCH] x86: simplify and slightly correct XCHG vs NOP checking
Date: Thu, 1 Dec 2022 10:11:50 +0100	[thread overview]
Message-ID: <35539292-53a8-292d-2f5d-f65ad02a36bb@suse.com> (raw)

For one, because of CheckRegSize, there's no need to check the size of
both (register) operands. And then in process_suffix() check opcode
space rather than the (potentially ambiguous) extension opcode.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6686,8 +6686,7 @@ match_template (char mnem_suffix)
 	      && t->opcode_modifier.opcodespace == SPACE_BASE
 	      && i.types[0].bitfield.instance == Accum
 	      && i.types[0].bitfield.dword
-	      && i.types[1].bitfield.instance == Accum
-	      && i.types[1].bitfield.dword)
+	      && i.types[1].bitfield.instance == Accum)
 	    continue;
 	  /* xrelease mov %eax, <disp> is another special case. It must not
 	     match the accumulator-only encoding of mov.  */
@@ -7408,11 +7407,10 @@ process_suffix (void)
 	     need rex64. */
 	  && ! (i.operands == 2
 		&& i.tm.base_opcode == 0x90
-		&& i.tm.extension_opcode == None
+		&& i.tm.opcode_modifier.opcodespace == SPACE_BASE
 		&& i.types[0].bitfield.instance == Accum
 		&& i.types[0].bitfield.qword
-		&& i.types[1].bitfield.instance == Accum
-		&& i.types[1].bitfield.qword))
+		&& i.types[1].bitfield.instance == Accum))
 	i.rex |= REX_W;
 
       break;

             reply	other threads:[~2022-12-01  9:12 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-01  9:11 Jan Beulich [this message]
2022-12-01 16:43 ` H.J. Lu

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