From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx2.suse.de (mx2.suse.de [195.135.220.15]) by sourceware.org (Postfix) with ESMTPS id 903323858024 for ; Fri, 26 Mar 2021 10:50:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 903323858024 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id ACB68AB8A; Fri, 26 Mar 2021 10:50:54 +0000 (UTC) Subject: [PATCH 2/6] x86: shrink some struct insn_template fields To: Binutils References: <287ad145-1fe3-2477-327a-30e8d45a4be7@suse.com> From: Jan Beulich Message-ID: <379a1b1a-f48f-3070-ee76-1b460450d518@suse.com> Date: Fri, 26 Mar 2021 11:50:54 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.9.0 MIME-Version: 1.0 In-Reply-To: <287ad145-1fe3-2477-327a-30e8d45a4be7@suse.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3033.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 26 Mar 2021 10:50:56 -0000 Now that all base opcodes are only at most 2 bytes in size, shrink its template field to just as much. By also shrinking extension_opcode and operands to just what they really need, we can free up an entire 32-bit slot (plus 4 left bits past the bitfields themselves). At present this alters sizeof(struct insn_template) only for 32-bit builds. In 64-bit builds it instead leaves a padding hole that will allow to buffer future growth of other fields (opcode_modifier, cpu_flags, operand_types[]). opcodes/ 2021-03-XX Jan Beulich * i386-opc.h (struct insn_template): Shrink base_opcode to 16 bits. Shrink extension_opcode to 9 bits. Make it signed. Change value of None. Shrink operands to 3 bits. --- Code-generation wise it may be better to move the signed extension_opcode field last within the containing 32-bit slot. --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -917,7 +917,7 @@ typedef struct insn_template /* base_opcode is the fundamental opcode byte without optional prefix(es). */ - unsigned int base_opcode; + unsigned int base_opcode:16; #define Opcode_D 0x2 /* Direction bit: set if Reg --> Regmem; unset if Regmem --> Reg. */ @@ -934,8 +934,8 @@ typedef struct insn_template AMD 3DNow! instructions. If this template has no extension opcode (the usual case) use None Instructions */ - unsigned short extension_opcode; -#define None 0xffff /* If no extension_opcode is possible. */ + signed int extension_opcode:9; +#define None (-1) /* If no extension_opcode is possible. */ /* Pseudo prefixes. */ #define Prefix_Disp8 0 /* {disp8} */ @@ -950,7 +950,7 @@ typedef struct insn_template #define Prefix_NoOptimize 9 /* {nooptimize} */ /* how many operands */ - unsigned char operands; + unsigned int operands:3; /* the bits in opcode_modifier are used to generate the final opcode from the base_opcode. These bits also are used to detect alternate forms of