From mboxrd@z Thu Jan  1 00:00:00 1970
From: Timothy Wall <twall@tiac.net>
To: binutils@sourceware.cygnus.com
Subject: Linker overlay pages strategy [Q]
Date: Thu, 19 Aug 1999 19:37:00 -0000
Message-id: <37BCBF63.BAE42A52@tiac.net>
X-SW-Source: 1999-08/msg00123.html

I'm trying to figure out the best way to handle a processor's dual
address space as it relates to the linker and script files.  Fortunately

I don't have to do compatibility with the other vendor's linker scripts,

but there are a few options I need to include.  First is being able to
specify separate allocations for load-time and run-time addresses of
sections, and second, being able to map into two overlapping addrss
spaces.

Most links for this target (TIC54X) specify memory regions for PROG
(usually ROM) and DATA (maybe on-chip, maybe not), these usually get
designated pages 0 and 1, respectively.

Some sections may be designated to have a different "run time"
allocation, which may be on the same or a different page.  e.g.

MEMORY
{
    PAGE 0: PROG: ORIGIN 0x0000 LENGTH 0xFF00
   PAGE 1: DATA: ORIGIN 0x0080 LENGTH 0xFF80
}

SECTIONS
{
    .text: load = PROG, run = 0x800
    .cinit: load = PROG, run = DATA
}

So what this does is effectively allocate two sections per section.  The

text section is expected to be relocated before running (so all
relocations are done for the "run" address).
Note that the memory "pages" have overlapping address space.

So for the first item, I can link each section in twice.
The overlay functions more or less provide the second item, though I'd
prefer to keep the semantics closer to the above example (which
represents putting sections into two memory areas which happen to have
the same address) rather than using the OVERLAY semantics (which puts
more than one section into the same address).

Any comments, ideas, references?  Please CC twall@tiac.net, as I am not
subscribed to the list.

Thanks
Tim Wall