From: "Andre Vieira (lists)" <andre.simoesdiasvieira@arm.com>
To: binutils@sourceware.org
Subject: [PATCH 8/57][Arm][GAS] Add support for MVE instructions: vcvt
Date: Wed, 01 May 2019 17:02:00 -0000 [thread overview]
Message-ID: <37c72fd3-c5ed-31af-8da1-3d675e915b87@arm.com> (raw)
In-Reply-To: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com>
[-- Attachment #1: Type: text/plain, Size: 1068 bytes --]
Hi,
This patch adds support for all MVE VCVT instructions.
gas/ChangeLog:
2019-05-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): Add new operand.
(parse_operands): Handle new operand.
(do_neon_cvt_1): Handle MVE variants.
(do_neon_cvttb_1): Likewise.
(insns): Accept MVE variants.
* testsuite/gas/arm/mve-vcvt-bad-1.d: New test.
* testsuite/gas/arm/mve-vcvt-bad-1.l: New test.
* testsuite/gas/arm/mve-vcvt-bad-1.s: New test.
* testsuite/gas/arm/mve-vcvt-bad-2.d: New test.
* testsuite/gas/arm/mve-vcvt-bad-2.l: New test.
* testsuite/gas/arm/mve-vcvt-bad-2.s: New test.
* testsuite/gas/arm/mve-vcvt-bad-3.d: New test.
* testsuite/gas/arm/mve-vcvt-bad-3.l: New test.
* testsuite/gas/arm/mve-vcvt-bad-3.s: New test.
* testsuite/gas/arm/mve-vcvt-bad-4.d: New test.
* testsuite/gas/arm/mve-vcvt-bad-4.l: New test.
* testsuite/gas/arm/mve-vcvt-bad-4.s: New test.
* testsuite/gas/arm/mve-vcvt-bad.d: New test.
* testsuite/gas/arm/mve-vcvt-bad.l: New test.
* testsuite/gas/arm/mve-vcvt-bad.s: New test.
[-- Attachment #2: 8.patch --]
[-- Type: text/x-patch, Size: 44451 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 08c9cac990af2c9bace573d197b9339ff382e999..59cf887e6ba007ed2f516fa6975d66bc88579107 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -6778,6 +6778,7 @@ enum operand_parse_code
OP_RNQ, /* Neon quad precision register */
OP_RNQMQ, /* Neon quad or MVE vector register */
OP_RVSD, /* VFP single or double precision register */
+ OP_RVSDMQ, /* VFP single, double precision or MVE vector register. */
OP_RNSD, /* Neon single or double precision register */
OP_RNDQ, /* Neon double or quad precision register */
OP_RNDQMQ, /* Neon double, quad or MVE vector register */
@@ -7049,7 +7050,6 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
if (op_parse_code >= OP_FIRST_OPTIONAL)
{
/* Remember where we are in case we need to backtrack. */
- gas_assert (!backtrack_pos);
backtrack_pos = str;
backtrack_error = inst.error;
backtrack_index = i;
@@ -7117,6 +7117,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
try_rndq:
case OP_oRNDQ:
case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
+ case OP_RVSDMQ:
+ po_reg_or_goto (REG_TYPE_MQ, try_rvsd);
+ break;
+ try_rvsd:
case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
case OP_oRNSDQ:
case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
@@ -17031,15 +17035,64 @@ do_neon_cvt_1 (enum neon_cvt_mode mode)
switch (rs)
{
- case NS_DDI:
case NS_QQI:
+ if (mode == neon_cvt_mode_z
+ && (flavour == neon_cvt_flavour_f16_s16
+ || flavour == neon_cvt_flavour_f16_u16
+ || flavour == neon_cvt_flavour_s16_f16
+ || flavour == neon_cvt_flavour_u16_f16
+ || flavour == neon_cvt_flavour_f32_u32
+ || flavour == neon_cvt_flavour_f32_s32
+ || flavour == neon_cvt_flavour_s32_f32
+ || flavour == neon_cvt_flavour_u32_f32))
+ {
+ if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH))
+ return;
+ }
+ else if (mode == neon_cvt_mode_n)
+ {
+ /* We are dealing with vcvt with the 'ne' condition. */
+ inst.cond = 0x1;
+ inst.instruction = N_MNEM_vcvt;
+ do_neon_cvt_1 (neon_cvt_mode_z);
+ return;
+ }
+ /* fall through. */
+ case NS_DDI:
{
unsigned immbits;
unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
0x0000100, 0x1000100, 0x0, 0x1000000};
- if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
- return;
+ if ((rs != NS_QQI || !ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
+ && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+ return;
+
+ if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
+ {
+ constraint (inst.operands[2].present && inst.operands[2].imm == 0,
+ _("immediate value out of range"));
+ switch (flavour)
+ {
+ case neon_cvt_flavour_f16_s16:
+ case neon_cvt_flavour_f16_u16:
+ case neon_cvt_flavour_s16_f16:
+ case neon_cvt_flavour_u16_f16:
+ constraint (inst.operands[2].imm > 16,
+ _("immediate value out of range"));
+ break;
+ case neon_cvt_flavour_f32_u32:
+ case neon_cvt_flavour_f32_s32:
+ case neon_cvt_flavour_s32_f32:
+ case neon_cvt_flavour_u32_f32:
+ constraint (inst.operands[2].imm > 32,
+ _("immediate value out of range"));
+ break;
+ default:
+ inst.error = BAD_FPU;
+ return;
+ }
+ }
/* Fixed-point conversion with #0 immediate is encoded as an
integer conversion. */
@@ -17072,14 +17125,40 @@ do_neon_cvt_1 (enum neon_cvt_mode mode)
}
break;
- case NS_DD:
case NS_QQ:
+ if ((mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
+ || mode == neon_cvt_mode_m || mode == neon_cvt_mode_p)
+ && (flavour == neon_cvt_flavour_s16_f16
+ || flavour == neon_cvt_flavour_u16_f16
+ || flavour == neon_cvt_flavour_s32_f32
+ || flavour == neon_cvt_flavour_u32_f32))
+ {
+ if (check_simd_pred_availability (1,
+ NEON_CHECK_CC | NEON_CHECK_ARCH8))
+ return;
+ }
+ else if (mode == neon_cvt_mode_z
+ && (flavour == neon_cvt_flavour_f16_s16
+ || flavour == neon_cvt_flavour_f16_u16
+ || flavour == neon_cvt_flavour_s16_f16
+ || flavour == neon_cvt_flavour_u16_f16
+ || flavour == neon_cvt_flavour_f32_u32
+ || flavour == neon_cvt_flavour_f32_s32
+ || flavour == neon_cvt_flavour_s32_f32
+ || flavour == neon_cvt_flavour_u32_f32))
+ {
+ if (check_simd_pred_availability (1,
+ NEON_CHECK_CC | NEON_CHECK_ARCH))
+ return;
+ }
+ /* fall through. */
+ case NS_DD:
if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
{
- NEON_ENCODE (FLOAT, inst);
- set_pred_insn_type (OUTSIDE_PRED_INSN);
- if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
+ NEON_ENCODE (FLOAT, inst);
+ if (check_simd_pred_availability (1,
+ NEON_CHECK_CC | NEON_CHECK_ARCH8))
return;
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
@@ -17109,8 +17188,11 @@ do_neon_cvt_1 (enum neon_cvt_mode mode)
NEON_ENCODE (INTEGER, inst);
- if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
- return;
+ if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
+ {
+ if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+ return;
+ }
if (flavour != neon_cvt_flavour_invalid)
inst.instruction |= enctab[flavour];
@@ -17229,10 +17311,51 @@ static void
do_neon_cvttb_1 (bfd_boolean t)
{
enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD,
- NS_DF, NS_DH, NS_NULL);
+ NS_DF, NS_DH, NS_QQ, NS_QQI, NS_NULL);
if (rs == NS_NULL)
return;
+ else if (rs == NS_QQ || rs == NS_QQI)
+ {
+ int single_to_half = 0;
+ if (check_simd_pred_availability (1, NEON_CHECK_ARCH))
+ return;
+
+ enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
+
+ if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
+ && (flavour == neon_cvt_flavour_u16_f16
+ || flavour == neon_cvt_flavour_s16_f16
+ || flavour == neon_cvt_flavour_f16_s16
+ || flavour == neon_cvt_flavour_f16_u16
+ || flavour == neon_cvt_flavour_u32_f32
+ || flavour == neon_cvt_flavour_s32_f32
+ || flavour == neon_cvt_flavour_f32_s32
+ || flavour == neon_cvt_flavour_f32_u32))
+ {
+ inst.cond = 0xf;
+ inst.instruction = N_MNEM_vcvt;
+ set_pred_insn_type (INSIDE_VPT_INSN);
+ do_neon_cvt_1 (neon_cvt_mode_z);
+ return;
+ }
+ else if (rs == NS_QQ && flavour == neon_cvt_flavour_f32_f16)
+ single_to_half = 1;
+ else if (rs == NS_QQ && flavour != neon_cvt_flavour_f16_f32)
+ {
+ first_error (BAD_FPU);
+ return;
+ }
+
+ inst.instruction = 0xee3f0e01;
+ inst.instruction |= single_to_half << 28;
+ inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+ inst.instruction |= LOW4 (inst.operands[0].reg) << 13;
+ inst.instruction |= t << 12;
+ inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+ inst.instruction |= LOW4 (inst.operands[1].reg) << 1;
+ inst.is_neon = 1;
+ }
else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
{
inst.error = NULL;
@@ -21839,10 +21962,6 @@ static const struct asm_opcode insns[] =
nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
- nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
- nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
- nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
- nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
@@ -22503,10 +22622,10 @@ static const struct asm_opcode insns[] =
NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
- nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
+ mnCEF(vcvt, _vcvt, 3, (RNSDQMQ, RNSDQMQ, oI32z), neon_cvt),
nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
- NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
- NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
+ MNCEF(vcvtb, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtb),
+ MNCEF(vcvtt, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtt),
/* NOTE: All VMOV encoding is special-cased! */
@@ -23266,7 +23385,14 @@ static const struct asm_opcode insns[] =
MNCEF(vabs, 1b10300, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
MNCEF(vneg, 1b10380, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
-#undef ARM_VARIANT
+#undef ARM_VARIANT
+#define ARM_VARIANT & fpu_vfp_ext_armv8xd
+ mnUF(vcvta, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvta),
+ mnUF(vcvtp, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtp),
+ mnUF(vcvtn, _vcvta, 3, (RNSDQMQ, oRNSDQMQ, oI32z), neon_cvtn),
+ mnUF(vcvtm, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtm),
+
+#undef ARM_VARIANT
#define ARM_VARIANT & fpu_neon_ext_v1
mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
mnUF(vabdl, _vabdl, 3, (RNQMQ, RNDMQ, RNDMQ), neon_dyadic_long),
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-1.d b/gas/testsuite/gas/arm/mve-vcvt-bad-1.d
new file mode 100644
index 0000000000000000000000000000000000000000..15ba724a6fdd4a03e4aaa1e85e796b2aa882b338
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-1.d
@@ -0,0 +1,6 @@
+#name: bad MVE VCVT (between floating-point and fixed-point) instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vcvt-bad-1.l
+
+.*: +file format .*arm.*
+
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-1.l b/gas/testsuite/gas/arm/mve-vcvt-bad-1.l
new file mode 100644
index 0000000000000000000000000000000000000000..4c727d305b4c5d1bf1b21dd11c28a361ea3563c7
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-1.l
@@ -0,0 +1,75 @@
+[^:]*: Assembler messages:
+[^:]*:12: Error: immediate value out of range -- `vcvt.f16.s16 q0,q1,#0'
+[^:]*:13: Error: immediate value out of range -- `vcvt.s16.f16 q0,q1,#0'
+[^:]*:14: Error: immediate value out of range -- `vcvt.f16.u16 q0,q1,#0'
+[^:]*:15: Error: immediate value out of range -- `vcvt.u16.f16 q0,q1,#0'
+[^:]*:16: Error: immediate value out of range -- `vcvt.f16.s16 q0,q1,#17'
+[^:]*:17: Error: immediate value out of range -- `vcvt.s16.f16 q0,q1,#17'
+[^:]*:18: Error: immediate value out of range -- `vcvt.f16.u16 q0,q1,#17'
+[^:]*:19: Error: immediate value out of range -- `vcvt.u16.f16 q0,q1,#17'
+[^:]*:20: Error: immediate value out of range -- `vcvt.f32.s32 q0,q1,#0'
+[^:]*:21: Error: immediate value out of range -- `vcvt.s32.f32 q0,q1,#0'
+[^:]*:22: Error: immediate value out of range -- `vcvt.f32.u32 q0,q1,#0'
+[^:]*:23: Error: immediate value out of range -- `vcvt.u32.f32 q0,q1,#0'
+[^:]*:24: Error: immediate value out of range -- `vcvt.f32.s32 q0,q1,#33'
+[^:]*:25: Error: immediate value out of range -- `vcvt.s32.f32 q0,q1,#33'
+[^:]*:26: Error: immediate value out of range -- `vcvt.f32.u32 q0,q1,#33'
+[^:]*:27: Error: immediate value out of range -- `vcvt.u32.f32 q0,q1,#33'
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Error: bad type in SIMD instruction -- `vcvt.f64.u64 q0,q1,#1'
+[^:]*:30: Error: bad type in SIMD instruction -- `vcvt.u64.f64 q0,q1,#1'
+[^:]*:31: Error: bad type in SIMD instruction -- `vcvt.f64.s64 q0,q1,#1'
+[^:]*:32: Error: bad type in SIMD instruction -- `vcvt.s64.f64 q0,q1,#1'
+[^:]*:34: Error: syntax error -- `vcvteq.f32.u32 q0,q1,#1'
+[^:]*:35: Error: syntax error -- `vcvteq.f32.u32 q0,q1,#1'
+[^:]*:37: Error: syntax error -- `vcvteq.f32.u32 q0,q1,#1'
+[^:]*:39: Error: instruction missing MVE vector predication code -- `vcvt.f32.u32 q0,q1,#1'
+[^:]*:40: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtt.f32.u32 q0,q1,#1'
+
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-1.s b/gas/testsuite/gas/arm/mve-vcvt-bad-1.s
new file mode 100644
index 0000000000000000000000000000000000000000..401014ac842336c8f4535541ec06071e7d9a3cdc
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-1.s
@@ -0,0 +1,40 @@
+.macro cond
+.irp cond, eq, ne, gt, ge, lt, le
+.irp size, .f16.s16, .s16.f16, .f16.u16, .u16.f16, .f32.s32, .s32.f32, .f32.u32, .u32.f32
+it \cond
+vcvt\size q0, q1, #1
+.endr
+.endr
+.endm
+
+.syntax unified
+.thumb
+vcvt.f16.s16 q0, q1, #0
+vcvt.s16.f16 q0, q1, #0
+vcvt.f16.u16 q0, q1, #0
+vcvt.u16.f16 q0, q1, #0
+vcvt.f16.s16 q0, q1, #17
+vcvt.s16.f16 q0, q1, #17
+vcvt.f16.u16 q0, q1, #17
+vcvt.u16.f16 q0, q1, #17
+vcvt.f32.s32 q0, q1, #0
+vcvt.s32.f32 q0, q1, #0
+vcvt.f32.u32 q0, q1, #0
+vcvt.u32.f32 q0, q1, #0
+vcvt.f32.s32 q0, q1, #33
+vcvt.s32.f32 q0, q1, #33
+vcvt.f32.u32 q0, q1, #33
+vcvt.u32.f32 q0, q1, #33
+cond
+vcvt.f64.u64 q0, q1, #1
+vcvt.u64.f64 q0, q1, #1
+vcvt.f64.s64 q0, q1, #1
+vcvt.s64.f64 q0, q1, #1
+it eq
+vcvteq.f32.u32 q0, q1, #1
+vcvteq.f32.u32 q0, q1, #1
+vpst
+vcvteq.f32.u32 q0, q1, #1
+vpst
+vcvt.f32.u32 q0, q1, #1
+vcvtt.f32.u32 q0, q1, #1
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-2.d b/gas/testsuite/gas/arm/mve-vcvt-bad-2.d
new file mode 100644
index 0000000000000000000000000000000000000000..eb98daa7b25d38dbe52b485fca1b93e0d256ab4a
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-2.d
@@ -0,0 +1,5 @@
+#name: bad MVE VCVT (between floating-point and integer) instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vcvt-bad-2.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-2.l b/gas/testsuite/gas/arm/mve-vcvt-bad-2.l
new file mode 100644
index 0000000000000000000000000000000000000000..a608fd45ecad3fe8935bf52029e3b2e3232f16d3
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-2.l
@@ -0,0 +1,58 @@
+[^:]*: Assembler messages:
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Error: bad type in SIMD instruction -- `vcvt.u64.f64 q0,q1'
+[^:]*:14: Error: bad type in SIMD instruction -- `vcvt.f64.u64 q0,q1'
+[^:]*:15: Error: bad type in SIMD instruction -- `vcvt.s64.f64 q0,q1'
+[^:]*:16: Error: bad type in SIMD instruction -- `vcvt.f64.s64 q0,q1'
+[^:]*:18: Error: syntax error -- `vcvteq.f32.s32 q0,q1'
+[^:]*:19: Error: syntax error -- `vcvteq.f32.s32 q0,q1'
+[^:]*:21: Error: syntax error -- `vcvteq.f32.s32 q0,q1'
+[^:]*:23: Error: instruction missing MVE vector predication code -- `vcvt.f32.s32 q0,q1'
+[^:]*:24: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtt.f32.s32 q0,q1'
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-2.s b/gas/testsuite/gas/arm/mve-vcvt-bad-2.s
new file mode 100644
index 0000000000000000000000000000000000000000..e3dc08b6faf5e364b9ebae33be830932e9ee718c
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-2.s
@@ -0,0 +1,24 @@
+.macro cond
+.irp cond, eq, ne, gt, ge, lt, le
+.irp size, .f16.s16, .s16.f16, .f16.u16, .u16.f16, .f32.s32, .s32.f32, .f32.u32, .u32.f32
+it \cond
+vcvt\size q0, q1
+.endr
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond
+vcvt.u64.f64 q0, q1
+vcvt.f64.u64 q0, q1
+vcvt.s64.f64 q0, q1
+vcvt.f64.s64 q0, q1
+it eq
+vcvteq.f32.s32 q0, q1
+vcvteq.f32.s32 q0, q1
+vpst
+vcvteq.f32.s32 q0, q1
+vpst
+vcvt.f32.s32 q0, q1
+vcvtt.f32.s32 q0, q1
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-3.d b/gas/testsuite/gas/arm/mve-vcvt-bad-3.d
new file mode 100644
index 0000000000000000000000000000000000000000..b85a41e015f17810c36b393820902e9e23b811f2
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-3.d
@@ -0,0 +1,5 @@
+#name: bad MVE VCVT (between single and half precision floating-point) instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vcvt-bad-3.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-3.l b/gas/testsuite/gas/arm/mve-vcvt-bad-3.l
new file mode 100644
index 0000000000000000000000000000000000000000..c51fd434ea015fab4bea0a080503d789f0122287
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-3.l
@@ -0,0 +1,39 @@
+[^:]*: Assembler messages:
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Error: bad type in SIMD instruction -- `vcvt.f64.f16 q0,q1'
+[^:]*:16: Error: bad type in SIMD instruction -- `vcvt.f64.f32 q0,q1'
+[^:]*:17: Error: bad type in SIMD instruction -- `vcvt.f16.f64 q0,q1'
+[^:]*:18: Error: bad type in SIMD instruction -- `vcvt.f32.f64 q0,q1'
+[^:]*:20: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
+[^:]*:21: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
+[^:]*:23: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
+[^:]*:24: Error: vector predicated instruction should be in VPT/VPST block -- `vcvttt.f16.f32 q0,q1'
+[^:]*:26: Error: instruction missing MVE vector predication code -- `vcvtt.f16.f32 q0,q1'
+[^:]*:28: Error: syntax error -- `vcvtbeq.f16.f32 q0,q1'
+[^:]*:29: Error: syntax error -- `vcvtbeq.f16.f32 q0,q1'
+[^:]*:31: Error: syntax error -- `vcvtbeq.f16.f32 q0,q1'
+[^:]*:32: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtbt.f16.f32 q0,q1'
+[^:]*:34: Error: instruction missing MVE vector predication code -- `vcvtb.f16.f32 q0,q1'
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-3.s b/gas/testsuite/gas/arm/mve-vcvt-bad-3.s
new file mode 100644
index 0000000000000000000000000000000000000000..6552cd21b9ed135b0a088d7c878d86b2e792bbf9
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-3.s
@@ -0,0 +1,34 @@
+.macro cond
+.irp top, t, b
+.irp cond, eq, ne, gt, ge, lt, le
+.irp size, .f16.f32, .f32.f16
+it \cond
+vcvt\top\size q0, q1
+.endr
+.endr
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond
+vcvt.f64.f16 q0, q1
+vcvt.f64.f32 q0, q1
+vcvt.f16.f64 q0, q1
+vcvt.f32.f64 q0, q1
+it eq
+vcvtteq.f16.f32 q0, q1
+vcvtteq.f16.f32 q0, q1
+vpst
+vcvtteq.f16.f32 q0, q1
+vcvttt.f16.f32 q0, q1
+vpst
+vcvtt.f16.f32 q0, q1
+it eq
+vcvtbeq.f16.f32 q0, q1
+vcvtbeq.f16.f32 q0, q1
+vpst
+vcvtbeq.f16.f32 q0, q1
+vcvtbt.f16.f32 q0, q1
+vpst
+vcvtb.f16.f32 q0, q1
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-4.d b/gas/testsuite/gas/arm/mve-vcvt-bad-4.d
new file mode 100644
index 0000000000000000000000000000000000000000..2b46152d988a642d869e699d66be2f13958ed085
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-4.d
@@ -0,0 +1,5 @@
+#name: bad MVE VCVT (from floating-point to integer) instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vcvt-bad-4.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-4.l b/gas/testsuite/gas/arm/mve-vcvt-bad-4.l
new file mode 100644
index 0000000000000000000000000000000000000000..36d423af26d91da7f87cf3860aaadb4b47c64678
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-4.l
@@ -0,0 +1,133 @@
+[^:]*: Assembler messages:
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Error: bad type in SIMD instruction -- `vcvta.s64.f64 q0,q1'
+[^:]*:16: Error: bad type in SIMD instruction -- `vcvta.u64.f64 q0,q1'
+[^:]*:17: Error: bad type in SIMD instruction -- `vcvta.f64.s64 q0,q1'
+[^:]*:18: Error: bad type in SIMD instruction -- `vcvta.f64.u64 q0,q1'
+[^:]*:19: Error: bad type in SIMD instruction -- `vcvtn.s64.f64 q0,q1'
+[^:]*:20: Error: bad type in SIMD instruction -- `vcvtn.u64.f64 q0,q1'
+[^:]*:21: Error: bad type in SIMD instruction -- `vcvtn.f64.s64 q0,q1'
+[^:]*:22: Error: bad type in SIMD instruction -- `vcvtn.f64.u64 q0,q1'
+[^:]*:23: Error: bad type in SIMD instruction -- `vcvtp.s64.f64 q0,q1'
+[^:]*:24: Error: bad type in SIMD instruction -- `vcvtp.u64.f64 q0,q1'
+[^:]*:25: Error: bad type in SIMD instruction -- `vcvtp.f64.s64 q0,q1'
+[^:]*:26: Error: bad type in SIMD instruction -- `vcvtp.f64.u64 q0,q1'
+[^:]*:27: Error: bad type in SIMD instruction -- `vcvtm.s64.f64 q0,q1'
+[^:]*:28: Error: bad type in SIMD instruction -- `vcvtm.u64.f64 q0,q1'
+[^:]*:29: Error: bad type in SIMD instruction -- `vcvtm.f64.s64 q0,q1'
+[^:]*:30: Error: bad type in SIMD instruction -- `vcvtm.f64.u64 q0,q1'
+[^:]*:32: Error: syntax error -- `vcvtaeq.s32.f32 q0,q1'
+[^:]*:33: Error: syntax error -- `vcvtaeq.s32.f32 q0,q1'
+[^:]*:35: Error: syntax error -- `vcvtaeq.s32.f32 q0,q1'
+[^:]*:36: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtat.s32.f32 q0,q1'
+[^:]*:38: Error: instruction missing MVE vector predication code -- `vcvta.s32.f32 q0,q1'
+[^:]*:40: Error: syntax error -- `vcvtneq.s32.f32 q0,q1'
+[^:]*:41: Error: syntax error -- `vcvtneq.s32.f32 q0,q1'
+[^:]*:43: Error: syntax error -- `vcvtneq.s32.f32 q0,q1'
+[^:]*:44: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtnt.s32.f32 q0,q1'
+[^:]*:46: Error: instruction missing MVE vector predication code -- `vcvtn.s32.f32 q0,q1'
+[^:]*:48: Error: syntax error -- `vcvtpeq.s32.f32 q0,q1'
+[^:]*:49: Error: syntax error -- `vcvtpeq.s32.f32 q0,q1'
+[^:]*:51: Error: syntax error -- `vcvtpeq.s32.f32 q0,q1'
+[^:]*:52: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtpt.s32.f32 q0,q1'
+[^:]*:54: Error: instruction missing MVE vector predication code -- `vcvtp.s32.f32 q0,q1'
+[^:]*:56: Error: syntax error -- `vcvtmeq.s32.f32 q0,q1'
+[^:]*:57: Error: syntax error -- `vcvtmeq.s32.f32 q0,q1'
+[^:]*:59: Error: syntax error -- `vcvtmeq.s32.f32 q0,q1'
+[^:]*:60: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtmt.s32.f32 q0,q1'
+[^:]*:62: Error: instruction missing MVE vector predication code -- `vcvtm.s32.f32 q0,q1'
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-4.s b/gas/testsuite/gas/arm/mve-vcvt-bad-4.s
new file mode 100644
index 0000000000000000000000000000000000000000..cffb6e4076e85b002cfc8ffda811f41eb95ad1b8
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-4.s
@@ -0,0 +1,62 @@
+.macro cond
+.irp round, a, n, p, m
+.irp cond, eq, ne, gt, ge, lt, le
+.irp size, .s16.f16, .u16.f16, .s32.f32, .u32.f32
+it \cond
+vcvt\round\size q0, q1
+.endr
+.endr
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond
+vcvta.s64.f64 q0, q1
+vcvta.u64.f64 q0, q1
+vcvta.f64.s64 q0, q1
+vcvta.f64.u64 q0, q1
+vcvtn.s64.f64 q0, q1
+vcvtn.u64.f64 q0, q1
+vcvtn.f64.s64 q0, q1
+vcvtn.f64.u64 q0, q1
+vcvtp.s64.f64 q0, q1
+vcvtp.u64.f64 q0, q1
+vcvtp.f64.s64 q0, q1
+vcvtp.f64.u64 q0, q1
+vcvtm.s64.f64 q0, q1
+vcvtm.u64.f64 q0, q1
+vcvtm.f64.s64 q0, q1
+vcvtm.f64.u64 q0, q1
+it eq
+vcvtaeq.s32.f32 q0, q1
+vcvtaeq.s32.f32 q0, q1
+vpst
+vcvtaeq.s32.f32 q0, q1
+vcvtat.s32.f32 q0, q1
+vpst
+vcvta.s32.f32 q0, q1
+it eq
+vcvtneq.s32.f32 q0, q1
+vcvtneq.s32.f32 q0, q1
+vpst
+vcvtneq.s32.f32 q0, q1
+vcvtnt.s32.f32 q0, q1
+vpst
+vcvtn.s32.f32 q0, q1
+it eq
+vcvtpeq.s32.f32 q0, q1
+vcvtpeq.s32.f32 q0, q1
+vpst
+vcvtpeq.s32.f32 q0, q1
+vcvtpt.s32.f32 q0, q1
+vpst
+vcvtp.s32.f32 q0, q1
+it eq
+vcvtmeq.s32.f32 q0, q1
+vcvtmeq.s32.f32 q0, q1
+vpst
+vcvtmeq.s32.f32 q0, q1
+vcvtmt.s32.f32 q0, q1
+vpst
+vcvtm.s32.f32 q0, q1
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad.d b/gas/testsuite/gas/arm/mve-vcvt-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..dd0ec53319b46562663ab98b42617e5657c23be6
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad.d
@@ -0,0 +1,6 @@
+#name: bad MVE VCVT instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vcvt-bad.l
+
+.*: +file format .*arm.*
+
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad.l b/gas/testsuite/gas/arm/mve-vcvt-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..7c4ea69c4a8cb0916f4273ce13f117db174d11eb
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad.l
@@ -0,0 +1,77 @@
+[^:]*: Assembler messages:
+[^:]*:11: Error: immediate value out of range -- `vcvt.f16.s16 q0,q1,#0'
+[^:]*:12: Error: immediate value out of range -- `vcvt.f16.s16 q0,q1,#17'
+[^:]*:13: Error: immediate value out of range -- `vcvt.f16.u16 q0,q1,#0'
+[^:]*:14: Error: immediate value out of range -- `vcvt.f16.u16 q0,q1,#17'
+[^:]*:15: Error: immediate value out of range -- `vcvt.s16.f16 q0,q1,#0'
+[^:]*:16: Error: immediate value out of range -- `vcvt.s16.f16 q0,q1,#17'
+[^:]*:17: Error: immediate value out of range -- `vcvt.u16.f16 q0,q1,#0'
+[^:]*:18: Error: immediate value out of range -- `vcvt.u16.f16 q0,q1,#17'
+[^:]*:19: Error: immediate value out of range -- `vcvt.f32.s32 q0,q1,#0'
+[^:]*:20: Error: immediate value out of range -- `vcvt.f32.s32 q0,q1,#33'
+[^:]*:21: Error: immediate value out of range -- `vcvt.f32.u32 q0,q1,#0'
+[^:]*:22: Error: immediate value out of range -- `vcvt.f32.u32 q0,q1,#33'
+[^:]*:23: Error: immediate value out of range -- `vcvt.s32.f32 q0,q1,#0'
+[^:]*:24: Error: immediate value out of range -- `vcvt.s32.f32 q0,q1,#33'
+[^:]*:25: Error: immediate value out of range -- `vcvt.u32.f32 q0,q1,#0'
+[^:]*:26: Error: immediate value out of range -- `vcvt.u32.f32 q0,q1,#33'
+[^:]*:27: Error: bad type in SIMD instruction -- `vcvt.f64.s64 q0,q1,#1'
+[^:]*:28: Error: bad type in SIMD instruction -- `vcvt.f64.u64 q0,q1,#1'
+[^:]*:29: Error: bad type in SIMD instruction -- `vcvt.s64.f64 q0,q1,#1'
+[^:]*:30: Error: bad type in SIMD instruction -- `vcvt.u64.f64 q0,q1,#1'
+[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:33: Error: syntax error -- `vcvteq.f16.s16 q0,q1,#1'
+[^:]*:34: Error: syntax error -- `vcvteq.f16.s16 q0,q1,#1'
+[^:]*:36: Error: syntax error -- `vcvteq.f16.s16 q0,q1,#1'
+[^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtt.f16.s16 q0,q1,#1'
+[^:]*:39: Error: instruction missing MVE vector predication code -- `vcvt.f16.s16 q0,q1,#1'
+[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:49: Error: bad type in SIMD instruction -- `vcvt.f64.s64 q0,q1'
+[^:]*:50: Error: bad type in SIMD instruction -- `vcvt.f64.u64 q0,q1'
+[^:]*:51: Error: bad type in SIMD instruction -- `vcvt.s64.f64 q0,q1'
+[^:]*:52: Error: bad type in SIMD instruction -- `vcvt.u64.f64 q0,q1'
+[^:]*:54: Error: syntax error -- `vcvteq.u32.f32 q0,q1'
+[^:]*:55: Error: syntax error -- `vcvteq.u32.f32 q0,q1'
+[^:]*:57: Error: syntax error -- `vcvteq.u32.f32 q0,q1'
+[^:]*:58: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtt.u32.f32 q0,q1'
+[^:]*:60: Error: instruction missing MVE vector predication code -- `vcvt.u32.f32 q0,q1'
+[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:70: Error: bad type in SIMD instruction -- `vcvtb.f16.f64 q0,q1'
+[^:]*:71: Error: bad type in SIMD instruction -- `vcvtb.f64.f16 q0,q1'
+[^:]*:72: Error: bad type in SIMD instruction -- `vcvtb.f32.f64 q0,q1'
+[^:]*:73: Error: bad type in SIMD instruction -- `vcvtb.f64.f32 q0,q1'
+[^:]*:75: Error: syntax error -- `vcvtbeq.f16.f32 q0,q1'
+[^:]*:76: Error: syntax error -- `vcvtbeq.f16.f32 q0,q1'
+[^:]*:78: Error: syntax error -- `vcvtbeq.f16.f32 q0,q1'
+[^:]*:79: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtbt.f16.f32 q0,q1'
+[^:]*:81: Error: instruction missing MVE vector predication code -- `vcvtb.f16.f32 q0,q1'
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:83: Error: bad type in SIMD instruction -- `vcvtt.f16.f64 q0,q1'
+[^:]*:84: Error: bad type in SIMD instruction -- `vcvtt.f64.f16 q0,q1'
+[^:]*:85: Error: bad type in SIMD instruction -- `vcvtt.f32.f64 q0,q1'
+[^:]*:86: Error: bad type in SIMD instruction -- `vcvtt.f64.f32 q0,q1'
+[^:]*:88: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
+[^:]*:89: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
+[^:]*:91: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
+[^:]*:92: Error: vector predicated instruction should be in VPT/VPST block -- `vcvttt.f16.f32 q0,q1'
+[^:]*:94: Error: instruction missing MVE vector predication code -- `vcvtt.f16.f32 q0,q1'
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad.s b/gas/testsuite/gas/arm/mve-vcvt-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..302fe88223c97e1d48123a5f120fbfbb5cf14fed
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad.s
@@ -0,0 +1,94 @@
+.macro cond1
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vcvt\().f16.s16 q0, q1, #1
+.endr
+.endm
+
+.syntax unified
+.thumb
+
+vcvt.f16.s16 q0, q1, #0
+vcvt.f16.s16 q0, q1, #17
+vcvt.f16.u16 q0, q1, #0
+vcvt.f16.u16 q0, q1, #17
+vcvt.s16.f16 q0, q1, #0
+vcvt.s16.f16 q0, q1, #17
+vcvt.u16.f16 q0, q1, #0
+vcvt.u16.f16 q0, q1, #17
+vcvt.f32.s32 q0, q1, #0
+vcvt.f32.s32 q0, q1, #33
+vcvt.f32.u32 q0, q1, #0
+vcvt.f32.u32 q0, q1, #33
+vcvt.s32.f32 q0, q1, #0
+vcvt.s32.f32 q0, q1, #33
+vcvt.u32.f32 q0, q1, #0
+vcvt.u32.f32 q0, q1, #33
+vcvt.f64.s64 q0, q1, #1
+vcvt.f64.u64 q0, q1, #1
+vcvt.s64.f64 q0, q1, #1
+vcvt.u64.f64 q0, q1, #1
+cond1
+it eq
+vcvteq.f16.s16 q0, q1, #1
+vcvteq.f16.s16 q0, q1, #1
+vpst
+vcvteq.f16.s16 q0, q1, #1
+vcvtt.f16.s16 q0, q1, #1
+vpst
+vcvt.f16.s16 q0, q1, #1
+
+.macro cond2
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vcvt\().f16.s16 q0, q1
+.endr
+.endm
+
+cond2
+vcvt.f64.s64 q0, q1
+vcvt.f64.u64 q0, q1
+vcvt.s64.f64 q0, q1
+vcvt.u64.f64 q0, q1
+it eq
+vcvteq.u32.f32 q0, q1
+vcvteq.u32.f32 q0, q1
+vpst
+vcvteq.u32.f32 q0, q1
+vcvtt.u32.f32 q0, q1
+vpst
+vcvt.u32.f32 q0, q1
+
+.macro cond3 mnem
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\mnem\().f16.f32 q0, q1
+.endr
+.endm
+
+cond3 vcvtb
+vcvtb.f16.f64 q0, q1
+vcvtb.f64.f16 q0, q1
+vcvtb.f32.f64 q0, q1
+vcvtb.f64.f32 q0, q1
+it eq
+vcvtbeq.f16.f32 q0, q1
+vcvtbeq.f16.f32 q0, q1
+vpst
+vcvtbeq.f16.f32 q0, q1
+vcvtbt.f16.f32 q0, q1
+vpst
+vcvtb.f16.f32 q0, q1
+cond3 vcvtt
+vcvtt.f16.f64 q0, q1
+vcvtt.f64.f16 q0, q1
+vcvtt.f32.f64 q0, q1
+vcvtt.f64.f32 q0, q1
+it eq
+vcvtteq.f16.f32 q0, q1
+vcvtteq.f16.f32 q0, q1
+vpst
+vcvtteq.f16.f32 q0, q1
+vcvttt.f16.f32 q0, q1
+vpst
+vcvtt.f16.f32 q0, q1
next prev parent reply other threads:[~2019-05-01 17:02 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-01 16:51 [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 16:53 ` [PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fp Andre Vieira (lists)
2019-05-01 16:55 ` [PATCH 2/57][Arm][GAS] Add support for MVE instructions: vpst, vadd, vsub and vabd Andre Vieira (lists)
2019-05-02 10:56 ` Nick Clifton
2019-05-13 13:42 ` Andre Vieira (lists)
[not found] ` <98e50dc4-7b0e-d727-0c20-34711be86533@redhat.com>
[not found] ` <4e56a5f3-bcde-f4cd-21d4-35cc3f11b5e8@arm.com>
2019-05-14 16:53 ` Nick Clifton
2019-05-14 16:54 ` Nick Clifton
2019-05-01 16:56 ` [PATCH 3/57][Arm][GAS] Add support for MVE instructions: vabs and vneg Andre Vieira (lists)
2019-05-01 16:57 ` [PATCH 4/57][Arm][GAS] Add support for MVE instructions: vabav, vmladav and vmlsdav Andre Vieira (lists)
2019-05-01 16:59 ` [PATCH 5/57][Arm][GAS] Add support for MVE instructions: vmull{b,t} Andre Vieira (lists)
2019-05-01 17:00 ` [PATCH 6/57][Arm][GAS] Add support for MVE instructions: vst/vld{2,4} Andre Vieira (lists)
2019-05-01 17:01 ` [PATCH 7/57][Arm][GAS] Add support for MVE instructions: vstr/vldr Andre Vieira (lists)
2019-05-01 17:02 ` Andre Vieira (lists) [this message]
2019-05-01 17:03 ` [PATCH 9/57][Arm][GAS] Add support for MVE instructions: vmov Andre Vieira (lists)
2019-05-01 17:03 ` [PATCH 10/57][Arm][GAS] Add support for MVE instructions: vcmp and vpt Andre Vieira (lists)
2019-05-01 17:05 ` [PATCH 11/57][Arm][GAS] Add support for MVE instructions: vadc, vsbc and vbrsr Andre Vieira (lists)
2019-05-01 17:06 ` [PATCH 12/57][Arm][GAS] Add support for MVE instructions: vaddlv and vaddv Andre Vieira (lists)
2019-05-01 17:07 ` [PATCH 13/57][Arm][GAS] Add support for MVE instructions: vand, vbic, vorr, vorn and veor Andre Vieira (lists)
2019-05-01 17:08 ` [PATCH 14/57][Arm][GAS] Add support for MVE instructions: vcadd, vcmla and vcmul Andre Vieira (lists)
2019-05-01 17:09 ` [PATCH 15/57][Arm][GAS] Add support for MVE instructions: vcls, vclz and vfmas Andre Vieira (lists)
2019-05-01 17:09 ` [PATCH 16/57][Arm][GAS] Add support for MVE instructions: vdup, vddup, vdwdup, vidup and viwdup Andre Vieira (lists)
2019-05-01 17:11 ` [PATCH 17/57][Arm][GAS] Add support for MVE instructions: vfma and vfms Andre Vieira (lists)
2019-05-01 17:12 ` [PATCH 18/57][Arm][GAS] Add support for MVE instructions: vhcadd, vhadd, vhsub and vrhadd Andre Vieira (lists)
2019-05-01 17:12 ` [PATCH 19/57][Arm][GAS] Add support for MVE instructions: vmax[nm][a] and vmin[nm][a] Andre Vieira (lists)
2019-05-01 17:13 ` [PATCH 21/57][Arm][GAS] Add support for MVE instructions: vmaxv, vmaxav, vminv and vminav Andre Vieira (lists)
2019-05-01 17:13 ` [PATCH 20/57][Arm][GAS] Add support for MVE instructions: vmaxnmv, vmaxnmav, vminnmv and vminnmav Andre Vieira (lists)
2019-05-01 17:15 ` [PATCH 22/57][Arm][GAS] Add support for MVE instructions: vmlaldav, vmlalv, vmlsldav, vrmlaldavh, vrmlalvh and vrmlsldavh Andre Vieira (lists)
2019-05-01 17:15 ` [PATCH 23/57][Arm][GAS] Add support for MVE instructions: vmla, vmul, vqadd and vqsub Andre Vieira (lists)
2019-05-01 17:16 ` [PATCH 24/57][Arm][GAS] Add support for MVE instructions: vmlas, vmulh and vrmulh Andre Vieira (lists)
2019-05-01 17:17 ` [PATCH 26/57][Arm][GAS] Add support for MVE instructions: vpnot and vpsel Andre Vieira (lists)
2019-05-01 17:17 ` [PATCH 25/57][Arm][GAS] Add support for MVE instruction: vmvn, vqabs and vqneg Andre Vieira (lists)
2019-05-01 17:18 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 17:19 ` [PATCH 28/57][Arm][GAS] Add support for MVE instructions: vqdmlah, vqrdmlah, vqdmlash, vqrdmlash, vqdmulh and vqrdmulh Andre Vieira (lists)
2019-05-01 17:30 ` [PATCH 27/57][Arm][GAS] Add support for MVE instructions: vqdmladh, vqrdmladh, vqdmlsdh and vqrdmlsdh Andre Vieira (lists)
2019-05-01 17:31 ` [PATCH 29/57][Arm][GAS] Add support for MVE instructions: vqdmullt and vqdmullb Andre Vieira (lists)
2019-05-01 17:32 ` [PATCH 30/57][Arm][GAS] Add support for MVE instructions: vqmovnt, vqmovnb, vqmovunt, vqmovunb, vqrshl and vrshl Andre Vieira (lists)
2019-05-01 17:32 ` [PATCH 31/57][Arm][GAS] Add support for MVE instructions: vshrn[tb], vrshrn[tb], vqshrn[tb], vqshrun[tb], vqrshrn[tb] and vqrshrun[tb] Andre Vieira (lists)
2019-05-01 17:33 ` [PATCH 32/57][Arm][GAS] Add support for MVE instructions: vrintn, vrintx, vrinta, vrintz, vrintm and vrintp Andre Vieira (lists)
2019-05-01 17:34 ` [PATCH 33/57][Arm][GAS] Add support for MVE instructions: vshr, vrshr, vsli, vsri, vrev16, vrev32 and vrev64 Andre Vieira (lists)
2019-05-01 17:34 ` [PATCH 34/57][Arm][GAS] Add support for MVE instructions: vshl and vqshl Andre Vieira (lists)
2019-05-01 17:36 ` [PATCH 35/57][Arm][GAS] Add support for MVE instructions: vshlc and vshll Andre Vieira (lists)
2019-05-01 17:36 ` [PATCH 36/57][Arm][GAS] Add support for MVE instructions: wlstp, dlstp, letp and lctp Andre Vieira (lists)
2019-05-01 17:38 ` [PATCH 37/57][Arm][OBJDUMP] Add framework for MVE instructions Andre Vieira (lists)
2019-05-01 17:38 ` [PATCH 38/57][Arm][OBJDUMP] Disable the use of MVE reserved coproc numbers in coprocessor instructions Andre Vieira (lists)
2019-05-01 17:39 ` [PATCH 39/57][Arm][OBJDUMP] Add support for MVE instructions: vpt, vpst and vcmp Andre Vieira (lists)
2019-05-01 17:40 ` [PATCH 40/57][Arm][OBJDUMP] Add support for MVE instructions: vdup, veor, vfma, vfms, vhadd, vhsub and vrhadd Andre Vieira (lists)
2019-05-01 17:40 ` [PATCH 41/57][Arm][OBJDUMP] Add support for MVE instructions: vld[24] and vst[24] Andre Vieira (lists)
2019-05-01 17:41 ` [PATCH 42/57][Arm][OBJDUMP] Add support for MVE instructions: vldr[bhw] and vstr[bhw] Andre Vieira (lists)
2019-05-01 17:42 ` [PATCH 43/57][Arm][OBJDUMP] Add support for MVE instructions: scatter stores and gather loads Andre Vieira (lists)
2019-05-01 17:43 ` [PATCH 44/57][Arm][OBJDUMP] Add support for MVE instructions: vcvt and vrint Andre Vieira (lists)
2019-05-02 9:54 ` Nick Clifton
2019-05-13 13:38 ` Andre Vieira (lists)
2019-05-01 17:44 ` [PATCH 46/57][Arm][OBJDUMP] Add support for MVE instructions: vmovl, vmull, vqdmull, vqmovn, vqmovun and vmovn Andre Vieira (lists)
2019-05-01 17:44 ` [PATCH 45/57][Arm][OBJDUMP] Add support for MVE instructions: vmov, vmvn, vorr, vorn, vmovx and vbic Andre Vieira (lists)
2019-05-01 17:45 ` [PATCH 47/57][Arm][OBJDUMP] Add support for MVE instructions: vaddv, vmlaldav, vmladav, vmlas, vrmlsldavh, vmlsldav, vmlsdav, vrmlaldavh, vqdmlah, vqrdmlash, vqrdmlash, vqdmlsdh, vqrdmlsdh, vqdmulh and vqrdmulh Andre Vieira (lists)
2019-05-01 17:46 ` [PATCH 49/57][Arm][OBJDUMP] Add support for MVE complex number instructions Andre Vieira (lists)
2019-05-01 17:46 ` [PATCH 48/57][Arm][OBJDUMP] Add support for MVE instructions: vddup, vdwdup, vidup and viwdup Andre Vieira (lists)
2019-05-01 17:47 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 17:48 ` [PATCH 52/57][Arm][OBJDUMP] Add support for MVE instructions: vadc, vabav, vabd, vabs, vadd, vsbc and vsub Andre Vieira (lists)
2019-05-01 17:48 ` [PATCH 51/57][Arm][OBJDUMP] Add support for MVE instructions: lctp, letp, wlstp and dlstp Andre Vieira (lists)
2019-05-01 17:49 ` [PATCH 53/57][Arm][OBJDUMP] Add support for MVE instructions: vand, vbrsr, vcls, vclz and vctp Andre Vieira (lists)
2019-05-01 17:50 ` [PATCH 54/57][Arm][OBJDUMP] Add support for MVE instructions: vmax(a), vmax(a)v, vmaxnm(a), vmaxnm(a)v, vmin(a), vmin(a)v, vminnm(a), vminnm(a)v and vmla Andre Vieira (lists)
2019-05-01 17:50 ` [PATCH 55/57][Arm][OBJDUMP] Add support for MVE instructions: vmul, vmulh, vrmulh and vneg Andre Vieira (lists)
2019-05-01 17:51 ` [PATCH 56/57][Arm][OBJDUMP] Add support for MVE instructions: vpnot, vpsel, vqabs, vqadd, vqsub, vqneg and vrev Andre Vieira (lists)
2019-05-01 18:23 ` [PATCH 57/57][Arm][GAS] MVE Tests Andre Vieira (lists)
2019-05-01 18:24 ` Andre Vieira (lists)
2019-05-01 18:25 ` Andre Vieira (lists)
2019-05-01 18:25 ` Andre Vieira (lists)
2019-05-02 10:03 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Nick Clifton
2019-05-02 10:18 ` Nick Clifton
2019-05-13 13:39 ` [PATCH, binutils, Arm] Add Armv8.1-M Mainline and MVE enablement to NEWS Andre Vieira (lists)
2019-05-02 13:39 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Nick Clifton
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