From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Subject: [PATCH 3/4] RISC-V/gas: don't open-code insn_length()
Date: Fri, 30 Sep 2022 13:59:45 +0200 [thread overview]
Message-ID: <385d01fd-7e57-1f3f-1bae-30aa0c313d63@suse.com> (raw)
In-Reply-To: <eeb84f0c-b482-99a3-03e8-87a92789eedb@suse.com>
Use the helper when it can be used.
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1445,7 +1445,7 @@ append_insn (struct riscv_cl_insn *ip, e
|| reloc_type == BFD_RELOC_RISCV_JMP)
{
int j = reloc_type == BFD_RELOC_RISCV_JMP;
- int best_case = riscv_insn_length (ip->insn_opcode);
+ int best_case = insn_length (ip);
unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
if (now_seg == absolute_section)
next prev parent reply other threads:[~2022-09-30 11:59 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-30 11:57 [PATCH 0/4] RISC-V/gas: assorted adjustments Jan Beulich
2022-09-30 11:59 ` [PATCH 1/4] RISC-V/gas: drop riscv_subsets static variable Jan Beulich
2022-09-30 11:59 ` [PATCH 2/4] RISC-V/gas: drop stray call to install_insn() Jan Beulich
2022-09-30 11:59 ` Jan Beulich [this message]
2022-09-30 12:00 ` [PATCH 4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn Jan Beulich
2022-09-30 14:39 ` [PATCH 0/4] RISC-V/gas: assorted adjustments Nelson Chu
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