Re: SH5 compact register numbering in gcc -> gdb interface - include/elf/sh.h ?

Re: SH5 compact register numbering in gcc -> gdb interface - include/elf/sh.h ?

[Joern Rennecke]

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To give gcc and gdb a common interface, it is best put into a header file that
but
gdb/sh-tdep and gcc/config/sh/sh.h (can) include.

I thought of putting it into include/elg/sh.h, since elf is now the predominant
object format for SH gcc.  Or should we start something like an include/dwarf
directory?
But then, it's not strictly dwarf either, since these register numbers are
also used for stabs debugging info (in the SH1..SH4 coff toolchain, or if
you ask specifically for stabs.)

-- 
--------------------------
SuperH
2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
T:+44 1454 462330

[-- Attachment #2: sh-debug --]
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*** ../include/elf/sh.h-feb8	Fri Feb  8 05:05:58 2002
--- ../include/elf/sh.h	Thu May  9 22:22:18 2002
*************** START_RELOC_NUMBERS (elf_sh_reloc_type)
*** 218,221 ****
--- 218,247 ----
    RELOC_NUMBER (R_SH_64_PCREL, 255)
  END_RELOC_NUMBERS (R_SH_max)
  
+ enum
+ {
+   SH_DEBUG_INFO_R0 = 0,
+   SH_DEBUG_INFO_PR = 17,
+   SH_DEBUG_INFO_GBR = 18,
+   SH_DEBUG_INFO_MACH_BIG = 20, SH_DEBUG_INFO_MACL, SH_DEBUG_INFO_MACH_LITTLE,
+   SH_DEBUG_INFO_FPUL = 23,
+   SH_DEBUG_INFO_FPSCR = 24,
+   SH_DEBUG_INFO_FR0 = 25,
+   SH_DEBUG_INFO_XD0 = 87
+ }
+ 
+ enum
+ {
+   SH64_DEBUG_INFO_R0 = 0,
+   SH64_DEBUG_INFO_TR0 = 68,
+   SH64_DEBUG_INFO_FR0 = 77,
+   SH64_DEBUG_INFO_T_C = 19,
+   SH64_DEBUG_INFO_XF0_C = SH64_DEBUG_INFO_FR0 + 16,
+   SH64_DEBUG_INFO_FPUL_C = SH64_DEBUG_INFO_FR0 + 32,
+   SH64_DEBUG_INFO_R0_C = 141,
+   SH64_DEBUG_INFO_GBR_C = 157,
+   SH64_DEBUG_INFO_MACH_C_BIG, SH64_DEBUG_INFO_MACL_C,
+   SH64_DEBUG_INFO_MACH_C_LITTLE,
+   SH64_DEBUG_INFO_PR_C, SH_DEBUG_INFO_FPSCR_C
+ };
  #endif

Re: SH5 compact register numbering in gcc -> gdb interface - include/elf/sh.h ?

[Elena Zannoni]

Joern Rennecke writes:
 > To give gcc and gdb a common interface, it is best put into a header file that
 > but
 > gdb/sh-tdep and gcc/config/sh/sh.h (can) include.
 > 
 > I thought of putting it into include/elg/sh.h, since elf is now the predominant
 > object format for SH gcc.  Or should we start something like an include/dwarf
 > directory?
 > But then, it's not strictly dwarf either, since these register numbers are
 > also used for stabs debugging info (in the SH1..SH4 coff toolchain, or if
 > you ask specifically for stabs.)
 > 

I think include/gcc-sh64.h or include/gdb-sh64.h could be OK. Would match the
include/sim-sh64.h file.


 > --- ../include/elf/sh.h	Thu May  9 22:22:18 2002
 > *************** START_RELOC_NUMBERS (elf_sh_reloc_type)
 > *** 218,221 ****
 > --- 218,247 ----
 >     RELOC_NUMBER (R_SH_64_PCREL, 255)
 >   END_RELOC_NUMBERS (R_SH_max)
 >   
 > + enum
 > + {
 > +   SH_DEBUG_INFO_R0 = 0,
 > +   SH_DEBUG_INFO_PR = 17,
 > +   SH_DEBUG_INFO_GBR = 18,
 > +   SH_DEBUG_INFO_MACH_BIG = 20, SH_DEBUG_INFO_MACL, SH_DEBUG_INFO_MACH_LITTLE,

This will break gdb. Register 22 ir SR. What are these registers?
Doesn't SH have only mach and macl?

 > +   SH_DEBUG_INFO_FPUL = 23,
 > +   SH_DEBUG_INFO_FPSCR = 24,
 > +   SH_DEBUG_INFO_FR0 = 25,
 > +   SH_DEBUG_INFO_XD0 = 87
 > + }
 > + 
 > + enum
 > + {
 > +   SH64_DEBUG_INFO_R0 = 0,
 > +   SH64_DEBUG_INFO_TR0 = 68,
 > +   SH64_DEBUG_INFO_FR0 = 77,
 > +   SH64_DEBUG_INFO_T_C = 19,
 > +   SH64_DEBUG_INFO_XF0_C = SH64_DEBUG_INFO_FR0 + 16,
 > +   SH64_DEBUG_INFO_FPUL_C = SH64_DEBUG_INFO_FR0 + 32,
 > +   SH64_DEBUG_INFO_R0_C = 141,
 > +   SH64_DEBUG_INFO_GBR_C = 157,
 > +   SH64_DEBUG_INFO_MACH_C_BIG, SH64_DEBUG_INFO_MACL_C,
 > +   SH64_DEBUG_INFO_MACH_C_LITTLE,
 > +   SH64_DEBUG_INFO_PR_C, SH_DEBUG_INFO_FPSCR_C
 > + };
 >   #endif

What is the advantage of reusing media numbers for compact registers?
This also wouldn't work with the current code, because it is assumed
that the register sets are disjoint. I see that you have made disjoint
the GPRs and that is OK because it will fix some bugs. Might as well
make the whole set distinct. Same question as above about the mach/macl
registers applies here.
Can you expand a bit on that?

thanks
Elena

Re: SH5 compact register numbering in gcc -> gdb interface - include/elf/sh.h ?

[Andrew Cagney]

> I think include/gcc-sh64.h or include/gdb-sh64.h could be OK. Would match the
> include/sim-sh64.h file.

BTW, GDB has started moving the include/sim-*.h files into 
include/gdb/sim-*.h, but otherwise, yes.

Andrew

Re: SH5 compact register numbering in gcc -> gdb interface - include/elf/sh.h ?

[Joern Rennecke]

ezannoni@redhat.com wrote:
> 
> Joern Rennecke writes:
>  > To give gcc and gdb a common interface, it is best put into a header file that
>  > but
>  > gdb/sh-tdep and gcc/config/sh/sh.h (can) include.
>  >
>  > I thought of putting it into include/elg/sh.h, since elf is now the predominant
>  > object format for SH gcc.  Or should we start something like an include/dwarf
>  > directory?
>  > But then, it's not strictly dwarf either, since these register numbers are
>  > also used for stabs debugging info (in the SH1..SH4 coff toolchain, or if
>  > you ask specifically for stabs.)
>  >
> 
> I think include/gcc-sh64.h or include/gdb-sh64.h could be OK. Would match the
> include/sim-sh64.h file.
> 
>  > --- ../include/elf/sh.h      Thu May  9 22:22:18 2002
>  > *************** START_RELOC_NUMBERS (elf_sh_reloc_type)
>  > *** 218,221 ****
>  > --- 218,247 ----
>  >     RELOC_NUMBER (R_SH_64_PCREL, 255)
>  >   END_RELOC_NUMBERS (R_SH_max)
>  >
>  > + enum
>  > + {
>  > +   SH_DEBUG_INFO_R0 = 0,
>  > +   SH_DEBUG_INFO_PR = 17,
>  > +   SH_DEBUG_INFO_GBR = 18,
>  > +   SH_DEBUG_INFO_MACH_BIG = 20, SH_DEBUG_INFO_MACL, SH_DEBUG_INFO_MACH_LITTLE,
> 
> This will break gdb. Register 22 ir SR. What are these registers?

gcc does not emit debug information for SR - if it was encountered in
DBX_REGISTER_NUMBER, the compiler would abort.  So we don't actually have a
number
allocated in the interface right now, and if we need one, we are free to choose
any.

> Doesn't SH have only mach and macl?

Yes, it has only mach and macl.  But you could hold a 64 bit value in this
register
pair, in which case MACH always holds the high part and MACL holds the low part.
So the idea is to use SH_DEBUG_INFO_MACH_BIG for big endian, and
SH_DEBUG_INFO_MACH_LITTLE for little endian.  This way, it is clear where low
and high
part are.  both SH_DEBUG_INFO_MACH_BIG and SH_DEBUG_INFO_MACH_LITTLE are then
mapped
to gdb's MACH.  Note that SH_DEBUG_INFO_MACH_BIG is the old MACH number, and
SH_DEBUG_INFO_MACL is the old MACL number, so we have full backwards
compatibility.
Having both this backwards compatibility and the ability to represent a 64 bit
value
in MACH/MACL for little endian was the point of using 22 for
SH_DEBUG_INFO_MACH_LITTLE.

>  > +   SH64_DEBUG_INFO_R0 = 0,
>  > +   SH64_DEBUG_INFO_TR0 = 68,
>  > +   SH64_DEBUG_INFO_FR0 = 77,
>  > +   SH64_DEBUG_INFO_T_C = 19,
>  > +   SH64_DEBUG_INFO_XF0_C = SH64_DEBUG_INFO_FR0 + 16,
>  > +   SH64_DEBUG_INFO_FPUL_C = SH64_DEBUG_INFO_FR0 + 32,
>  > +   SH64_DEBUG_INFO_R0_C = 141,
>  > +   SH64_DEBUG_INFO_GBR_C = 157,
>  > +   SH64_DEBUG_INFO_MACH_C_BIG, SH64_DEBUG_INFO_MACL_C,
>  > +   SH64_DEBUG_INFO_MACH_C_LITTLE,
>  > +   SH64_DEBUG_INFO_PR_C, SH_DEBUG_INFO_FPSCR_C
>  > + };
>  >   #endif
> 
> What is the advantage of reusing media numbers for compact registers?

The numbers are reused where the registers are actually identical.  Thus,
there is actually less work for gcc and gdb to encode and decode these
registers.

> This also wouldn't work with the current code, because it is assumed
> that the register sets are disjoint. I see that you have made disjoint

I don't know what you need disjoint registers for, when the size and
location of the register is the same in either mode.  What part of the
code makes assumptions about further disjointness?
	
-- 
--------------------------
SuperH
2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
T:+44 1454 462330

Re: SH5 compact register numbering in gcc -> gdb interface - include/elf/sh.h ?

[Joern Rennecke]

ezannoni@redhat.com wrote:
> What is the advantage of reusing media numbers for compact registers?

P.S.: a further - and maybe actually more important - advantage is that
the debug information is compacter, since register numbers < 128 can be
expressed with a single byte.
	
-- 
--------------------------
SuperH
2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
T:+44 1454 462330

Re: SH5 compact register numbering in gcc -> gdb interface - include/elf/sh.h ?

[Joern Rennecke]

ezannoni@redhat.com:
> > I think include/gcc-sh64.h or include/gdb-sh64.h could be OK. Would match the
> > include/sim-sh64.h file.

Since we are going to have a file that describes both the SH1-4 and SH64 stuff,
I think it makes more sense to just say gdb-sh.h

ac131313@cygnus.com wrote:
> BTW, GDB has started moving the include/sim-*.h files into
> include/gdb/sim-*.h, but otherwise, yes.

Ok, gdb/gdb-sh.h then.
	
-- 
--------------------------
SuperH
2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
T:+44 1454 462330

Re: SH simulator register numbers: include/gdb/sim-sh.h

[Joern Rennecke]

[-- Attachment #1: Type: text/plain, Size: 532 bytes --]

> BTW, GDB has started moving the include/sim-*.h files into
> include/gdb/sim-*.h, but otherwise, yes.

Right, so the simulator interface would go into include/gdb/sim-sh.h .

Fri May 10 14:58:33 2002  J"orn Rennecke <joern.rennecke@superh.com>

        * sim-sh.h: New file, from include/sim-sh64.h.  Added
        SH1-SH4 / SH-DSP register numbers, moved SH5 register numbers,
        added full set of control registers.

-- 
--------------------------
SuperH
2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
T:+44 1454 462330

[-- Attachment #2: sim-sh.h --]
[-- Type: text/plain, Size: 4826 bytes --]

/* This file defines the interface between the sh64 simulator and gdb.
   Copyright (C) 2000, 2002 Free Software Foundation, Inc.

This file is part of GDB.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#if !defined (SIM_SH_H)
#define SIM_SH_H

#ifdef __cplusplus
extern "C" { // }
#endif

/* The simulator makes use of the following register information. */

enum
  {
    SIM_SH_R0_REGNUM = 0, SIM_SH_R1_REGNUM, SIM_SH_R2_REGNUM, SIM_SH_R3_REGNUM,
    SIM_SH_R4_REGNUM, SIM_SH_R5_REGNUM, SIM_SH_R6_REGNUM, SIM_SH_R7_REGNUM,
    SIM_SH_R8_REGNUM, SIM_SH_R9_REGNUM, SIM_SH_R10_REGNUM, SIM_SH_R11_REGNUM,
    SIM_SH_R12_REGNUM, SIM_SH_R13_REGNUM, SIM_SH_R14_REGNUM, SIM_SH_R15_REGNUM,
    SIM_SH_PC_REGNUM, SIM_SH_PR_REGNUM,
    SIM_SH_GBR_REGNUM, SIM_SH_VBR_REGNUM,
    SIM_SH_MACH_REGNUM, SIM_SH_MACL_REGNUM, SIM_SH_SR_REGNUM,
    SIM_SH_FPUL_REGNUM, SIM_SH_FPSCR_REGNUM,
    SIM_SH_FR0_REGNUM = 25, /* sh3e / sh4 */
    /* sh[3]-dsp */
    SIM_SH_DSR_REGNUM = 24,
    SIM_SH_A0G_REGNUM, SIM_SH_A0_REGNUM,
    SIM_SH_A1G_REGNUM, SIM_SH_A1_REGNUM,
    SIM_SH_M0_REGNUM, SIM_SH_M1_REGNUM,
    SIM_SH_X0_REGNUM, SIM_SH_X1_REGNUM,
    SIM_SH_Y0_REGNUM, SIM_SH_Y1_REGNUM,
    SIM_SH_MOD_REGNUM = 40,
    SIM_SH_SSR_REGNUM = 41, SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */
    SIM_SH_RS_REGNUM = 43, SIM_SH_RE_REGNUM, /* sh[3]-dsp */
    SIM_SH_R0_BANK0_REGNUM = 43, SIM_SH_R7_BANK0_REGNUM = 50, /* sh3[e] / sh4 */
    SIM_SH_R0_BANK1_REGNUM = 51, SIM_SH_R7_BANK1_REGNUM = 58, /* sh3[e] / sh4 */
    SIM_SH_R0_BANK_REGNUM = 51, SIM_SH_R7_BANK_REGNUM = 58, /* sh[3]-dsp */
    SIM_SH_XF0_REGNUM = 59,
    SIM_SH_SGR_REGNUM = 75,
    SIM_SH_DBR_REGNUM = 76,
    SIM_SH4_NUM_REGS,
    /* 77..127: room for expansion.  */
  

    SIM_SH64_R0_REGNUM = 128,
    SIM_SH64_SP_REGNUM   = SIM_SH64_R0_REGNUM+15,
    SIM_SH64_PC_REGNUM   = SIM_SH64_R0_REGNUM+64,
    /* 64 64-bit control registers */
    SIM_SH64_CR0_REGNUM  = SIM_SH64_R0_REGNUM+65,
    SIM_SH64_SR_REGNUM   = SIM_SH64_CR0_REGNUM,    /* Status reg            */
    SIM_SH64_SSR_REGNUM  = SIM_SH64_CR0_REGNUM+1,  /* Saved status reg      */
    SIM_SH64_PSSR_REGNUM = SIM_SH64_CR0_REGNUM+2,  /* Panic-saved status reg*/
    SIM_SH64_INTEVT_REGNUM=SIM_SH64_CR0_REGNUM+4,  /* Interrupt event reg   */
    SIM_SH64_EXPEVT_REGNUM=SIM_SH64_CR0_REGNUM+5,  /* Exception event reg   */
    SIM_SH64_PEXPEVT_REGNUM= SIM_SH64_CR0_REGNUM+6,/* Panic-saved Exception
								  event reg */
    SIM_SH64_TRA_REGNUM  = SIM_SH64_CR0_REGNUM+7,  /* TRAP exception reg    */
    SIM_SH64_SPC_REGNUM  = SIM_SH64_CR0_REGNUM+8,  /* Saved program counter */
    SIM_SH64_PSPC_REGNUM = SIM_SH64_CR0_REGNUM+9,  /* Panic-saved program
								    counter */
    SIM_SH64_RESVEC_REGNUM=SIM_SH64_CR0_REGNUM+10, /* Reset vector          */
    SIM_SH64_VBR_REGNUM  = SIM_SH64_CR0_REGNUM+11, /* Vector base register  */
    SIM_SH64_TEA_REGNUM  = SIM_SH64_CR0_REGNUM+13, /* Faulting effective
							   address register */
    SIM_SH64_DCR_REGNUM  = SIM_SH64_CR0_REGNUM+16, /* Debug control reg     */
    SIM_SH64_KCR0_REGNUM = SIM_SH64_CR0_REGNUM+17, /* Kernel register 0     */
    SIM_SH64_KCR1_REGNUM = SIM_SH64_CR0_REGNUM+18, /* Kernel register 1     */
    SIM_SH64_CTC_REGNUM  = SIM_SH64_CR0_REGNUM+62, /* Clock tick counter    */
    SIM_SH64_USR_REGNUM  = SIM_SH64_CR0_REGNUM+63, /* User-accessible
							    status register */
    SIM_SH64_CR63_REGNUM = SIM_SH64_R0_REGNUM+128,
    SIM_SH64_TR0_REGNUM  = SIM_SH64_R0_REGNUM+129,
    SIM_SH64_FPSCR_REGNUM= SIM_SH64_R0_REGNUM+137,
    SIM_SH64_FR0_REGNUM  = SIM_SH64_R0_REGNUM+138
  };

enum
  {
    SIM_SH64_NUM_REGS = 202,  /* total number of architectural registers */
    SIM_SH64_NR_R_REGS = 64, /* number of general registers */
    SIM_SH64_NR_TR_REGS = 8, /* number of target registers */
    SIM_SH64_NR_FP_REGS = 64, /* number of floating point registers */

    SIM_SH64_FPSCR_OFFSET = (SIM_SH64_FPSCR_REGNUM - SIM_SH64_R0_REGNUM) * 8,
    SIM_SH64_FR0_OFFSET = (SIM_SH64_FPSCR_REGNUM - SIM_SH64_R0_REGNUM) * 8 + 4
  };

enum
  {
    SIM_SH4_REG_BYTES = SIM_SH4_NUM_REGS * 4,
    SIM_SH64_REG_BYTES = SIM_SH64_NUM_REGS * 8 - (SIM_SH64_NR_FP_REGS + 1) * 4
  };

#ifdef __cplusplus
}
#endif

#endif

Re: SH5 compact register numbering in gcc -> gdb interface - include/elf/sh.h ?

[Andrew Cagney]

>  + enum
>>  > + {
>>  > +   SH_DEBUG_INFO_R0 = 0,
>>  > +   SH_DEBUG_INFO_PR = 17,
>>  > +   SH_DEBUG_INFO_GBR = 18,
>>  > +   SH_DEBUG_INFO_MACH_BIG = 20, SH_DEBUG_INFO_MACL, SH_DEBUG_INFO_MACH_LITTLE,
>> 
>> This will break gdb. Register 22 ir SR. What are these registers?
> 
> 
> gcc does not emit debug information for SR - if it was encountered in
> DBX_REGISTER_NUMBER, the compiler would abort.  So we don't actually have a
> number
> allocated in the interface right now, and if we need one, we are free to choose
> any.
> 
> 
>> Doesn't SH have only mach and macl?
> 
> 
> Yes, it has only mach and macl.  But you could hold a 64 bit value in this
> register
> pair, in which case MACH always holds the high part and MACL holds the low part.
> So the idea is to use SH_DEBUG_INFO_MACH_BIG for big endian, and
> SH_DEBUG_INFO_MACH_LITTLE for little endian.  This way, it is clear where low
> and high
> part are.  both SH_DEBUG_INFO_MACH_BIG and SH_DEBUG_INFO_MACH_LITTLE are then
> mapped
> to gdb's MACH.  Note that SH_DEBUG_INFO_MACH_BIG is the old MACH number, and
> SH_DEBUG_INFO_MACL is the old MACL number, so we have full backwards
> compatibility.
> Having both this backwards compatibility and the ability to represent a 64 bit
> value
> in MACH/MACL for little endian was the point of using 22 for
> SH_DEBUG_INFO_MACH_LITTLE.

The correct way to represent a 64 bit value in MACH and MACL is to emit 
a location expression indicating that the value is split across the 
MACL/MACH registers.  GDB currently only handles the simple case of this 
(but hey that is just a bug).  If GCC can't emit this info correctly in 
all cases then I guess GCC also has a bug and that bug also needs to be 
fixed.

enjoy,
Andrew

Re: SH5 compact register numbering in gcc -> gdb interface - include/elf/sh.h ?

[Andrew Cagney]

> 
> Ok, gdb/gdb-sh.h then.

No. This isn't a GDB interface but rather a GCC interface.  gdb/gcc-sh.h 
is one option.

Andrew

Re: SH5 compact register numbering in gcc -> gdb interface - include/elf/sh.h ?

[Joern Rennecke]

ac131313@cygnus.com wrote:
> The correct way to represent a 64 bit value in MACH and MACL is to emit
> a location expression indicating that the value is split across the
> MACL/MACH registers.  GDB currently only handles the simple case of this
> (but hey that is just a bug).  If GCC can't emit this info correctly in
> all cases then I guess GCC also has a bug and that bug also needs to be
> fixed.

Ok, so we don't need the MACH_LITTLE assignments, nabd make MACH_BIG into MACH
again.  That't leave a gap at 22 for the time being, whereas
SH64_DEBUG_INFO_PR_C and SH_DEBUG_INFO_FPSCR_C will follow immediately after
SH64_DEBUG_INFO_MACL_C .

-- 
--------------------------
SuperH
2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
T:+44 1454 462330

Re: SH5 compact register numbering in gcc -> gdb interface - include/elf/sh.h ?

[Joern Rennecke]

ac131313@cygnus.com wrote:
> 
> >
> > Ok, gdb/gdb-sh.h then.
> 
> No. This isn't a GDB interface but rather a GCC interface.  gdb/gcc-sh.h
> is one option.

Well, it is both a gcc and a gdb interface, but include/gdb/gcc-sh.h is
fine with me.  The pathname then refers to both of the programs being 
interfaced.
	
-- 
--------------------------
SuperH
2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
T:+44 1454 462330

Unreviewed patch: add include/gdb/sim-sh.h (Was: Re: SH simulator register numbers: include/gdb/sim-sh.h)

[Joern Rennecke]

Joern Rennecke wrote:
> 
> > BTW, GDB has started moving the include/sim-*.h files into
> > include/gdb/sim-*.h, but otherwise, yes.
> 
> Right, so the simulator interface would go into include/gdb/sim-sh.h .
> 
> Fri May 10 14:58:33 2002  J"orn Rennecke <joern.rennecke@superh.com>
> 
>         * sim-sh.h: New file, from include/sim-sh64.h.  Added
>         SH1-SH4 / SH-DSP register numbers, moved SH5 register numbers,
>         added full set of control registers.
> 
> --
> --------------------------
> SuperH
> 2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
> T:+44 1454 462330
> 
>   --------------------------------------------------------------------------------
> /* This file defines the interface between the sh64 simulator and gdb.
>    Copyright (C) 2000, 2002 Free Software Foundation, Inc.
> 
> This file is part of GDB.
> 
> This program is free software; you can redistribute it and/or modify
> it under the terms of the GNU General Public License as published by
> the Free Software Foundation; either version 2 of the License, or
> (at your option) any later version.
> 
> This program is distributed in the hope that it will be useful,
> but WITHOUT ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> GNU General Public License for more details.
> 
> You should have received a copy of the GNU General Public License
> along with this program; if not, write to the Free Software
> Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
> 
> #if !defined (SIM_SH_H)
> #define SIM_SH_H
> 
> #ifdef __cplusplus
> extern "C" { // }
> #endif
> 
> /* The simulator makes use of the following register information. */
> 
> enum
>   {
>     SIM_SH_R0_REGNUM = 0, SIM_SH_R1_REGNUM, SIM_SH_R2_REGNUM, SIM_SH_R3_REGNUM,
>     SIM_SH_R4_REGNUM, SIM_SH_R5_REGNUM, SIM_SH_R6_REGNUM, SIM_SH_R7_REGNUM,
>     SIM_SH_R8_REGNUM, SIM_SH_R9_REGNUM, SIM_SH_R10_REGNUM, SIM_SH_R11_REGNUM,
>     SIM_SH_R12_REGNUM, SIM_SH_R13_REGNUM, SIM_SH_R14_REGNUM, SIM_SH_R15_REGNUM,
>     SIM_SH_PC_REGNUM, SIM_SH_PR_REGNUM,
>     SIM_SH_GBR_REGNUM, SIM_SH_VBR_REGNUM,
>     SIM_SH_MACH_REGNUM, SIM_SH_MACL_REGNUM, SIM_SH_SR_REGNUM,
>     SIM_SH_FPUL_REGNUM, SIM_SH_FPSCR_REGNUM,
>     SIM_SH_FR0_REGNUM = 25, /* sh3e / sh4 */
>     /* sh[3]-dsp */
>     SIM_SH_DSR_REGNUM = 24,
>     SIM_SH_A0G_REGNUM, SIM_SH_A0_REGNUM,
>     SIM_SH_A1G_REGNUM, SIM_SH_A1_REGNUM,
>     SIM_SH_M0_REGNUM, SIM_SH_M1_REGNUM,
>     SIM_SH_X0_REGNUM, SIM_SH_X1_REGNUM,
>     SIM_SH_Y0_REGNUM, SIM_SH_Y1_REGNUM,
>     SIM_SH_MOD_REGNUM = 40,
>     SIM_SH_SSR_REGNUM = 41, SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */
>     SIM_SH_RS_REGNUM = 43, SIM_SH_RE_REGNUM, /* sh[3]-dsp */
>     SIM_SH_R0_BANK0_REGNUM = 43, SIM_SH_R7_BANK0_REGNUM = 50, /* sh3[e] / sh4 */
>     SIM_SH_R0_BANK1_REGNUM = 51, SIM_SH_R7_BANK1_REGNUM = 58, /* sh3[e] / sh4 */
>     SIM_SH_R0_BANK_REGNUM = 51, SIM_SH_R7_BANK_REGNUM = 58, /* sh[3]-dsp */
>     SIM_SH_XF0_REGNUM = 59,
>     SIM_SH_SGR_REGNUM = 75,
>     SIM_SH_DBR_REGNUM = 76,
>     SIM_SH4_NUM_REGS,
>     /* 77..127: room for expansion.  */
> 
> 
>     SIM_SH64_R0_REGNUM = 128,
>     SIM_SH64_SP_REGNUM   = SIM_SH64_R0_REGNUM+15,
>     SIM_SH64_PC_REGNUM   = SIM_SH64_R0_REGNUM+64,
>     /* 64 64-bit control registers */
>     SIM_SH64_CR0_REGNUM  = SIM_SH64_R0_REGNUM+65,
>     SIM_SH64_SR_REGNUM   = SIM_SH64_CR0_REGNUM,    /* Status reg            */
>     SIM_SH64_SSR_REGNUM  = SIM_SH64_CR0_REGNUM+1,  /* Saved status reg      */
>     SIM_SH64_PSSR_REGNUM = SIM_SH64_CR0_REGNUM+2,  /* Panic-saved status reg*/
>     SIM_SH64_INTEVT_REGNUM=SIM_SH64_CR0_REGNUM+4,  /* Interrupt event reg   */
>     SIM_SH64_EXPEVT_REGNUM=SIM_SH64_CR0_REGNUM+5,  /* Exception event reg   */
>     SIM_SH64_PEXPEVT_REGNUM= SIM_SH64_CR0_REGNUM+6,/* Panic-saved Exception
>                                                                   event reg */
>     SIM_SH64_TRA_REGNUM  = SIM_SH64_CR0_REGNUM+7,  /* TRAP exception reg    */
>     SIM_SH64_SPC_REGNUM  = SIM_SH64_CR0_REGNUM+8,  /* Saved program counter */
>     SIM_SH64_PSPC_REGNUM = SIM_SH64_CR0_REGNUM+9,  /* Panic-saved program
>                                                                     counter */
>     SIM_SH64_RESVEC_REGNUM=SIM_SH64_CR0_REGNUM+10, /* Reset vector          */
>     SIM_SH64_VBR_REGNUM  = SIM_SH64_CR0_REGNUM+11, /* Vector base register  */
>     SIM_SH64_TEA_REGNUM  = SIM_SH64_CR0_REGNUM+13, /* Faulting effective
>                                                            address register */
>     SIM_SH64_DCR_REGNUM  = SIM_SH64_CR0_REGNUM+16, /* Debug control reg     */
>     SIM_SH64_KCR0_REGNUM = SIM_SH64_CR0_REGNUM+17, /* Kernel register 0     */
>     SIM_SH64_KCR1_REGNUM = SIM_SH64_CR0_REGNUM+18, /* Kernel register 1     */
>     SIM_SH64_CTC_REGNUM  = SIM_SH64_CR0_REGNUM+62, /* Clock tick counter    */
>     SIM_SH64_USR_REGNUM  = SIM_SH64_CR0_REGNUM+63, /* User-accessible
>                                                             status register */
>     SIM_SH64_CR63_REGNUM = SIM_SH64_R0_REGNUM+128,
>     SIM_SH64_TR0_REGNUM  = SIM_SH64_R0_REGNUM+129,
>     SIM_SH64_FPSCR_REGNUM= SIM_SH64_R0_REGNUM+137,
>     SIM_SH64_FR0_REGNUM  = SIM_SH64_R0_REGNUM+138
>   };
> 
> enum
>   {
>     SIM_SH64_NUM_REGS = 202,  /* total number of architectural registers */
>     SIM_SH64_NR_R_REGS = 64, /* number of general registers */
>     SIM_SH64_NR_TR_REGS = 8, /* number of target registers */
>     SIM_SH64_NR_FP_REGS = 64, /* number of floating point registers */
> 
>     SIM_SH64_FPSCR_OFFSET = (SIM_SH64_FPSCR_REGNUM - SIM_SH64_R0_REGNUM) * 8,
>     SIM_SH64_FR0_OFFSET = (SIM_SH64_FPSCR_REGNUM - SIM_SH64_R0_REGNUM) * 8 + 4
>   };
> 
> enum
>   {
>     SIM_SH4_REG_BYTES = SIM_SH4_NUM_REGS * 4,
>     SIM_SH64_REG_BYTES = SIM_SH64_NUM_REGS * 8 - (SIM_SH64_NR_FP_REGS + 1) * 4
>   };
> 
> #ifdef __cplusplus
> }
> #endif
> 
> #endif

-- 
--------------------------
SuperH
2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
T:+44 1454 462330

Re: Unreviewed patch: add include/gdb/sim-sh.h (Was: Re: SH simulator register numbers: include/gdb/sim-sh.h)

[Elena Zannoni]

Sorry.
Can you format the file with one register per line?
Take a look at sim-d10v.h, now that Andrew cleaned it up.

I am not sure that leaving holes in the register numbers is a good idea.

Does this work with gdb as it is now?

Elena


Joern Rennecke writes:
 > Joern Rennecke wrote:
 > > 
 > > > BTW, GDB has started moving the include/sim-*.h files into
 > > > include/gdb/sim-*.h, but otherwise, yes.
 > > 
 > > Right, so the simulator interface would go into include/gdb/sim-sh.h .
 > > 
 > > Fri May 10 14:58:33 2002  J"orn Rennecke <joern.rennecke@superh.com>
 > > 
 > >         * sim-sh.h: New file, from include/sim-sh64.h.  Added
 > >         SH1-SH4 / SH-DSP register numbers, moved SH5 register numbers,
 > >         added full set of control registers.
 > > 
 > > --
 > > --------------------------
 > > SuperH
 > > 2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
 > > T:+44 1454 462330
 > > 
 > >   --------------------------------------------------------------------------------
 > > /* This file defines the interface between the sh64 simulator and gdb.
 > >    Copyright (C) 2000, 2002 Free Software Foundation, Inc.
 > > 
 > > This file is part of GDB.
 > > 
 > > This program is free software; you can redistribute it and/or modify
 > > it under the terms of the GNU General Public License as published by
 > > the Free Software Foundation; either version 2 of the License, or
 > > (at your option) any later version.
 > > 
 > > This program is distributed in the hope that it will be useful,
 > > but WITHOUT ANY WARRANTY; without even the implied warranty of
 > > MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 > > GNU General Public License for more details.
 > > 
 > > You should have received a copy of the GNU General Public License
 > > along with this program; if not, write to the Free Software
 > > Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 > > 
 > > #if !defined (SIM_SH_H)
 > > #define SIM_SH_H
 > > 
 > > #ifdef __cplusplus
 > > extern "C" { // }
 > > #endif
 > > 
 > > /* The simulator makes use of the following register information. */
 > > 
 > > enum
 > >   {
 > >     SIM_SH_R0_REGNUM = 0, SIM_SH_R1_REGNUM, SIM_SH_R2_REGNUM, SIM_SH_R3_REGNUM,
 > >     SIM_SH_R4_REGNUM, SIM_SH_R5_REGNUM, SIM_SH_R6_REGNUM, SIM_SH_R7_REGNUM,
 > >     SIM_SH_R8_REGNUM, SIM_SH_R9_REGNUM, SIM_SH_R10_REGNUM, SIM_SH_R11_REGNUM,
 > >     SIM_SH_R12_REGNUM, SIM_SH_R13_REGNUM, SIM_SH_R14_REGNUM, SIM_SH_R15_REGNUM,
 > >     SIM_SH_PC_REGNUM, SIM_SH_PR_REGNUM,
 > >     SIM_SH_GBR_REGNUM, SIM_SH_VBR_REGNUM,
 > >     SIM_SH_MACH_REGNUM, SIM_SH_MACL_REGNUM, SIM_SH_SR_REGNUM,
 > >     SIM_SH_FPUL_REGNUM, SIM_SH_FPSCR_REGNUM,
 > >     SIM_SH_FR0_REGNUM = 25, /* sh3e / sh4 */
 > >     /* sh[3]-dsp */
 > >     SIM_SH_DSR_REGNUM = 24,
 > >     SIM_SH_A0G_REGNUM, SIM_SH_A0_REGNUM,
 > >     SIM_SH_A1G_REGNUM, SIM_SH_A1_REGNUM,
 > >     SIM_SH_M0_REGNUM, SIM_SH_M1_REGNUM,
 > >     SIM_SH_X0_REGNUM, SIM_SH_X1_REGNUM,
 > >     SIM_SH_Y0_REGNUM, SIM_SH_Y1_REGNUM,
 > >     SIM_SH_MOD_REGNUM = 40,
 > >     SIM_SH_SSR_REGNUM = 41, SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */
 > >     SIM_SH_RS_REGNUM = 43, SIM_SH_RE_REGNUM, /* sh[3]-dsp */
 > >     SIM_SH_R0_BANK0_REGNUM = 43, SIM_SH_R7_BANK0_REGNUM = 50, /* sh3[e] / sh4 */
 > >     SIM_SH_R0_BANK1_REGNUM = 51, SIM_SH_R7_BANK1_REGNUM = 58, /* sh3[e] / sh4 */
 > >     SIM_SH_R0_BANK_REGNUM = 51, SIM_SH_R7_BANK_REGNUM = 58, /* sh[3]-dsp */
 > >     SIM_SH_XF0_REGNUM = 59,
 > >     SIM_SH_SGR_REGNUM = 75,
 > >     SIM_SH_DBR_REGNUM = 76,
 > >     SIM_SH4_NUM_REGS,
 > >     /* 77..127: room for expansion.  */
 > > 
 > > 
 > >     SIM_SH64_R0_REGNUM = 128,
 > >     SIM_SH64_SP_REGNUM   = SIM_SH64_R0_REGNUM+15,
 > >     SIM_SH64_PC_REGNUM   = SIM_SH64_R0_REGNUM+64,
 > >     /* 64 64-bit control registers */
 > >     SIM_SH64_CR0_REGNUM  = SIM_SH64_R0_REGNUM+65,
 > >     SIM_SH64_SR_REGNUM   = SIM_SH64_CR0_REGNUM,    /* Status reg            */
 > >     SIM_SH64_SSR_REGNUM  = SIM_SH64_CR0_REGNUM+1,  /* Saved status reg      */
 > >     SIM_SH64_PSSR_REGNUM = SIM_SH64_CR0_REGNUM+2,  /* Panic-saved status reg*/
 > >     SIM_SH64_INTEVT_REGNUM=SIM_SH64_CR0_REGNUM+4,  /* Interrupt event reg   */
 > >     SIM_SH64_EXPEVT_REGNUM=SIM_SH64_CR0_REGNUM+5,  /* Exception event reg   */
 > >     SIM_SH64_PEXPEVT_REGNUM= SIM_SH64_CR0_REGNUM+6,/* Panic-saved Exception
 > >                                                                   event reg */
 > >     SIM_SH64_TRA_REGNUM  = SIM_SH64_CR0_REGNUM+7,  /* TRAP exception reg    */
 > >     SIM_SH64_SPC_REGNUM  = SIM_SH64_CR0_REGNUM+8,  /* Saved program counter */
 > >     SIM_SH64_PSPC_REGNUM = SIM_SH64_CR0_REGNUM+9,  /* Panic-saved program
 > >                                                                     counter */
 > >     SIM_SH64_RESVEC_REGNUM=SIM_SH64_CR0_REGNUM+10, /* Reset vector          */
 > >     SIM_SH64_VBR_REGNUM  = SIM_SH64_CR0_REGNUM+11, /* Vector base register  */
 > >     SIM_SH64_TEA_REGNUM  = SIM_SH64_CR0_REGNUM+13, /* Faulting effective
 > >                                                            address register */
 > >     SIM_SH64_DCR_REGNUM  = SIM_SH64_CR0_REGNUM+16, /* Debug control reg     */
 > >     SIM_SH64_KCR0_REGNUM = SIM_SH64_CR0_REGNUM+17, /* Kernel register 0     */
 > >     SIM_SH64_KCR1_REGNUM = SIM_SH64_CR0_REGNUM+18, /* Kernel register 1     */
 > >     SIM_SH64_CTC_REGNUM  = SIM_SH64_CR0_REGNUM+62, /* Clock tick counter    */
 > >     SIM_SH64_USR_REGNUM  = SIM_SH64_CR0_REGNUM+63, /* User-accessible
 > >                                                             status register */
 > >     SIM_SH64_CR63_REGNUM = SIM_SH64_R0_REGNUM+128,
 > >     SIM_SH64_TR0_REGNUM  = SIM_SH64_R0_REGNUM+129,
 > >     SIM_SH64_FPSCR_REGNUM= SIM_SH64_R0_REGNUM+137,
 > >     SIM_SH64_FR0_REGNUM  = SIM_SH64_R0_REGNUM+138
 > >   };
 > > 
 > > enum
 > >   {
 > >     SIM_SH64_NUM_REGS = 202,  /* total number of architectural registers */
 > >     SIM_SH64_NR_R_REGS = 64, /* number of general registers */
 > >     SIM_SH64_NR_TR_REGS = 8, /* number of target registers */
 > >     SIM_SH64_NR_FP_REGS = 64, /* number of floating point registers */
 > > 
 > >     SIM_SH64_FPSCR_OFFSET = (SIM_SH64_FPSCR_REGNUM - SIM_SH64_R0_REGNUM) * 8,
 > >     SIM_SH64_FR0_OFFSET = (SIM_SH64_FPSCR_REGNUM - SIM_SH64_R0_REGNUM) * 8 + 4
 > >   };
 > > 
 > > enum
 > >   {
 > >     SIM_SH4_REG_BYTES = SIM_SH4_NUM_REGS * 4,
 > >     SIM_SH64_REG_BYTES = SIM_SH64_NUM_REGS * 8 - (SIM_SH64_NR_FP_REGS + 1) * 4
 > >   };
 > > 
 > > #ifdef __cplusplus
 > > }
 > > #endif
 > > 
 > > #endif
 > 
 > -- 
 > --------------------------
 > SuperH
 > 2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
 > T:+44 1454 462330

Re: Unreviewed patch: add include/gdb/sim-sh.h (Was: Re: SH simulator register numbers: include/gdb/sim-sh.h)

[Joern Rennecke]

[-- Attachment #1: Type: text/plain, Size: 807 bytes --]

Elena Zannoni wrote:
> 
> Sorry.
> Can you format the file with one register per line?
> Take a look at sim-d10v.h, now that Andrew cleaned it up.

Ok.
	
> I am not sure that leaving holes in the register numbers is a good idea.

It's only leaving holes for specific subtargets that lack registers.
	
> Does this work with gdb as it is now?

Yes.  This is just putting the SH[1-4], sh-dsp, sh3e, sh3-dsp constants
in place and uses them, istead of literals.  I wanted to get this out of
the way before tackling the actual renumbering of the sh64 registers, to
cut down on the size of potentially controversial patches to review.

I have attached the updated patch set including the sim/sh patches.	
	
-- 
--------------------------
SuperH
2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
T:+44 1454 462330

[-- Attachment #2: sim-sh-patch --]
[-- Type: text/plain, Size: 17842 bytes --]

Wed Jun 12 13:20:51 2002  J"orn Rennecke <joern.rennecke@superh.com>

include/gdb:
	* sim-sh.h: Add enum constants for sh[1-4], sh3e, sh3?-dsp.
sim/sh:
	* Makefile (interp.o): Depend on $(srcroot)/include/gdb/sim-sh.h.
	* interp.c: Include "gdb/sim-sh.h".
	(sim_store_register, sim_fetch_register): Use constants defined there.

Index: include/gdb/sim-sh.h
===================================================================
RCS file: /cvs/src/src/include/gdb/sim-sh.h,v
retrieving revision 1.1
diff -p -r1.1 sim-sh.h
*** include/gdb/sim-sh.h	10 May 2002 22:53:56 -0000	1.1
--- include/gdb/sim-sh.h	12 Jun 2002 12:18:56 -0000
***************
*** 1,5 ****
  /* This file defines the interface between the sh simulator and gdb.
!    Copyright (C) 2002 Free Software Foundation, Inc.
  
  This file is part of GDB.
  
--- 1,5 ----
  /* This file defines the interface between the sh simulator and gdb.
!    Copyright (C) 2000, 2002 Free Software Foundation, Inc.
  
  This file is part of GDB.
  
*************** extern "C" { // }
*** 27,51 ****
  /* The simulator makes use of the following register information. */
  
  enum
!   {
!     SIM_SH64_R0_REGNUM = 0,
!     SIM_SH64_SP_REGNUM = 15,
!     SIM_SH64_PC_REGNUM = 64,
!     SIM_SH64_SR_REGNUM = 65,
!     SIM_SH64_SSR_REGNUM = 66,
!     SIM_SH64_SPC_REGNUM = 67,
!     SIM_SH64_TR0_REGNUM = 68,
!     SIM_SH64_FPCSR_REGNUM = 76,
!     SIM_SH64_FR0_REGNUM = 77
!   };
  
  enum
!   {
!     SIM_SH64_NR_REGS = 141,  /* total number of architectural registers */
!     SIM_SH64_NR_R_REGS = 64, /* number of general registers */
!     SIM_SH64_NR_TR_REGS = 8, /* number of target registers */
!     SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */
!   };
  
  #ifdef __cplusplus
  }
--- 27,158 ----
  /* The simulator makes use of the following register information. */
  
  enum
! {
!   SIM_SH_R0_REGNUM = 0,
!   SIM_SH_R1_REGNUM,
!   SIM_SH_R2_REGNUM,
!   SIM_SH_R3_REGNUM,
!   SIM_SH_R4_REGNUM,
!   SIM_SH_R5_REGNUM,
!   SIM_SH_R6_REGNUM,
!   SIM_SH_R7_REGNUM,
!   SIM_SH_R8_REGNUM,
!   SIM_SH_R9_REGNUM,
!   SIM_SH_R10_REGNUM,
!   SIM_SH_R11_REGNUM,
!   SIM_SH_R12_REGNUM,
!   SIM_SH_R13_REGNUM,
!   SIM_SH_R14_REGNUM,
!   SIM_SH_R15_REGNUM,
!   SIM_SH_PC_REGNUM,
!   SIM_SH_PR_REGNUM,
!   SIM_SH_GBR_REGNUM,
!   SIM_SH_VBR_REGNUM,
!   SIM_SH_MACH_REGNUM,
!   SIM_SH_MACL_REGNUM,
!   SIM_SH_SR_REGNUM,
!   SIM_SH_FPUL_REGNUM,
!   SIM_SH_FPSCR_REGNUM,
!   SIM_SH_FR0_REGNUM, /* FRn registers: sh3e / sh4 */
!   SIM_SH_FR1_REGNUM,
!   SIM_SH_FR2_REGNUM,
!   SIM_SH_FR3_REGNUM,
!   SIM_SH_FR4_REGNUM,
!   SIM_SH_FR5_REGNUM,
!   SIM_SH_FR6_REGNUM,
!   SIM_SH_FR7_REGNUM,
!   SIM_SH_FR8_REGNUM,
!   SIM_SH_FR9_REGNUM,
!   SIM_SH_FR10_REGNUM,
!   SIM_SH_FR11_REGNUM,
!   SIM_SH_FR12_REGNUM,
!   SIM_SH_FR13_REGNUM,
!   SIM_SH_FR14_REGNUM,
!   SIM_SH_FR15_REGNUM,
!   SIM_SH_SSR_REGNUM, /* sh3{,e,-dsp}, sh4 */
!   SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */
!   SIM_SH_R0_BANK0_REGNUM, /* SIM_SH_Rn_BANKm_REGNUM: sh3[e] / sh4 */
!   SIM_SH_R1_BANK0_REGNUM,
!   SIM_SH_R2_BANK0_REGNUM,
!   SIM_SH_R3_BANK0_REGNUM,
!   SIM_SH_R4_BANK0_REGNUM,
!   SIM_SH_R5_BANK0_REGNUM,
!   SIM_SH_R6_BANK0_REGNUM,
!   SIM_SH_R7_BANK0_REGNUM,
!   SIM_SH_R0_BANK1_REGNUM,
!   SIM_SH_R1_BANK1_REGNUM,
!   SIM_SH_R2_BANK1_REGNUM,
!   SIM_SH_R3_BANK1_REGNUM,
!   SIM_SH_R4_BANK1_REGNUM,
!   SIM_SH_R5_BANK1_REGNUM,
!   SIM_SH_R6_BANK1_REGNUM,
!   SIM_SH_R7_BANK1_REGNUM,
!   SIM_SH_XF0_REGNUM,
!   SIM_SH_XF1_REGNUM,
!   SIM_SH_XF2_REGNUM,
!   SIM_SH_XF3_REGNUM,
!   SIM_SH_XF4_REGNUM,
!   SIM_SH_XF5_REGNUM,
!   SIM_SH_XF6_REGNUM,
!   SIM_SH_XF7_REGNUM,
!   SIM_SH_XF8_REGNUM,
!   SIM_SH_XF9_REGNUM,
!   SIM_SH_XF10_REGNUM,
!   SIM_SH_XF11_REGNUM,
!   SIM_SH_XF12_REGNUM,
!   SIM_SH_XF13_REGNUM,
!   SIM_SH_XF14_REGNUM,
!   SIM_SH_XF15_REGNUM,
!   SIM_SH_SGR_REGNUM,
!   SIM_SH_DBR_REGNUM,
!   SIM_SH4_NUM_REGS
!   /* 77..127: room for expansion.  */
! };
!   
! /* sh[3]-dsp */
! enum
! {
!   SIM_SH_DSR_REGNUM = SIM_SH_FPSCR_REGNUM,
!   SIM_SH_A0G_REGNUM,
!   SIM_SH_A0_REGNUM,
!   SIM_SH_A1G_REGNUM,
!   SIM_SH_A1_REGNUM,
!   SIM_SH_M0_REGNUM,
!   SIM_SH_M1_REGNUM,
!   SIM_SH_X0_REGNUM,
!   SIM_SH_X1_REGNUM,
!   SIM_SH_Y0_REGNUM,
!   SIM_SH_Y1_REGNUM,
! 
!   SIM_SH_MOD_REGNUM = SIM_SH_FR15_REGNUM,
! 
!   SIM_SH_RS_REGNUM = SIM_SH_R0_BANK0_REGNUM,
!   SIM_SH_RE_REGNUM,
! 
!   SIM_SH_R0_BANK_REGNUM = SIM_SH_R0_BANK1_REGNUM,
!   SIM_SH_R7_BANK_REGNUM = SIM_SH_R7_BANK1_REGNUM
! };
! 
! enum
! {
!   SIM_SH64_R0_REGNUM = 0,
!   SIM_SH64_SP_REGNUM = 15,
!   SIM_SH64_PC_REGNUM = 64,
!   SIM_SH64_SR_REGNUM = 65,
!   SIM_SH64_SSR_REGNUM = 66,
!   SIM_SH64_SPC_REGNUM = 67,
!   SIM_SH64_TR0_REGNUM = 68,
!   SIM_SH64_FPCSR_REGNUM = 76,
!   SIM_SH64_FR0_REGNUM = 77
! };
  
  enum
! {
!   SIM_SH64_NR_REGS = 141,  /* total number of architectural registers */
!   SIM_SH64_NR_R_REGS = 64, /* number of general registers */
!   SIM_SH64_NR_TR_REGS = 8, /* number of target registers */
!   SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */
! };
  
  #ifdef __cplusplus
  }
Index: sim/sh/Makefile.in
===================================================================
RCS file: /cvs/src/src/sim/sh/Makefile.in,v
retrieving revision 1.2
diff -p -r1.2 Makefile.in
*** sim/sh/Makefile.in	7 Jun 2000 14:59:16 -0000	1.2
--- sim/sh/Makefile.in	12 Jun 2002 12:18:56 -0000
*************** SIM_EXTRA_CLEAN = sh-clean
*** 24,30 ****
  
  ## COMMON_POST_CONFIG_FRAG
  
! interp.o: interp.c code.c table.c ppi.c
  
  code.c: gencode
  	./gencode -x >code.c
--- 24,30 ----
  
  ## COMMON_POST_CONFIG_FRAG
  
! interp.o: interp.c code.c table.c ppi.c $(srcroot)/include/gdb/sim-sh.h
  
  code.c: gencode
  	./gencode -x >code.c
Index: sim/sh/interp.c
===================================================================
RCS file: /cvs/src/src/sim/sh/interp.c,v
retrieving revision 1.5
diff -p -r1.5 interp.c
*** sim/sh/interp.c	9 Jun 2002 15:45:52 -0000	1.5
--- sim/sh/interp.c	12 Jun 2002 12:18:56 -0000
***************
*** 29,34 ****
--- 29,35 ----
  #include "bfd.h"
  #include "gdb/callback.h"
  #include "gdb/remote-sim.h"
+ #include "gdb/sim-sh.h"
  
  /* This file is local - if newlib changes, then so should this.  */
  #include "syscall.h"
*************** sim_store_register (sd, rn, memory, leng
*** 1790,1887 ****
    val = swap (* (int *)memory);
    switch (rn)
      {
!     case  0: case  1: case  2: case  3: case  4: case  5: case  6: case  7:
!     case  8: case  9: case 10: case 11: case 12: case 13: case 14: case 15:
        saved_state.asregs.regs[rn] = val;
        break;
!     case 16:
        saved_state.asregs.pc = val;
        break;
!     case 17:
        PR = val;
        break;
!     case 18:
        GBR = val;
        break;
!     case 19:
        VBR = val;
        break;
!     case 20:
        MACH = val;
        break;
!     case 21:
        MACL = val;
        break;
!     case 22:
        SET_SR (val);
        break;
!     case 23:
        FPUL = val;
        break;
!     case 24:
        SET_FPSCR (val);
        break;
!     case 25:
        if (target_dsp)
  	A0G = val;
!     else case 26:
        if (target_dsp)
  	A0 = val;
!     else case 27:
        if (target_dsp)
  	A1G = val;
!     else case 28:
        if (target_dsp)
  	A1 = val;
!     else case 29:
        if (target_dsp)
  	M0 = val;
!     else case 30:
        if (target_dsp)
  	M1 = val;
!     else case 31:
        if (target_dsp)
  	X0 = val;
!     else case 32:
        if (target_dsp)
  	X1 = val;
!     else case 33:
        if (target_dsp)
  	Y0 = val;
!     else case 34:
        if (target_dsp)
  	Y1 = val;
!     else case 40:
        if (target_dsp)
  	SET_MOD (val);
!     else case 35: case 36: case 37: case 38: case 39:
! 	SET_FI (rn - 25, val);
        break;
!     case 41:
        SSR = val;
        break;
!     case 42:
        SPC = val;
        break;
      /* The rn_bank idiosyncracies are not due to hardware differences, but to
         a weird aliasing naming scheme for sh3 / sh3e / sh4.  */
!     case 43:
        if (target_dsp)
  	RS = val;
!     else case 44:
        if (target_dsp)
  	RE = val;
!     else case 45: case 46: case 47: case 48: case 49: case 50:
        if (SR_MD && SR_RB)
! 	Rn_BANK (rn - 43) = val;
        else
! 	saved_state.asregs.regs[rn - 43] = val;
        break;
!     case 51: case 52: case 53: case 54: case 55: case 56: case 57: case 58:
        if (target_dsp || ! SR_MD || ! SR_RB)
! 	SET_Rn_BANK (rn - 51, val);
        else
! 	saved_state.asregs.regs[rn - 51] = val;
        break;
      default:
        return 0;
--- 1791,1899 ----
    val = swap (* (int *)memory);
    switch (rn)
      {
!     case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM:
!     case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM:
!     case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM:
!     case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM:
!     case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM:
!     case SIM_SH_R15_REGNUM:
        saved_state.asregs.regs[rn] = val;
        break;
!     case SIM_SH_PC_REGNUM:
        saved_state.asregs.pc = val;
        break;
!     case SIM_SH_PR_REGNUM:
        PR = val;
        break;
!     case SIM_SH_GBR_REGNUM:
        GBR = val;
        break;
!     case SIM_SH_VBR_REGNUM:
        VBR = val;
        break;
!     case SIM_SH_MACH_REGNUM:
        MACH = val;
        break;
!     case SIM_SH_MACL_REGNUM:
        MACL = val;
        break;
!     case SIM_SH_SR_REGNUM:
        SET_SR (val);
        break;
!     case SIM_SH_FPUL_REGNUM:
        FPUL = val;
        break;
!     case SIM_SH_FPSCR_REGNUM:
        SET_FPSCR (val);
        break;
!     case SIM_SH_A0G_REGNUM:
        if (target_dsp)
  	A0G = val;
!     else case SIM_SH_A0_REGNUM:
        if (target_dsp)
  	A0 = val;
!     else case SIM_SH_A1G_REGNUM:
        if (target_dsp)
  	A1G = val;
!     else case SIM_SH_A1_REGNUM:
        if (target_dsp)
  	A1 = val;
!     else case SIM_SH_M0_REGNUM:
        if (target_dsp)
  	M0 = val;
!     else case SIM_SH_M1_REGNUM:
        if (target_dsp)
  	M1 = val;
!     else case SIM_SH_X0_REGNUM:
        if (target_dsp)
  	X0 = val;
!     else case SIM_SH_X1_REGNUM:
        if (target_dsp)
  	X1 = val;
!     else case SIM_SH_Y0_REGNUM:
        if (target_dsp)
  	Y0 = val;
!     else case SIM_SH_Y1_REGNUM:
        if (target_dsp)
  	Y1 = val;
!     else case SIM_SH_MOD_REGNUM:
        if (target_dsp)
  	SET_MOD (val);
!     else case SIM_SH_FR0_REGNUM+10:
!     case SIM_SH_FR0_REGNUM+11: case SIM_SH_FR0_REGNUM+12:
!     case SIM_SH_FR0_REGNUM+13: case SIM_SH_FR0_REGNUM+14:
! 	SET_FI (rn - SIM_SH_FR0_REGNUM, val);
        break;
!     case SIM_SH_SSR_REGNUM:
        SSR = val;
        break;
!     case SIM_SH_SPC_REGNUM:
        SPC = val;
        break;
      /* The rn_bank idiosyncracies are not due to hardware differences, but to
         a weird aliasing naming scheme for sh3 / sh3e / sh4.  */
!     case SIM_SH_RS_REGNUM:
        if (target_dsp)
  	RS = val;
!     else case SIM_SH_RE_REGNUM:
        if (target_dsp)
  	RE = val;
!     else case SIM_SH_R0_BANK0_REGNUM+2: case SIM_SH_R0_BANK0_REGNUM+3:
!     case SIM_SH_R0_BANK0_REGNUM+4: case SIM_SH_R0_BANK0_REGNUM+5:
!     case SIM_SH_R0_BANK0_REGNUM+6: case SIM_SH_R0_BANK0_REGNUM+7:
        if (SR_MD && SR_RB)
! 	Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) = val;
        else
! 	saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM] = val;
        break;
!     case SIM_SH_R0_BANK_REGNUM+0: case SIM_SH_R0_BANK_REGNUM+1:
!     case SIM_SH_R0_BANK_REGNUM+2: case SIM_SH_R0_BANK_REGNUM+3:
!     case SIM_SH_R0_BANK_REGNUM+4: case SIM_SH_R0_BANK_REGNUM+5:
!     case SIM_SH_R0_BANK_REGNUM+6: case SIM_SH_R0_BANK_REGNUM+7:
        if (target_dsp || ! SR_MD || ! SR_RB)
! 	SET_Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM, val);
        else
! 	saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM] = val;
        break;
      default:
        return 0;
*************** sim_fetch_register (sd, rn, memory, leng
*** 1901,1996 ****
    init_pointers ();
    switch (rn)
      {
!     case  0: case  1: case  2: case  3: case  4: case  5: case  6: case  7:
!     case  8: case  9: case 10: case 11: case 12: case 13: case 14: case 15:
        val = saved_state.asregs.regs[rn];
        break;
!     case 16:
        val = saved_state.asregs.pc;
        break;
!     case 17:
        val = PR;
        break;
!     case 18:
        val = GBR;
        break;
!     case 19:
        val = VBR;
        break;
!     case 20:
        val = MACH;
        break;
!     case 21:
        val = MACL;
        break;
!     case 22:
        val = GET_SR ();
        break;
!     case 23:
        val = FPUL;
        break;
!     case 24:
        val = GET_FPSCR ();
        break;
!     case 25:
!       val = target_dsp ? SEXT (A0G) : FI (0);
!       break;
!     case 26:
!       val = target_dsp ? A0 : FI (1);
!       break;
!     case 27:
!       val = target_dsp ? SEXT (A1G) : FI (2);
!       break;
!     case 28:
!       val = target_dsp ? A1 : FI (3);
!       break;
!     case 29:
!       val = target_dsp ? M0 : FI (4);
!       break;
!     case 30:
!       val = target_dsp ? M1 : FI (5);
!       break;
!     case 31:
!       val = target_dsp ? X0 : FI (6);
!       break;
!     case 32:
!       val = target_dsp ? X1 : FI (7);
!       break;
!     case 33:
!       val = target_dsp ? Y0 : FI (8);
!       break;
!     case 34:
!       val = target_dsp ? Y1 : FI (9);
!       break;
!     case 35: case 36: case 37: case 38: case 39:
!       val = FI (rn - 25);
!       break;
!     case 40:
!       val = target_dsp ? MOD : FI (15);
        break;
!     case 41:
        val = SSR;
        break;
!     case 42:
        val = SPC;
        break;
      /* The rn_bank idiosyncracies are not due to hardware differences, but to
         a weird aliasing naming scheme for sh3 / sh3e / sh4.  */
!     case 43:
        if (target_dsp)
  	val = RS;
!     else case 44:
        if (target_dsp)
  	val = RE;
!     else case 45: case 46: case 47: case 48: case 49: case 50:
  	val = (SR_MD && SR_RB
! 	       ? Rn_BANK (rn - 43)
! 	       : saved_state.asregs.regs[rn - 43]);
        break;
!     case 51: case 52: case 53: case 54: case 55: case 56: case 57: case 58:
        val = (target_dsp || ! SR_MD || ! SR_RB
! 	     ? Rn_BANK (rn - 51)
! 	     : saved_state.asregs.regs[rn - 51]);
        break;
      default:
        return 0;
--- 1913,2019 ----
    init_pointers ();
    switch (rn)
      {
!     case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM:
!     case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM:
!     case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM:
!     case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM:
!     case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM:
!     case SIM_SH_R15_REGNUM:
        val = saved_state.asregs.regs[rn];
        break;
!     case SIM_SH_PC_REGNUM:
        val = saved_state.asregs.pc;
        break;
!     case SIM_SH_PR_REGNUM:
        val = PR;
        break;
!     case SIM_SH_GBR_REGNUM:
        val = GBR;
        break;
!     case SIM_SH_VBR_REGNUM:
        val = VBR;
        break;
!     case SIM_SH_MACH_REGNUM:
        val = MACH;
        break;
!     case SIM_SH_MACL_REGNUM:
        val = MACL;
        break;
!     case SIM_SH_SR_REGNUM:
        val = GET_SR ();
        break;
!     case SIM_SH_FPUL_REGNUM:
        val = FPUL;
        break;
!     case SIM_SH_FPSCR_REGNUM:
        val = GET_FPSCR ();
        break;
!     case SIM_SH_A0G_REGNUM:
!       if (target_dsp)
! 	val = SEXT (A0G);
!     else case SIM_SH_A0_REGNUM:
!       if (target_dsp)
! 	val = A0;
!     else case SIM_SH_A1G_REGNUM:
!       if (target_dsp)
! 	val = SEXT (A1G);
!     else case SIM_SH_A1_REGNUM:
!       if (target_dsp)
! 	val = A1;
!     else case SIM_SH_M0_REGNUM:
!       if (target_dsp)
! 	val = M0;
!     else case SIM_SH_M1_REGNUM:
!       if (target_dsp)
! 	val = M1;
!     else case SIM_SH_X0_REGNUM:
!       if (target_dsp)
! 	val = X0;
!     else case SIM_SH_X1_REGNUM:
!       if (target_dsp)
! 	val = X1;
!     else case SIM_SH_Y0_REGNUM:
!       if (target_dsp)
! 	val = Y0;
!     else case SIM_SH_Y1_REGNUM:
!       if (target_dsp)
! 	val = Y1;
!     else case SIM_SH_MOD_REGNUM:
!       if (target_dsp)
! 	val = MOD;
!     else case SIM_SH_FR0_REGNUM+10:
!     case SIM_SH_FR0_REGNUM+11: case SIM_SH_FR0_REGNUM+12:
!     case SIM_SH_FR0_REGNUM+13: case SIM_SH_FR0_REGNUM+14:
! 	val = FI (rn - SIM_SH_FR0_REGNUM);
        break;
!     case SIM_SH_SSR_REGNUM:
        val = SSR;
        break;
!     case SIM_SH_SPC_REGNUM:
        val = SPC;
        break;
      /* The rn_bank idiosyncracies are not due to hardware differences, but to
         a weird aliasing naming scheme for sh3 / sh3e / sh4.  */
!     case SIM_SH_RS_REGNUM:
        if (target_dsp)
  	val = RS;
!     else case SIM_SH_RE_REGNUM:
        if (target_dsp)
  	val = RE;
!     else case SIM_SH_R0_BANK0_REGNUM+2: case SIM_SH_R0_BANK0_REGNUM+3:
!     case SIM_SH_R0_BANK0_REGNUM+4: case SIM_SH_R0_BANK0_REGNUM+5:
!     case SIM_SH_R0_BANK0_REGNUM+6: case SIM_SH_R0_BANK0_REGNUM+7:
  	val = (SR_MD && SR_RB
! 	       ? Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM)
! 	       : saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM]);
        break;
!     case SIM_SH_R0_BANK_REGNUM+0: case SIM_SH_R0_BANK_REGNUM+1:
!     case SIM_SH_R0_BANK_REGNUM+2: case SIM_SH_R0_BANK_REGNUM+3:
!     case SIM_SH_R0_BANK_REGNUM+4: case SIM_SH_R0_BANK_REGNUM+5:
!     case SIM_SH_R0_BANK_REGNUM+6: case SIM_SH_R0_BANK_REGNUM+7:
        val = (target_dsp || ! SR_MD || ! SR_RB
! 	     ? Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM)
! 	     : saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM]);
        break;
      default:
        return 0;

Re: Unreviewed patch: add include/gdb/sim-sh.h (Was: Re: SH simulator register numbers: include/gdb/sim-sh.h)

[Andrew Cagney]

> Elena Zannoni wrote:
> 
>> 
>> Sorry.
>> Can you format the file with one register per line?
>> Take a look at sim-d10v.h, now that Andrew cleaned it up.
> 

Just FYI, there are now two examples - sim-d10v.h and sim-arm.h.  In 
both cases the GDB<->sim interface is defined by a simple pure enum - 
there are no assignments or gaps.

If a mapping is needed then REGISTER_SIM_REGNO handles it.

enjoy,
Andrew