Re: [PATCH] : SH Assembler generates incorrect opcode for PCMP instructions

[Joern Rennecke <joern.rennecke@superh.com>]

Nick Clifton wrote:
> 
> Hi Arati,
> 
> > The SH assembler generates incorrect opcodes for the parallel PCMP
> > instruction.  Basically, its last nibble is a copy of the previous
> > instruction's second nibble when working in Big Endian format.

That's not exactly incorrect, since the reg_n field for pcmp is
ignored by the CPU.

> Your patch does work, but I do not like the way it makes a special
> case out of the opcode's name.  In fact I think that it may not be
> just the PCMP instruction that has this problem, since a perusal of
> the sh-opc.h file indicates that the PABS and PRND instructions may
> also have similar difficulties.

No, PCMP is indeed special, since it is the only PPI3 instuction that
ignores REG_N.

Moreover, REG_X and REG_Y are initialized at the start of assemble_ppi.

To get non-varying opcodes for pcmp, you can clear reg_n at that point, too.
	
-- 
--------------------------
SuperH
2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
T:+44 1454 462330