From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 482893858D39 for ; Thu, 9 May 2024 14:31:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 482893858D39 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 482893858D39 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715265110; cv=none; b=FTw5r/MWb0a78/aHAHmm/M0lkDELHdZxrYgKYY/gDu0XrliZHcZ3g2kjp9Wddf5TESrfvQAPGQelu5QTXcEjPgGhLj1S6O0dZpexkrzrj7IbmT8otAWjDmyvAVPvtZg0Zuh1jxTrGsGVQTFJTRG5su4cyXQLiWVSQt3r23Sqn8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715265110; c=relaxed/simple; bh=KcNdG8xhcaFO/j99txs1EqK53SUnN11hFLKeTIfQ1u4=; h=Message-ID:Date:MIME-Version:Subject:To:From; b=IE4wXsRrXJ0uq6ywJkNUjJzcSurlv2Hlu2JX7jFrvmhZz4ZpRRH+XBHc5ngBoU5V9de4LicC0xS4Hk+SDvCpFsB6p1LZZmZq9p98H0aY3CyOR88DfprbJwuxGbfAVUGEwo3YIe1adAWxORxdfc/8qBDbLJ+2IR8AlDbIB5zf4uE= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 77A70106F; Thu, 9 May 2024 07:32:13 -0700 (PDT) Received: from [10.57.82.226] (unknown [10.57.82.226]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0BC643F641; Thu, 9 May 2024 07:31:46 -0700 (PDT) Message-ID: <3a2d83e5-a1a9-4851-bbb4-b19274f41b4f@arm.com> Date: Thu, 9 May 2024 15:31:45 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/6] Arm64: correct SVE2.1 ld{3,4}q / st{3,4}q (scalar plus immediate) To: Jan Beulich , Binutils Cc: Richard Earnshaw , Marcus Shawcroft , Nick Clifton References: <2dbdd49f-2302-4dbc-98ba-0bdaf3c4cad2@suse.com> <93c4fe9f-159b-42d2-9003-8593e0782c74@suse.com> Content-Language: en-GB From: "Richard Earnshaw (lists)" In-Reply-To: <93c4fe9f-159b-42d2-9003-8593e0782c74@suse.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3491.3 required=5.0 tests=BAYES_00,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 23/02/2024 11:29, Jan Beulich wrote: > Like their byte, half, word, and doubleword counterparts their > immediates are multiples of 3 / 4 respectively. OK, but please change the summary tag to aarch64. R. > > --- a/gas/testsuite/gas/aarch64/sve2p1-1.d > +++ b/gas/testsuite/gas/aarch64/sve2p1-1.d > @@ -1,4 +1,4 @@ > -#name: Test of SVE2.1 min max instructions. > +#name: Test of SVE2.1 instructions > #as: -march=armv9.4-a+sve2p1 > #objdump: -dr > > @@ -91,15 +91,15 @@ > .*: 6497bc10 fminqv v16.4s, p7, z0.s > .*: c400b200 ld1q z0.q, p4/z, \[z16.d, x0\] > .*: a49ef000 ld2q {z0.q, z1.q}, p4/z, \[x0, #-4, mul vl\] > -.*: a51ef000 ld3q {z0.q, z1.q, z2.q}, p4/z, \[x0, #-4, mul vl\] > -.*: a59ef000 ld4q {z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, #-4, mul vl\] > +.*: a51ef000 ld3q {z0.q, z1.q, z2.q}, p4/z, \[x0, #-6, mul vl\] > +.*: a59ef000 ld4q {z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, #-8, mul vl\] > .*: a4a2f000 ld2h {z0.h-z1.h}, p4/z, \[x0, #4, mul vl\] > .*: a5249000 ld3q {z0.q, z1.q, z2.q}, p4/z, \[x0, x4, lsl #4\] > .*: a5a69000 ld4q {z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, x6, lsl #4\] > .*: e4203200 st1q z0.q, p4, \[z16.d, x0\] > .*: e44e1000 st2q {z0.q, z1.q}, p4, \[x0, #-4, mul vl\] > -.*: e48e1000 st3q {z0.q, z1.q, z2.q}, p4, \[x0, #-4, mul vl\] > -.*: e4ce1000 st4q {z0.q, z1.q, z2.q, z3.q}, p4, \[x0, #-4, mul vl\] > +.*: e48e1000 st3q {z0.q, z1.q, z2.q}, p4, \[x0, #-6, mul vl\] > +.*: e4ce1000 st4q {z0.q, z1.q, z2.q, z3.q}, p4, \[x0, #-8, mul vl\] > .*: e4621000 st2q {z0.q, z1.q}, p4, \[x0, x2, lsl #4\] > .*: e4a41000 st3q {z0.q, z1.q, z2.q}, p4, \[x0, x4, lsl #4\] > .*: e4e61000 st4q {z0.q, z1.q, z2.q, z3.q}, p4, \[x0, x6, lsl #4\] > --- a/gas/testsuite/gas/aarch64/sve2p1-1.s > +++ b/gas/testsuite/gas/aarch64/sve2p1-1.s > @@ -92,16 +92,16 @@ fminqv v8.2d, p4, z1.d > fminqv v16.4s, p7, z0.s > ld1q Z0.Q, p4/Z, [Z16.D, x0] > ld2q {Z0.Q, Z1.Q}, p4/Z, [x0, #-4, MUL VL] > -ld3q {Z0.Q, Z1.Q, Z2.Q}, p4/Z, [x0, #-4, MUL VL] > -ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4/Z, [x0, #-4, MUL VL] > +ld3q {Z0.Q, Z1.Q, Z2.Q}, p4/Z, [x0, #-6, MUL VL] > +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4/Z, [x0, #-8, MUL VL] > ld2q {Z0.Q, Z1.Q}, p4/Z, [x0, x2, lsl #4] > ld3q {Z0.Q, Z1.Q, Z2.Q}, p4/Z, [x0, x4, lsl #4] > ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4/Z, [x0, x6, lsl #4] > > st1q Z0.Q, p4, [Z16.D, x0] > st2q {Z0.Q, Z1.Q}, p4, [x0, #-4, MUL VL] > -st3q {Z0.Q, Z1.Q, Z2.Q}, p4, [x0, #-4, MUL VL] > -st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4, [x0, #-4, MUL VL] > +st3q {Z0.Q, Z1.Q, Z2.Q}, p4, [x0, #-6, MUL VL] > +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4, [x0, #-8, MUL VL] > st2q {Z0.Q, Z1.Q}, p4, [x0, x2, lsl #4] > st3q {Z0.Q, Z1.Q, Z2.Q}, p4, [x0, x4, lsl #4] > st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4, [x0, x6, lsl #4] > --- a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l > +++ b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l > @@ -82,15 +82,15 @@ > .*: Error: selected processor does not support `fminqv v16.4s,p7,z0.s' > .*: Error: selected processor does not support `ld1q Z0.Q,p4/Z,\[Z16.D,x0\]' > .*: Error: selected processor does not support `ld2q {Z0.Q,Z1.Q},p4/Z,\[x0,#-4,MUL VL\]' > -.*: Error: selected processor does not support `ld3q {Z0.Q,Z1.Q,Z2.Q},p4/Z,\[x0,#-4,MUL VL\]' > -.*: Error: selected processor does not support `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4/Z,\[x0,#-4,MUL VL\]' > +.*: Error: selected processor does not support `ld3q .* > +.*: Error: selected processor does not support `ld4q .* > .*: Error: selected processor does not support `ld2q {Z0.Q,Z1.Q},p4/Z,\[x0,x2,lsl#4\]' > .*: Error: selected processor does not support `ld3q {Z0.Q,Z1.Q,Z2.Q},p4/Z,\[x0,x4,lsl#4\]' > .*: Error: selected processor does not support `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4/Z,\[x0,x6,lsl#4\]' > .*: Error: selected processor does not support `st1q Z0.Q,p4,\[Z16.D,x0\]' > .*: Error: selected processor does not support `st2q {Z0.Q,Z1.Q},p4,\[x0,#-4,MUL VL\]' > -.*: Error: selected processor does not support `st3q {Z0.Q,Z1.Q,Z2.Q},p4,\[x0,#-4,MUL VL\]' > -.*: Error: selected processor does not support `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4,\[x0,#-4,MUL VL\]' > +.*: Error: selected processor does not support `st3q .* > +.*: Error: selected processor does not support `st4q .* > .*: Error: selected processor does not support `st2q {Z0.Q,Z1.Q},p4,\[x0,x2,lsl#4\]' > .*: Error: selected processor does not support `st3q {Z0.Q,Z1.Q,Z2.Q},p4,\[x0,x4,lsl#4\]' > .*: Error: selected processor does not support `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4,\[x0,x6,lsl#4\]' > --- a/opcodes/aarch64-tbl.h > +++ b/opcodes/aarch64-tbl.h > @@ -6378,16 +6378,16 @@ const struct aarch64_opcode aarch64_opco > SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 1), > SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0), > SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), > - SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), > - SVE2p1_INSNC("ld4q",0xa590e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), > + SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), > + SVE2p1_INSNC("ld4q",0xa590e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), > SVE2p1_INSNC("ld2q",0xa4a0e000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), > SVE2p1_INSNC("ld3q",0xa5208000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), > SVE2p1_INSNC("ld4q",0xa5a08000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), > > SVE2p1_INSNC("st1q",0xe4202000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SUS_QD, 0, C_SCAN_MOVPRFX, 0), > SVE2p1_INSNC("st2q",0xe4400000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), > - SVE2p1_INSNC("st3q",0xe4800000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), > - SVE2p1_INSNC("st4q",0xe4c00000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), > + SVE2p1_INSNC("st3q",0xe4800000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), > + SVE2p1_INSNC("st4q",0xe4c00000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), > SVE2p1_INSNC("st2q",0xe4600000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), > SVE2p1_INSNC("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), > SVE2p1_INSNC("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), >