From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id D65B038A941C for ; Tue, 11 Jan 2022 10:48:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D65B038A941C Received: by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 46F88300089; Tue, 11 Jan 2022 10:48:30 +0000 (UTC) From: Tsukasa OI To: Tsukasa OI Cc: binutils@sourceware.org Subject: [RFC PATCH 2/5] RISC-V: Add insn classes for Zfh/Zfhmin extensions Date: Tue, 11 Jan 2022 19:48:17 +0900 Message-Id: <3a40c19310810288606061a733581b1b277aec0e.1641898063.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 11 Jan 2022 10:48:33 -0000 This commit adds several instruction classes corresponding 'Zfh', 'Zfhmin' and 'Zfhmin'+'D|Q' extensions. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add handling for new instruction classes. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Add new instruction classes INSN_CLASS_ZFH, INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_AND_D and INSN_CLASS_ZFHMIN_AND_Q. --- bfd/elfxx-riscv.c | 10 ++++++++++ include/opcode/riscv.h | 4 ++++ 2 files changed, 14 insertions(+) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index dbe3611304b..4f3705ad396 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -2368,6 +2368,16 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, case INSN_CLASS_Q_OR_ZQINX: return (riscv_subset_supports (rps, "q") || riscv_subset_supports (rps, "zqinx")); + case INSN_CLASS_ZFH: + return riscv_subset_supports (rps, "zfh"); + case INSN_CLASS_ZFHMIN: + return riscv_subset_supports (rps, "zfhmin"); + case INSN_CLASS_ZFHMIN_AND_D: + return (riscv_subset_supports (rps, "zfhmin") + && riscv_subset_supports (rps, "d")); + case INSN_CLASS_ZFHMIN_AND_Q: + return (riscv_subset_supports (rps, "zfhmin") + && riscv_subset_supports (rps, "q")); case INSN_CLASS_ZBA: return riscv_subset_supports (rps, "zba"); case INSN_CLASS_ZBB: diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 048ab0a5d68..a5da8d0c4e0 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -370,6 +370,10 @@ enum riscv_insn_class INSN_CLASS_F_OR_ZFINX, INSN_CLASS_D_OR_ZDINX, INSN_CLASS_Q_OR_ZQINX, + INSN_CLASS_ZFH, + INSN_CLASS_ZFHMIN, + INSN_CLASS_ZFHMIN_AND_D, + INSN_CLASS_ZFHMIN_AND_Q, INSN_CLASS_ZBA, INSN_CLASS_ZBB, INSN_CLASS_ZBC, -- 2.32.0