From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 94D273858CDA for ; Tue, 28 May 2024 16:29:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 94D273858CDA Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 94D273858CDA Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716913787; cv=none; b=ciZL9+dPqEvQ0m195Gj7rECmCA/tAun4AtFxB303DzYw2Q4zpv50oHwA/2qSWSTZopFLdjlbCL1Krj2O54XcDecw7Q9Iplbn8nPsFy34cba3fb4/cx+LHsEfpKX5/oIWdg8ZzCqmCoPfPRebC0Q2LGlpILJ6jEE57zBaGJgFZ48= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716913787; c=relaxed/simple; bh=nWYj+8X4t8XksUrFTK07yplMyd1iURMc/UuelSG0RK4=; h=Message-ID:Date:MIME-Version:Subject:To:From; b=lRjIIMqmsQtH6afiyxDhZkvckj6eqD7jcFxL923c0szUgv/4FImsPNB2Mqmpksr+O8xwNcio1+ZuQvIoRmQw3fPmdm+lMjnqqme9GiNVFzGrfA/MtdDxpHZBfbiD6lFO3XYVlS1KKUp5e+qRLDoGKl7e7rCdFyihRFjhtYst/Z8= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5A34C339; Tue, 28 May 2024 09:30:08 -0700 (PDT) Received: from [10.2.78.57] (e120077-lin.cambridge.arm.com [10.2.78.57]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B70043F762; Tue, 28 May 2024 09:29:43 -0700 (PDT) Message-ID: <3cca55a8-bc56-4ad0-a2e5-79d9177d2972@arm.com> Date: Tue, 28 May 2024 17:29:42 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 1/4] gas, aarch64: Add AdvSIMD lut extension To: saurabh.jha@arm.com, binutils@sourceware.org References: <20240528144553.2994250-1-saurabh.jha@arm.com> From: "Richard Earnshaw (lists)" Content-Language: en-GB In-Reply-To: <20240528144553.2994250-1-saurabh.jha@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3491.3 required=5.0 tests=BAYES_00,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 28/05/2024 15:45, saurabh.jha@arm.com wrote: > > Introduces instructions for the Advanced SIMD lut extension for AArch64. They are documented in the following links: > * luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en > * luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en > > These instructions needed definition of some new operands. We will first > discuss operands for the third operand of the instructions and then > discuss a vector register list operand needed for the second operand. > > The third operands are vectors with bit indices and without type > qualifiers. They are called Em_INDEX1_14, Em_INDEX2_13, and Em_INDEX3_12 > and they have 1 bit, 2 bit, and 3 bit indices respectively. For these > new operands, we defined new parsing case branch. The lsb and width of > these operands are the same as many existing but the convention is to > give different names to fields that serve different purpose so we > introduced new fields in aarch64-opc.c and aarch64-opc.h for these new > operands. > > For the second operand of these instructions, we introduced a new > operand called LVn_LUT. This represents a vector register list with > stride 1. We defined new inserter and extractor for this new operand and > it is encoded in FLD_Rn. We are enforcing the number of registers in the > reglist using opcode flag rather than operand flag as this is what other > SIMD vector register list operands are doing. The disassembly also uses > opcode flag to print the correct number of registers. > --- > Hi, > > Regression tested for aarch64-none-elf and found no regressions. > > Ok for binutils-master? I don't have commit access so can someone please commit on my behalf? Thanks, I've pushed this series after squashing the regenerated files into their corresponding parent patches. R. > > Regards, > Saurabh > --- > gas/NEWS | 2 + > gas/config/tc-aarch64.c | 67 ++++++ > gas/doc/c-aarch64.texi | 2 + > gas/testsuite/gas/aarch64/advsimd-lut-bad.d | 3 + > gas/testsuite/gas/aarch64/advsimd-lut-bad.l | 25 +++ > .../gas/aarch64/advsimd-lut-illegal.d | 3 + > .../gas/aarch64/advsimd-lut-illegal.l | 208 ++++++++++++++++++ > .../gas/aarch64/advsimd-lut-illegal.s | 128 +++++++++++ > gas/testsuite/gas/aarch64/advsimd-lut.d | 32 +++ > gas/testsuite/gas/aarch64/advsimd-lut.s | 29 +++ > include/opcode/aarch64.h | 9 +- > opcodes/aarch64-asm.c | 11 + > opcodes/aarch64-asm.h | 1 + > opcodes/aarch64-dis.c | 15 ++ > opcodes/aarch64-dis.h | 1 + > opcodes/aarch64-opc.c | 23 ++ > opcodes/aarch64-opc.h | 2 + > opcodes/aarch64-tbl.h | 38 +++- > 18 files changed, 597 insertions(+), 2 deletions(-) > create mode 100644 gas/testsuite/gas/aarch64/advsimd-lut-bad.d > create mode 100644 gas/testsuite/gas/aarch64/advsimd-lut-bad.l > create mode 100644 gas/testsuite/gas/aarch64/advsimd-lut-illegal.d > create mode 100644 gas/testsuite/gas/aarch64/advsimd-lut-illegal.l > create mode 100644 gas/testsuite/gas/aarch64/advsimd-lut-illegal.s > create mode 100644 gas/testsuite/gas/aarch64/advsimd-lut.d > create mode 100644 gas/testsuite/gas/aarch64/advsimd-lut.s >