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* [PATCH 4/6] aarch64: Remove ZIDR_EL1
@ 2021-11-30 12:22 Richard Sandiford
  2021-11-30 13:31 ` Richard Earnshaw
  0 siblings, 1 reply; 2+ messages in thread
From: Richard Sandiford @ 2021-11-30 12:22 UTC (permalink / raw)
  To: binutils; +Cc: rearnsha

ZIDR_EL1 was part of an early version of SVE, but didn't make
it to the final release.

Tested on aarch64-linux-gnu.  OK to install?

Richard


opcodes/
	* aarch64-opc.c (aarch64_sys_regs): Remove zidr_el1 entry.

gas/
	* testsuite/gas/aarch64/sve-sysreg.s: Remove zidr_el1.
	* testsuite/gas/aarch64/sve-sysreg.d: Update accordingly.
	* testsuite/gas/aarch64/sve-sysreg-invalid.l: Likewise.
---
 gas/testsuite/gas/aarch64/sve-sysreg-invalid.l | 2 --
 gas/testsuite/gas/aarch64/sve-sysreg.d         | 2 --
 gas/testsuite/gas/aarch64/sve-sysreg.s         | 3 ---
 opcodes/aarch64-opc.c                          | 1 -
 4 files changed, 8 deletions(-)

diff --git a/gas/testsuite/gas/aarch64/sve-sysreg-invalid.l b/gas/testsuite/gas/aarch64/sve-sysreg-invalid.l
index b68c41decfd..0eaefe147df 100644
--- a/gas/testsuite/gas/aarch64/sve-sysreg-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve-sysreg-invalid.l
@@ -17,5 +17,3 @@
 .*:20: Error: selected processor does not support system register name 'zcr_el3'
 .*:21: Error: selected processor does not support system register name 'zcr_el3'
 .*:22: Error: selected processor does not support system register name 'zcr_el3'
-.*:24: Error: selected processor does not support system register name 'zidr_el1'
-.*:25: Error: selected processor does not support system register name 'zidr_el1'
diff --git a/gas/testsuite/gas/aarch64/sve-sysreg.d b/gas/testsuite/gas/aarch64/sve-sysreg.d
index 24ab421e456..22d9e5ac1f6 100644
--- a/gas/testsuite/gas/aarch64/sve-sysreg.d
+++ b/gas/testsuite/gas/aarch64/sve-sysreg.d
@@ -25,5 +25,3 @@ Disassembly of section .*:
 .*:	d53e121b 	mrs	x27, zcr_el3
 .*:	d51e1200 	msr	zcr_el3, x0
 .*:	d51e121a 	msr	zcr_el3, x26
-.*:	d53800e0 	mrs	x0, zidr_el1
-.*:	d53800fb 	mrs	x27, zidr_el1
diff --git a/gas/testsuite/gas/aarch64/sve-sysreg.s b/gas/testsuite/gas/aarch64/sve-sysreg.s
index a38ad7ffbf9..90e0951d31d 100644
--- a/gas/testsuite/gas/aarch64/sve-sysreg.s
+++ b/gas/testsuite/gas/aarch64/sve-sysreg.s
@@ -20,6 +20,3 @@
 	mrs	X27, zcr_el3
 	msr	ZCR_EL3, X0
 	msr	zcr_el3, x26
-
-	mrs	x0, ZIDR_EL1
-	mrs	X27, zidr_el1
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 34b141eaed0..ace7032b7fb 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4119,7 +4119,6 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   SR_SVE  ("zcr_el12",		CPENC (3,5,C1,C2,0),	0),
   SR_SVE  ("zcr_el2",		CPENC (3,4,C1,C2,0),	0),
   SR_SVE  ("zcr_el3",		CPENC (3,6,C1,C2,0),	0),
-  SR_SVE  ("zidr_el1",		CPENC (3,0,C0,C0,7),	0),
   SR_CORE ("ttbr0_el1",		CPENC (3,0,C2,C0,0),	0),
   SR_CORE ("ttbr1_el1",		CPENC (3,0,C2,C0,1),	0),
   SR_V8_A ("ttbr0_el2",		CPENC (3,4,C2,C0,0),	0),
-- 
2.25.1


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH 4/6] aarch64: Remove ZIDR_EL1
  2021-11-30 12:22 [PATCH 4/6] aarch64: Remove ZIDR_EL1 Richard Sandiford
@ 2021-11-30 13:31 ` Richard Earnshaw
  0 siblings, 0 replies; 2+ messages in thread
From: Richard Earnshaw @ 2021-11-30 13:31 UTC (permalink / raw)
  To: binutils, rearnsha, richard.sandiford



On 30/11/2021 12:22, Richard Sandiford via Binutils wrote:
> ZIDR_EL1 was part of an early version of SVE, but didn't make
> it to the final release.
> 
> Tested on aarch64-linux-gnu.  OK to install?

I presume that if there is any code out there that is using this 
register then it will need rewriting anyway.

OK.

R.

> 
> Richard
> 
> 
> opcodes/
> 	* aarch64-opc.c (aarch64_sys_regs): Remove zidr_el1 entry.
> 
> gas/
> 	* testsuite/gas/aarch64/sve-sysreg.s: Remove zidr_el1.
> 	* testsuite/gas/aarch64/sve-sysreg.d: Update accordingly.
> 	* testsuite/gas/aarch64/sve-sysreg-invalid.l: Likewise.
> ---
>   gas/testsuite/gas/aarch64/sve-sysreg-invalid.l | 2 --
>   gas/testsuite/gas/aarch64/sve-sysreg.d         | 2 --
>   gas/testsuite/gas/aarch64/sve-sysreg.s         | 3 ---
>   opcodes/aarch64-opc.c                          | 1 -
>   4 files changed, 8 deletions(-)
> 
> diff --git a/gas/testsuite/gas/aarch64/sve-sysreg-invalid.l b/gas/testsuite/gas/aarch64/sve-sysreg-invalid.l
> index b68c41decfd..0eaefe147df 100644
> --- a/gas/testsuite/gas/aarch64/sve-sysreg-invalid.l
> +++ b/gas/testsuite/gas/aarch64/sve-sysreg-invalid.l
> @@ -17,5 +17,3 @@
>   .*:20: Error: selected processor does not support system register name 'zcr_el3'
>   .*:21: Error: selected processor does not support system register name 'zcr_el3'
>   .*:22: Error: selected processor does not support system register name 'zcr_el3'
> -.*:24: Error: selected processor does not support system register name 'zidr_el1'
> -.*:25: Error: selected processor does not support system register name 'zidr_el1'
> diff --git a/gas/testsuite/gas/aarch64/sve-sysreg.d b/gas/testsuite/gas/aarch64/sve-sysreg.d
> index 24ab421e456..22d9e5ac1f6 100644
> --- a/gas/testsuite/gas/aarch64/sve-sysreg.d
> +++ b/gas/testsuite/gas/aarch64/sve-sysreg.d
> @@ -25,5 +25,3 @@ Disassembly of section .*:
>   .*:	d53e121b 	mrs	x27, zcr_el3
>   .*:	d51e1200 	msr	zcr_el3, x0
>   .*:	d51e121a 	msr	zcr_el3, x26
> -.*:	d53800e0 	mrs	x0, zidr_el1
> -.*:	d53800fb 	mrs	x27, zidr_el1
> diff --git a/gas/testsuite/gas/aarch64/sve-sysreg.s b/gas/testsuite/gas/aarch64/sve-sysreg.s
> index a38ad7ffbf9..90e0951d31d 100644
> --- a/gas/testsuite/gas/aarch64/sve-sysreg.s
> +++ b/gas/testsuite/gas/aarch64/sve-sysreg.s
> @@ -20,6 +20,3 @@
>   	mrs	X27, zcr_el3
>   	msr	ZCR_EL3, X0
>   	msr	zcr_el3, x26
> -
> -	mrs	x0, ZIDR_EL1
> -	mrs	X27, zidr_el1
> diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
> index 34b141eaed0..ace7032b7fb 100644
> --- a/opcodes/aarch64-opc.c
> +++ b/opcodes/aarch64-opc.c
> @@ -4119,7 +4119,6 @@ const aarch64_sys_reg aarch64_sys_regs [] =
>     SR_SVE  ("zcr_el12",		CPENC (3,5,C1,C2,0),	0),
>     SR_SVE  ("zcr_el2",		CPENC (3,4,C1,C2,0),	0),
>     SR_SVE  ("zcr_el3",		CPENC (3,6,C1,C2,0),	0),
> -  SR_SVE  ("zidr_el1",		CPENC (3,0,C0,C0,7),	0),
>     SR_CORE ("ttbr0_el1",		CPENC (3,0,C2,C0,0),	0),
>     SR_CORE ("ttbr1_el1",		CPENC (3,0,C2,C0,1),	0),
>     SR_V8_A ("ttbr0_el2",		CPENC (3,4,C2,C0,0),	0),
> 

^ permalink raw reply	[flat|nested] 2+ messages in thread

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