From: "Andre Vieira (lists)" <andre.simoesdiasvieira@arm.com>
To: binutils@sourceware.org
Subject: [PATCH 15/57][Arm][GAS] Add support for MVE instructions: vcls, vclz and vfmas
Date: Wed, 01 May 2019 17:09:00 -0000 [thread overview]
Message-ID: <3f18ee2c-76a9-6132-03fc-f555e1794c74@arm.com> (raw)
In-Reply-To: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com>
[-- Attachment #1: Type: text/plain, Size: 785 bytes --]
Hi,
This patch adds support for MVE instructions: VCLS, VCLZ, and VFMAS.
gas/ChangeLog:
2019-05-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vfmas): New encoding function.
(do_neon_cls): Change to support MVE variants.
(do_neon_clz): Change to support MVE variants.
(insns): Change to support MVE variants and add new.
* testsuite/gas/arm/mve-vcls-bad.d: New test.
* testsuite/gas/arm/mve-vcls-bad.l: New test.
* testsuite/gas/arm/mve-vcls-bad.s: New test.
* testsuite/gas/arm/mve-vclz-bad.d: New test.
* testsuite/gas/arm/mve-vclz-bad.l: New test.
* testsuite/gas/arm/mve-vclz-bad.s: New test.
* testsuite/gas/arm/mve-vfmas-bad.d: New test.
* testsuite/gas/arm/mve-vfmas-bad.l: New test.
* testsuite/gas/arm/mve-vfmas-bad.s: New test.
[-- Attachment #2: 15.patch --]
[-- Type: text/x-patch, Size: 10428 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 8d61ab3f1c5017294c36524047137c410dae32a6..e739c5b94ab1924f65a262e15342a748e2a4dc40 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -15582,6 +15582,32 @@ do_mve_vcmp (void)
return;
}
+static void
+do_mve_vfmas (void)
+{
+ enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
+ struct neon_type_el et
+ = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK, N_EQK);
+
+ if (inst.cond > COND_ALWAYS)
+ inst.pred_insn_type = INSIDE_VPT_INSN;
+ else
+ inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
+
+ if (inst.operands[2].reg == REG_SP)
+ as_tsktsk (MVE_BAD_SP);
+ else if (inst.operands[2].reg == REG_PC)
+ as_tsktsk (MVE_BAD_PC);
+
+ inst.instruction |= (et.size == 16) << 28;
+ inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+ inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
+ inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+ inst.instruction |= HI1 (inst.operands[1].reg) << 7;
+ inst.instruction |= inst.operands[2].reg;
+ inst.is_neon = 1;
+}
+
static void
do_mve_vcmul (void)
{
@@ -19006,7 +19032,15 @@ do_neon_recip_est (void)
static void
do_neon_cls (void)
{
- enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+ if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
+ return;
+
+ enum neon_shape rs;
+ if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
+ rs = neon_select_shape (NS_QQ, NS_NULL);
+ else
+ rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+
struct neon_type_el et = neon_check_type (2, rs,
N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
neon_two_same (neon_quad (rs), 1, et.size);
@@ -19015,7 +19049,15 @@ do_neon_cls (void)
static void
do_neon_clz (void)
{
- enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+ if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
+ return;
+
+ enum neon_shape rs;
+ if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
+ rs = neon_select_shape (NS_QQ, NS_NULL);
+ else
+ rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+
struct neon_type_el et = neon_check_type (2, rs,
N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
neon_two_same (neon_quad (rs), 1, et.size);
@@ -23648,10 +23690,8 @@ static const struct asm_opcode insns[] =
NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
/* VCLS. Types S8 S16 S32. */
- NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
/* VCLZ. Types I8 I16 I32. */
- NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
/* VCNT. Size 8. */
NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
@@ -24185,6 +24225,7 @@ static const struct asm_opcode insns[] =
#undef THUMB_VARIANT
#define THUMB_VARIANT & mve_fp_ext
mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
+ mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_vfp_ext_v1
@@ -24240,6 +24281,8 @@ static const struct asm_opcode insns[] =
mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
mnUF(vorn, _vorn, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic),
+ MNUF(vcls, 1b00400, 2, (RNDQMQ, RNDQMQ), neon_cls),
+ MNUF(vclz, 1b00480, 2, (RNDQMQ, RNDQMQ), neon_clz),
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_v8_3
diff --git a/gas/testsuite/gas/arm/mve-vcls-bad.d b/gas/testsuite/gas/arm/mve-vcls-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..0cfdabd7a5f8c3152cd704eb1a68dfda40bed56c
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcls-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VCLS instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vcls-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vcls-bad.l b/gas/testsuite/gas/arm/mve-vcls-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..c58d34f6cf1a95e6b4f37ff410b647ae095c17c8
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcls-bad.l
@@ -0,0 +1,17 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vcls.f32 q0,q1'
+[^:]*:11: Error: bad type in SIMD instruction -- `vcls.u32 q0,q1'
+[^:]*:12: Error: bad type in SIMD instruction -- `vcls.32 q0,q1'
+[^:]*:13: Error: bad type in SIMD instruction -- `vcls.i32 q0,q1'
+[^:]*:14: Error: bad type in SIMD instruction -- `vcls.s64 q0,q1'
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Error: syntax error -- `vclseq.s16 q0,q1'
+[^:]*:18: Error: syntax error -- `vclseq.s16 q0,q1'
+[^:]*:20: Error: syntax error -- `vclseq.s16 q0,q1'
+[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vclst.s16 q0,q1'
+[^:]*:23: Error: instruction missing MVE vector predication code -- `vcls.s16 q0,q1'
diff --git a/gas/testsuite/gas/arm/mve-vcls-bad.s b/gas/testsuite/gas/arm/mve-vcls-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..a3cb1be59d21c3cbd04a462496bd0c425aa97f77
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcls-bad.s
@@ -0,0 +1,24 @@
+.macro cond
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vcls.s32 q0, q1
+.endr
+.endm
+
+.syntax unified
+.thumb
+vcls.f32 q0, q1
+vcls.u32 q0, q1
+vcls.32 q0, q1
+vcls.i32 q0, q1
+vcls.s64 q0, q1
+cond
+it eq
+vclseq.s16 q0, q1
+vclseq.s16 q0, q1
+vpst
+vclseq.s16 q0, q1
+vclst.s16 q0, q1
+vpst
+vcls.s16 q0, q1
+
diff --git a/gas/testsuite/gas/arm/mve-vclz-bad.d b/gas/testsuite/gas/arm/mve-vclz-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..72f37da2c9ee0a3dd9c09cd0c45c8156ab98c1d8
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vclz-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VCLZ instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vclz-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vclz-bad.l b/gas/testsuite/gas/arm/mve-vclz-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..aa68b0f5f7d8c4f3a409f2c37f1a44fc2a018142
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vclz-bad.l
@@ -0,0 +1,14 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vclz.f32 q0,q1'
+[^:]*:11: Error: bad type in SIMD instruction -- `vclz.i64 q0,q1'
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Error: syntax error -- `vclzeq.i16 q0,q1'
+[^:]*:15: Error: syntax error -- `vclzeq.i16 q0,q1'
+[^:]*:17: Error: syntax error -- `vclzeq.i16 q0,q1'
+[^:]*:18: Error: vector predicated instruction should be in VPT/VPST block -- `vclzt.i16 q0,q1'
+[^:]*:20: Error: instruction missing MVE vector predication code -- `vclz.i16 q0,q1'
diff --git a/gas/testsuite/gas/arm/mve-vclz-bad.s b/gas/testsuite/gas/arm/mve-vclz-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..088e831afa2ca6c3227e871c7c61f849704fe9cf
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vclz-bad.s
@@ -0,0 +1,20 @@
+.macro cond
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vclz.i32 q0, q1
+.endr
+.endm
+
+.syntax unified
+.thumb
+vclz.f32 q0, q1
+vclz.i64 q0, q1
+cond
+it eq
+vclzeq.i16 q0, q1
+vclzeq.i16 q0, q1
+vpst
+vclzeq.i16 q0, q1
+vclzt.i16 q0, q1
+vpst
+vclz.i16 q0, q1
diff --git a/gas/testsuite/gas/arm/mve-vfmas-bad.d b/gas/testsuite/gas/arm/mve-vfmas-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..dd3510f87ec10d0db605a4b8f9b93943c4031146
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vfmas-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE FP VFMAS instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vfmas-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vfmas-bad.l b/gas/testsuite/gas/arm/mve-vfmas-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..6a9b1f4313e611d3f213023bb9d0745492e8ccc9
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vfmas-bad.l
@@ -0,0 +1,16 @@
+[^:]*: Assembler messages:
+[^:]*:10: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:11: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:12: Error: bad type in SIMD instruction -- `vfmas.i32 q0,q1,r2'
+[^:]*:13: Error: bad type in SIMD instruction -- `vfmas.f64 q0,q1,r2'
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Error: syntax error -- `vfmaseq.f32 q0,q1,r2'
+[^:]*:17: Error: syntax error -- `vfmaseq.f32 q0,q1,r2'
+[^:]*:19: Error: syntax error -- `vfmaseq.f32 q0,q1,r2'
+[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vfmast.f32 q0,q1,r2'
+[^:]*:22: Error: instruction missing MVE vector predication code -- `vfmas.f32 q0,q1,r2'
diff --git a/gas/testsuite/gas/arm/mve-vfmas-bad.s b/gas/testsuite/gas/arm/mve-vfmas-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..15f894a6f65f9473ed5e04efabf6908e6342cb68
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vfmas-bad.s
@@ -0,0 +1,22 @@
+.macro cond
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vfmas.f32 q0, q1, r2
+.endr
+.endm
+
+.syntax unified
+.thumb
+vfmas.f32 q0, q1, sp
+vfmas.f32 q0, q1, pc
+vfmas.i32 q0, q1, r2
+vfmas.f64 q0, q1, r2
+cond
+it eq
+vfmaseq.f32 q0, q1, r2
+vfmaseq.f32 q0, q1, r2
+vpst
+vfmaseq.f32 q0, q1, r2
+vfmast.f32 q0, q1, r2
+vpst
+vfmas.f32 q0, q1, r2
next prev parent reply other threads:[~2019-05-01 17:09 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-01 16:51 [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 16:53 ` [PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fp Andre Vieira (lists)
2019-05-01 16:55 ` [PATCH 2/57][Arm][GAS] Add support for MVE instructions: vpst, vadd, vsub and vabd Andre Vieira (lists)
2019-05-02 10:56 ` Nick Clifton
2019-05-13 13:42 ` Andre Vieira (lists)
[not found] ` <98e50dc4-7b0e-d727-0c20-34711be86533@redhat.com>
[not found] ` <4e56a5f3-bcde-f4cd-21d4-35cc3f11b5e8@arm.com>
2019-05-14 16:53 ` Nick Clifton
2019-05-14 16:54 ` Nick Clifton
2019-05-01 16:56 ` [PATCH 3/57][Arm][GAS] Add support for MVE instructions: vabs and vneg Andre Vieira (lists)
2019-05-01 16:57 ` [PATCH 4/57][Arm][GAS] Add support for MVE instructions: vabav, vmladav and vmlsdav Andre Vieira (lists)
2019-05-01 16:59 ` [PATCH 5/57][Arm][GAS] Add support for MVE instructions: vmull{b,t} Andre Vieira (lists)
2019-05-01 17:00 ` [PATCH 6/57][Arm][GAS] Add support for MVE instructions: vst/vld{2,4} Andre Vieira (lists)
2019-05-01 17:01 ` [PATCH 7/57][Arm][GAS] Add support for MVE instructions: vstr/vldr Andre Vieira (lists)
2019-05-01 17:02 ` [PATCH 8/57][Arm][GAS] Add support for MVE instructions: vcvt Andre Vieira (lists)
2019-05-01 17:03 ` [PATCH 9/57][Arm][GAS] Add support for MVE instructions: vmov Andre Vieira (lists)
2019-05-01 17:03 ` [PATCH 10/57][Arm][GAS] Add support for MVE instructions: vcmp and vpt Andre Vieira (lists)
2019-05-01 17:05 ` [PATCH 11/57][Arm][GAS] Add support for MVE instructions: vadc, vsbc and vbrsr Andre Vieira (lists)
2019-05-01 17:06 ` [PATCH 12/57][Arm][GAS] Add support for MVE instructions: vaddlv and vaddv Andre Vieira (lists)
2019-05-01 17:07 ` [PATCH 13/57][Arm][GAS] Add support for MVE instructions: vand, vbic, vorr, vorn and veor Andre Vieira (lists)
2019-05-01 17:08 ` [PATCH 14/57][Arm][GAS] Add support for MVE instructions: vcadd, vcmla and vcmul Andre Vieira (lists)
2019-05-01 17:09 ` [PATCH 16/57][Arm][GAS] Add support for MVE instructions: vdup, vddup, vdwdup, vidup and viwdup Andre Vieira (lists)
2019-05-01 17:09 ` Andre Vieira (lists) [this message]
2019-05-01 17:11 ` [PATCH 17/57][Arm][GAS] Add support for MVE instructions: vfma and vfms Andre Vieira (lists)
2019-05-01 17:12 ` [PATCH 18/57][Arm][GAS] Add support for MVE instructions: vhcadd, vhadd, vhsub and vrhadd Andre Vieira (lists)
2019-05-01 17:12 ` [PATCH 19/57][Arm][GAS] Add support for MVE instructions: vmax[nm][a] and vmin[nm][a] Andre Vieira (lists)
2019-05-01 17:13 ` [PATCH 21/57][Arm][GAS] Add support for MVE instructions: vmaxv, vmaxav, vminv and vminav Andre Vieira (lists)
2019-05-01 17:13 ` [PATCH 20/57][Arm][GAS] Add support for MVE instructions: vmaxnmv, vmaxnmav, vminnmv and vminnmav Andre Vieira (lists)
2019-05-01 17:15 ` [PATCH 22/57][Arm][GAS] Add support for MVE instructions: vmlaldav, vmlalv, vmlsldav, vrmlaldavh, vrmlalvh and vrmlsldavh Andre Vieira (lists)
2019-05-01 17:15 ` [PATCH 23/57][Arm][GAS] Add support for MVE instructions: vmla, vmul, vqadd and vqsub Andre Vieira (lists)
2019-05-01 17:16 ` [PATCH 24/57][Arm][GAS] Add support for MVE instructions: vmlas, vmulh and vrmulh Andre Vieira (lists)
2019-05-01 17:17 ` [PATCH 26/57][Arm][GAS] Add support for MVE instructions: vpnot and vpsel Andre Vieira (lists)
2019-05-01 17:17 ` [PATCH 25/57][Arm][GAS] Add support for MVE instruction: vmvn, vqabs and vqneg Andre Vieira (lists)
2019-05-01 17:18 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 17:19 ` [PATCH 28/57][Arm][GAS] Add support for MVE instructions: vqdmlah, vqrdmlah, vqdmlash, vqrdmlash, vqdmulh and vqrdmulh Andre Vieira (lists)
2019-05-01 17:30 ` [PATCH 27/57][Arm][GAS] Add support for MVE instructions: vqdmladh, vqrdmladh, vqdmlsdh and vqrdmlsdh Andre Vieira (lists)
2019-05-01 17:31 ` [PATCH 29/57][Arm][GAS] Add support for MVE instructions: vqdmullt and vqdmullb Andre Vieira (lists)
2019-05-01 17:32 ` [PATCH 31/57][Arm][GAS] Add support for MVE instructions: vshrn[tb], vrshrn[tb], vqshrn[tb], vqshrun[tb], vqrshrn[tb] and vqrshrun[tb] Andre Vieira (lists)
2019-05-01 17:32 ` [PATCH 30/57][Arm][GAS] Add support for MVE instructions: vqmovnt, vqmovnb, vqmovunt, vqmovunb, vqrshl and vrshl Andre Vieira (lists)
2019-05-01 17:33 ` [PATCH 32/57][Arm][GAS] Add support for MVE instructions: vrintn, vrintx, vrinta, vrintz, vrintm and vrintp Andre Vieira (lists)
2019-05-01 17:34 ` [PATCH 34/57][Arm][GAS] Add support for MVE instructions: vshl and vqshl Andre Vieira (lists)
2019-05-01 17:34 ` [PATCH 33/57][Arm][GAS] Add support for MVE instructions: vshr, vrshr, vsli, vsri, vrev16, vrev32 and vrev64 Andre Vieira (lists)
2019-05-01 17:36 ` [PATCH 35/57][Arm][GAS] Add support for MVE instructions: vshlc and vshll Andre Vieira (lists)
2019-05-01 17:36 ` [PATCH 36/57][Arm][GAS] Add support for MVE instructions: wlstp, dlstp, letp and lctp Andre Vieira (lists)
2019-05-01 17:38 ` [PATCH 37/57][Arm][OBJDUMP] Add framework for MVE instructions Andre Vieira (lists)
2019-05-01 17:38 ` [PATCH 38/57][Arm][OBJDUMP] Disable the use of MVE reserved coproc numbers in coprocessor instructions Andre Vieira (lists)
2019-05-01 17:39 ` [PATCH 39/57][Arm][OBJDUMP] Add support for MVE instructions: vpt, vpst and vcmp Andre Vieira (lists)
2019-05-01 17:40 ` [PATCH 40/57][Arm][OBJDUMP] Add support for MVE instructions: vdup, veor, vfma, vfms, vhadd, vhsub and vrhadd Andre Vieira (lists)
2019-05-01 17:40 ` [PATCH 41/57][Arm][OBJDUMP] Add support for MVE instructions: vld[24] and vst[24] Andre Vieira (lists)
2019-05-01 17:41 ` [PATCH 42/57][Arm][OBJDUMP] Add support for MVE instructions: vldr[bhw] and vstr[bhw] Andre Vieira (lists)
2019-05-01 17:42 ` [PATCH 43/57][Arm][OBJDUMP] Add support for MVE instructions: scatter stores and gather loads Andre Vieira (lists)
2019-05-01 17:43 ` [PATCH 44/57][Arm][OBJDUMP] Add support for MVE instructions: vcvt and vrint Andre Vieira (lists)
2019-05-02 9:54 ` Nick Clifton
2019-05-13 13:38 ` Andre Vieira (lists)
2019-05-01 17:44 ` [PATCH 46/57][Arm][OBJDUMP] Add support for MVE instructions: vmovl, vmull, vqdmull, vqmovn, vqmovun and vmovn Andre Vieira (lists)
2019-05-01 17:44 ` [PATCH 45/57][Arm][OBJDUMP] Add support for MVE instructions: vmov, vmvn, vorr, vorn, vmovx and vbic Andre Vieira (lists)
2019-05-01 17:45 ` [PATCH 47/57][Arm][OBJDUMP] Add support for MVE instructions: vaddv, vmlaldav, vmladav, vmlas, vrmlsldavh, vmlsldav, vmlsdav, vrmlaldavh, vqdmlah, vqrdmlash, vqrdmlash, vqdmlsdh, vqrdmlsdh, vqdmulh and vqrdmulh Andre Vieira (lists)
2019-05-01 17:46 ` [PATCH 49/57][Arm][OBJDUMP] Add support for MVE complex number instructions Andre Vieira (lists)
2019-05-01 17:46 ` [PATCH 48/57][Arm][OBJDUMP] Add support for MVE instructions: vddup, vdwdup, vidup and viwdup Andre Vieira (lists)
2019-05-01 17:47 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 17:48 ` [PATCH 52/57][Arm][OBJDUMP] Add support for MVE instructions: vadc, vabav, vabd, vabs, vadd, vsbc and vsub Andre Vieira (lists)
2019-05-01 17:48 ` [PATCH 51/57][Arm][OBJDUMP] Add support for MVE instructions: lctp, letp, wlstp and dlstp Andre Vieira (lists)
2019-05-01 17:49 ` [PATCH 53/57][Arm][OBJDUMP] Add support for MVE instructions: vand, vbrsr, vcls, vclz and vctp Andre Vieira (lists)
2019-05-01 17:50 ` [PATCH 54/57][Arm][OBJDUMP] Add support for MVE instructions: vmax(a), vmax(a)v, vmaxnm(a), vmaxnm(a)v, vmin(a), vmin(a)v, vminnm(a), vminnm(a)v and vmla Andre Vieira (lists)
2019-05-01 17:50 ` [PATCH 55/57][Arm][OBJDUMP] Add support for MVE instructions: vmul, vmulh, vrmulh and vneg Andre Vieira (lists)
2019-05-01 17:51 ` [PATCH 56/57][Arm][OBJDUMP] Add support for MVE instructions: vpnot, vpsel, vqabs, vqadd, vqsub, vqneg and vrev Andre Vieira (lists)
2019-05-01 18:23 ` [PATCH 57/57][Arm][GAS] MVE Tests Andre Vieira (lists)
2019-05-01 18:24 ` Andre Vieira (lists)
2019-05-01 18:25 ` Andre Vieira (lists)
2019-05-01 18:25 ` Andre Vieira (lists)
2019-05-02 10:03 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Nick Clifton
2019-05-02 10:18 ` Nick Clifton
2019-05-13 13:39 ` [PATCH, binutils, Arm] Add Armv8.1-M Mainline and MVE enablement to NEWS Andre Vieira (lists)
2019-05-02 13:39 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Nick Clifton
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