From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 22596 invoked by alias); 1 May 2019 17:09:26 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 22587 invoked by uid 89); 1 May 2019 17:09:26 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.0 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LOTSOFHASH,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 01 May 2019 17:09:24 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DC48380D for ; Wed, 1 May 2019 10:09:22 -0700 (PDT) Received: from [10.2.207.62] (e107157-lin.cambridge.arm.com [10.2.207.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 60AE53F719 for ; Wed, 1 May 2019 10:09:22 -0700 (PDT) Subject: [PATCH 15/57][Arm][GAS] Add support for MVE instructions: vcls, vclz and vfmas To: binutils@sourceware.org References: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> From: "Andre Vieira (lists)" Message-ID: <3f18ee2c-76a9-6132-03fc-f555e1794c74@arm.com> Date: Wed, 01 May 2019 17:09:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> Content-Type: multipart/mixed; boundary="------------0AE08A129D626749D57691D0" X-IsSubscribed: yes X-SW-Source: 2019-05/txt/msg00044.txt.bz2 This is a multi-part message in MIME format. --------------0AE08A129D626749D57691D0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 785 Hi, This patch adds support for MVE instructions: VCLS, VCLZ, and VFMAS. gas/ChangeLog: 2019-05-01 Andre Vieira * config/tc-arm.c (do_mve_vfmas): New encoding function. (do_neon_cls): Change to support MVE variants. (do_neon_clz): Change to support MVE variants. (insns): Change to support MVE variants and add new. * testsuite/gas/arm/mve-vcls-bad.d: New test. * testsuite/gas/arm/mve-vcls-bad.l: New test. * testsuite/gas/arm/mve-vcls-bad.s: New test. * testsuite/gas/arm/mve-vclz-bad.d: New test. * testsuite/gas/arm/mve-vclz-bad.l: New test. * testsuite/gas/arm/mve-vclz-bad.s: New test. * testsuite/gas/arm/mve-vfmas-bad.d: New test. * testsuite/gas/arm/mve-vfmas-bad.l: New test. * testsuite/gas/arm/mve-vfmas-bad.s: New test. --------------0AE08A129D626749D57691D0 Content-Type: text/x-patch; name="15.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="15.patch" Content-length: 10428 diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 8d61ab3f1c5017294c36524047137c410dae32a6..e739c5b94ab1924f65a262e15342a748e2a4dc40 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -15582,6 +15582,32 @@ do_mve_vcmp (void) return; } +static void +do_mve_vfmas (void) +{ + enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); + struct neon_type_el et + = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK, N_EQK); + + if (inst.cond > COND_ALWAYS) + inst.pred_insn_type = INSIDE_VPT_INSN; + else + inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; + + if (inst.operands[2].reg == REG_SP) + as_tsktsk (MVE_BAD_SP); + else if (inst.operands[2].reg == REG_PC) + as_tsktsk (MVE_BAD_PC); + + inst.instruction |= (et.size == 16) << 28; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[1].reg) << 16; + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[1].reg) << 7; + inst.instruction |= inst.operands[2].reg; + inst.is_neon = 1; +} + static void do_mve_vcmul (void) { @@ -19006,7 +19032,15 @@ do_neon_recip_est (void) static void do_neon_cls (void) { - enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); + if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC)) + return; + + enum neon_shape rs; + if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) + rs = neon_select_shape (NS_QQ, NS_NULL); + else + rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); neon_two_same (neon_quad (rs), 1, et.size); @@ -19015,7 +19049,15 @@ do_neon_cls (void) static void do_neon_clz (void) { - enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); + if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC)) + return; + + enum neon_shape rs; + if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) + rs = neon_select_shape (NS_QQ, NS_NULL); + else + rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); neon_two_same (neon_quad (rs), 1, et.size); @@ -23648,10 +23690,8 @@ static const struct asm_opcode insns[] = NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), /* VCLS. Types S8 S16 S32. */ - NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), /* VCLZ. Types I8 I16 I32. */ - NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), /* VCNT. Size 8. */ NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), @@ -24185,6 +24225,7 @@ static const struct asm_opcode insns[] = #undef THUMB_VARIANT #define THUMB_VARIANT & mve_fp_ext mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul), + mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas), #undef ARM_VARIANT #define ARM_VARIANT & fpu_vfp_ext_v1 @@ -24240,6 +24281,8 @@ static const struct asm_opcode insns[] = mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic), mnUF(vorn, _vorn, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic), mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic), + MNUF(vcls, 1b00400, 2, (RNDQMQ, RNDQMQ), neon_cls), + MNUF(vclz, 1b00480, 2, (RNDQMQ, RNDQMQ), neon_clz), #undef ARM_VARIANT #define ARM_VARIANT & arm_ext_v8_3 diff --git a/gas/testsuite/gas/arm/mve-vcls-bad.d b/gas/testsuite/gas/arm/mve-vcls-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..0cfdabd7a5f8c3152cd704eb1a68dfda40bed56c --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcls-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE VCLS instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vcls-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vcls-bad.l b/gas/testsuite/gas/arm/mve-vcls-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..c58d34f6cf1a95e6b4f37ff410b647ae095c17c8 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcls-bad.l @@ -0,0 +1,17 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vcls.f32 q0,q1' +[^:]*:11: Error: bad type in SIMD instruction -- `vcls.u32 q0,q1' +[^:]*:12: Error: bad type in SIMD instruction -- `vcls.32 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vcls.i32 q0,q1' +[^:]*:14: Error: bad type in SIMD instruction -- `vcls.s64 q0,q1' +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Error: syntax error -- `vclseq.s16 q0,q1' +[^:]*:18: Error: syntax error -- `vclseq.s16 q0,q1' +[^:]*:20: Error: syntax error -- `vclseq.s16 q0,q1' +[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vclst.s16 q0,q1' +[^:]*:23: Error: instruction missing MVE vector predication code -- `vcls.s16 q0,q1' diff --git a/gas/testsuite/gas/arm/mve-vcls-bad.s b/gas/testsuite/gas/arm/mve-vcls-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..a3cb1be59d21c3cbd04a462496bd0c425aa97f77 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vcls-bad.s @@ -0,0 +1,24 @@ +.macro cond +.irp cond, eq, ne, gt, ge, lt, le +it \cond +vcls.s32 q0, q1 +.endr +.endm + +.syntax unified +.thumb +vcls.f32 q0, q1 +vcls.u32 q0, q1 +vcls.32 q0, q1 +vcls.i32 q0, q1 +vcls.s64 q0, q1 +cond +it eq +vclseq.s16 q0, q1 +vclseq.s16 q0, q1 +vpst +vclseq.s16 q0, q1 +vclst.s16 q0, q1 +vpst +vcls.s16 q0, q1 + diff --git a/gas/testsuite/gas/arm/mve-vclz-bad.d b/gas/testsuite/gas/arm/mve-vclz-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..72f37da2c9ee0a3dd9c09cd0c45c8156ab98c1d8 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vclz-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE VCLZ instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vclz-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vclz-bad.l b/gas/testsuite/gas/arm/mve-vclz-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..aa68b0f5f7d8c4f3a409f2c37f1a44fc2a018142 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vclz-bad.l @@ -0,0 +1,14 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vclz.f32 q0,q1' +[^:]*:11: Error: bad type in SIMD instruction -- `vclz.i64 q0,q1' +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Error: syntax error -- `vclzeq.i16 q0,q1' +[^:]*:15: Error: syntax error -- `vclzeq.i16 q0,q1' +[^:]*:17: Error: syntax error -- `vclzeq.i16 q0,q1' +[^:]*:18: Error: vector predicated instruction should be in VPT/VPST block -- `vclzt.i16 q0,q1' +[^:]*:20: Error: instruction missing MVE vector predication code -- `vclz.i16 q0,q1' diff --git a/gas/testsuite/gas/arm/mve-vclz-bad.s b/gas/testsuite/gas/arm/mve-vclz-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..088e831afa2ca6c3227e871c7c61f849704fe9cf --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vclz-bad.s @@ -0,0 +1,20 @@ +.macro cond +.irp cond, eq, ne, gt, ge, lt, le +it \cond +vclz.i32 q0, q1 +.endr +.endm + +.syntax unified +.thumb +vclz.f32 q0, q1 +vclz.i64 q0, q1 +cond +it eq +vclzeq.i16 q0, q1 +vclzeq.i16 q0, q1 +vpst +vclzeq.i16 q0, q1 +vclzt.i16 q0, q1 +vpst +vclz.i16 q0, q1 diff --git a/gas/testsuite/gas/arm/mve-vfmas-bad.d b/gas/testsuite/gas/arm/mve-vfmas-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..dd3510f87ec10d0db605a4b8f9b93943c4031146 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vfmas-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE FP VFMAS instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vfmas-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vfmas-bad.l b/gas/testsuite/gas/arm/mve-vfmas-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..6a9b1f4313e611d3f213023bb9d0745492e8ccc9 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vfmas-bad.l @@ -0,0 +1,16 @@ +[^:]*: Assembler messages: +[^:]*:10: Warning: instruction is UNPREDICTABLE with SP operand +[^:]*:11: Warning: instruction is UNPREDICTABLE with PC operand +[^:]*:12: Error: bad type in SIMD instruction -- `vfmas.i32 q0,q1,r2' +[^:]*:13: Error: bad type in SIMD instruction -- `vfmas.f64 q0,q1,r2' +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Error: syntax error -- `vfmaseq.f32 q0,q1,r2' +[^:]*:17: Error: syntax error -- `vfmaseq.f32 q0,q1,r2' +[^:]*:19: Error: syntax error -- `vfmaseq.f32 q0,q1,r2' +[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vfmast.f32 q0,q1,r2' +[^:]*:22: Error: instruction missing MVE vector predication code -- `vfmas.f32 q0,q1,r2' diff --git a/gas/testsuite/gas/arm/mve-vfmas-bad.s b/gas/testsuite/gas/arm/mve-vfmas-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..15f894a6f65f9473ed5e04efabf6908e6342cb68 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vfmas-bad.s @@ -0,0 +1,22 @@ +.macro cond +.irp cond, eq, ne, gt, ge, lt, le +it \cond +vfmas.f32 q0, q1, r2 +.endr +.endm + +.syntax unified +.thumb +vfmas.f32 q0, q1, sp +vfmas.f32 q0, q1, pc +vfmas.i32 q0, q1, r2 +vfmas.f64 q0, q1, r2 +cond +it eq +vfmaseq.f32 q0, q1, r2 +vfmaseq.f32 q0, q1, r2 +vpst +vfmaseq.f32 q0, q1, r2 +vfmast.f32 q0, q1, r2 +vpst +vfmas.f32 q0, q1, r2 --------------0AE08A129D626749D57691D0--