Index: c-arc.texi =================================================================== RCS file: /cvs/src/src/gas/doc/c-arc.texi,v retrieving revision 1.3 diff -c -3 -p -r1.3 c-arc.texi *** c-arc.texi 12 May 2001 15:14:52 -0000 1.3 --- c-arc.texi 14 Jan 2005 07:43:17 -0000 *************** *** 1,4 **** ! @c Copyright 2000, 2001 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. --- 1,4 ---- ! @c Copyright 2000, 2001,2002,2003,2004 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. *************** default. *** 100,106 **** @cindex ARC register names @cindex register names, ARC ! *TODO* @node ARC Floating Point --- 100,106 ---- @cindex ARC register names @cindex register names, ARC ! *TODO* @node ARC Floating Point *************** machine directives: *** 137,143 **** @cindex @code{extAuxRegister} directive, ARC @item .extAuxRegister @var{name},@var{address},@var{mode} ! *TODO* @smallexample .extAuxRegister mulhi,0x12,w --- 137,153 ---- @cindex @code{extAuxRegister} directive, ARC @item .extAuxRegister @var{name},@var{address},@var{mode} ! The ARCtangent A4 has extensible auxiliary register space. The ! auxiliary registers can be defined in the assembler source code by ! @var{name}, the address of the register in the auxiliary register ! memory map for the variant of the ARC. The mode in which the register ! is to be operated is specified by @var{mode} which could be one of : ! ! @table ! @cindex @code{r} (readonly) , ARC ! @cindex @code{w} (write only), ARC ! @cindex @code{r|w} (read or write), ARC ! @end table @smallexample .extAuxRegister mulhi,0x12,w *************** machine directives: *** 145,170 **** @cindex @code{extCondCode} directive, ARC @item .extCondCode @var{suffix},@var{value} ! *TODO* @smallexample .extCondCode is_busy,0x14 @end smallexample @cindex @code{extCoreRegister} directive, ARC @item .extCoreRegister @var{name},@var{regnum},@var{mode},@var{shortcut} ! *TODO* @smallexample .extCoreRegister mlo,57,r,can_shortcut @end smallexample @cindex @code{extInstruction} directive, ARC ! @item .extInstruction @var{name},@var{opcode},@var{subopcode},@var{suffixclass},@var{syntaxclass} ! *TODO* @smallexample ! .extInstruction mul64,0x14,0x0,SUFFIX_COND,SYNTAX_3OP|OP1_MUST_BE_IMM @end smallexample @cindex @code{half} directive, ARC --- 155,250 ---- @cindex @code{extCondCode} directive, ARC @item .extCondCode @var{suffix},@var{value} ! The condition codes on the ARCtangent A4 are extensible and can be ! specified by means of assembler directives. These are specified by the ! suffix and the value for the condition code. These can be used to ! specify extra condition codes with any values. @smallexample .extCondCode is_busy,0x14 + add.is_busy r1,r2,r3 + bis_busy _main @end smallexample @cindex @code{extCoreRegister} directive, ARC @item .extCoreRegister @var{name},@var{regnum},@var{mode},@var{shortcut} ! Specify an extension core register @var{name} for the ! application. This allows a register @var{name} with a valid ! @var{regnum} between 0 and 60, with @var{mode} ! ! ! @table ! @cindex @code{r} (readonly) , ARC ! @cindex @code{w} (write only), ARC ! @cindex @code{r|w} (read or write), ARC ! @end table ! ! This also gives a description whether the register has a ! @var{shortcut} in the pipeline or not. The valid values of ! @var{shortcut} are @code{can_shortcut} and @code{cannot_shortcut}. @smallexample .extCoreRegister mlo,57,r,can_shortcut @end smallexample @cindex @code{extInstruction} directive, ARC ! @item .extInstruction @var{name},@var{opcode},@var{subopcode}, ! @var{suffixclass},@var{syntaxclass} The ARCtangent A4 allows ! the user to specify extension instructions . The extension ! instructions are not macros . The assembler creates encodings for ! use of these instructions according to the specification by the user. ! The parameters are : ! @var{name} : Name of the extension instruction ! @var{opcode} : Opcode to be used. (Bits 27:31 in the encoding) ! Valid values 0x10-0x1f or 0x03 ! @var{subopcode}: Subopcode to be used. (Bits ) Valid values from ! 0x09-0x3f .However the correct value also depends on ! @var{syntaxclass} ! @var{suffixclass} : Determines the kinds of suffixes to be allowed . ! Valid values are @code{SUFFIX_NONE} , @code{SUFFIX_COND}, @code{SUFFIX_FLAG} ! which indicates the absence or presence of conditional suffixes and ! flag setting by the extension instruction . It is also possible ! to specify that an instruction sets the flags and is conditional by ! using @code{SUFFIX_CODE} | @code{SUFFIX_FLAG} ! @var{syntaxclass} : Determines the syntax class for the instruction. ! It can have the following values. ! ! @code{SYNTAX_2OP}: 2 Operand Instruction ! @code{SYNTAX_3OP}: 3 Operand Instruction ! ! Syntax Class Modifiers are : ! @code{OP1_MUST_BE_IMM}: OP1_MUST_BE_IMM modifies syntax class ! SYNTAX_3OP, specifying that the first operand of a three-operand ! instruction must be an immediate (i.e. the result is discarded ). ! OP1_MUST_BE_IMM is used by bitwise ORing it with SYNTAX_3OP as given ! in the example below. This could usually be used to set the flags ! using specific instructions and not retain results. ! ! @code{OP1_IMM_IMPLIED}:OP1_IMM_IMPLIED modifies syntax class ! SYNTAX_20P, it specifies that there is an implied immediate ! destination operand which does not appear in the syntax. For ! example, if the source code contains an instruction like: ! inst r1,r2 ! ! it really means that the first argument is an implied immediate (that ! is, the result is discarded). This is the same as though the source ! code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it ! with SYNTAX_20P. ! @smallexample ! Defining MUL64 with immediate operands. ! .extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG ,SYNTAX_3OP|OP1_MUST_BE_IMM ! Specifies an extension instruction called mp64 which has 3 operands , ! sets the flags and can be used with a condition code for which the ! first operand is an immediate equivalent to discarding the result ! of the operation. ! ! .extInstruction mp64, .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED ! The same as above, the only difference being that of this being a 2 ! operand instruction with an implicit first immediate operand. The ! result of this operation would be discarded . ! @end smallexample @cindex @code{half} directive, ARC *************** between the two - even for the implicit *** 204,207 **** @cindex opcodes for ARC For information on the ARC instruction set, see @cite{ARC Programmers ! Reference Manual}, ARC Cores Ltd. --- 284,287 ---- @cindex opcodes for ARC For information on the ARC instruction set, see @cite{ARC Programmers ! Reference Manual}, ARC International (www.arc.com)