From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Cc: "H.J. Lu" <hjl.tools@gmail.com>
Subject: [PATCH 3/3] x86: drop LOCK from XCHG when optimizing
Date: Fri, 27 Jan 2023 12:36:02 +0100 [thread overview]
Message-ID: <44b896ee-5b03-1ed6-bda2-8cffec382810@suse.com> (raw)
In-Reply-To: <bea7bb2c-0fa1-6bc3-fb5c-223facaf47a2@suse.com>
Like with segment overrides on LEA, optimize away such a redundant
instruction prefix.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -5179,14 +5179,20 @@ md_assemble (char *line)
/* Check for lock without a lockable instruction. Destination operand
must be memory unless it is xchg (0x86). */
- if (i.prefix[LOCK_PREFIX]
- && (i.tm.opcode_modifier.prefixok < PrefixLock
+ if (i.prefix[LOCK_PREFIX])
+ {
+ if (i.tm.opcode_modifier.prefixok < PrefixLock
|| i.mem_operands == 0
|| (i.tm.base_opcode != 0x86
- && !(i.flags[i.operands - 1] & Operand_Mem))))
- {
- as_bad (_("expecting lockable instruction after `lock'"));
- return;
+ && !(i.flags[i.operands - 1] & Operand_Mem)))
+ {
+ as_bad (_("expecting lockable instruction after `lock'"));
+ return;
+ }
+
+ /* Zap the redundant prefix from XCHG when optimizing. */
+ if (i.tm.base_opcode == 0x86 && optimize && !i.no_optimize)
+ i.prefix[LOCK_PREFIX] = 0;
}
if (is_any_vex_encoding (&i.tm)
--- a/gas/testsuite/gas/i386/optimize-2.d
+++ b/gas/testsuite/gas/i386/optimize-2.d
@@ -22,6 +22,8 @@ Disassembly of section .text:
+[a-f0-9]+: 08 e4 or %ah,%ah
+[a-f0-9]+: 66 09 ed or %bp,%bp
+[a-f0-9]+: 09 f6 or %esi,%esi
+ +[a-f0-9]+: 87 0a xchg %ecx,\(%edx\)
+ +[a-f0-9]+: 87 11 xchg %edx,\(%ecx\)
+[a-f0-9]+: c5 f1 55 e9 vandnpd %xmm1,%xmm1,%xmm5
+[a-f0-9]+: c5 f9 6f d1 vmovdqa %xmm1,%xmm2
+[a-f0-9]+: c5 f9 6f d1 vmovdqa %xmm1,%xmm2
--- a/gas/testsuite/gas/i386/optimize-2.s
+++ b/gas/testsuite/gas/i386/optimize-2.s
@@ -20,6 +20,9 @@ _start:
or %bp, %bp
or %esi, %esi
+ lock xchg %ecx, (%edx)
+ lock xchg (%ecx), %edx
+
vandnpd %zmm1, %zmm1, %zmm5
vmovdqa32 %xmm1, %xmm2
--- a/gas/testsuite/gas/i386/optimize-2b.d
+++ b/gas/testsuite/gas/i386/optimize-2b.d
@@ -23,6 +23,8 @@ Disassembly of section .text:
+[a-f0-9]+: 84 e4 test %ah,%ah
+[a-f0-9]+: 66 85 ed test %bp,%bp
+[a-f0-9]+: 85 f6 test %esi,%esi
+ +[a-f0-9]+: 87 0a xchg %ecx,\(%edx\)
+ +[a-f0-9]+: 87 11 xchg %edx,\(%ecx\)
+[a-f0-9]+: c5 f1 55 e9 vandnpd %xmm1,%xmm1,%xmm5
+[a-f0-9]+: c5 f9 6f d1 vmovdqa %xmm1,%xmm2
+[a-f0-9]+: c5 f9 6f d1 vmovdqa %xmm1,%xmm2
--- a/gas/testsuite/gas/i386/optimize-3.d
+++ b/gas/testsuite/gas/i386/optimize-3.d
@@ -9,6 +9,8 @@ Disassembly of section .text:
0+ <_start>:
+[a-f0-9]+: a9 7f 00 00 00 test \$0x7f,%eax
+ +[a-f0-9]+: f0 87 0a lock xchg %ecx,\(%edx\)
+ +[a-f0-9]+: f0 87 11 lock xchg %edx,\(%ecx\)
+[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2
+[a-f0-9]+: 62 f1 fd 28 6f d1 vmovdqa64 %ymm1,%ymm2
+[a-f0-9]+: 62 f1 7f 08 6f d1 vmovdqu8 %xmm1,%xmm2
--- a/gas/testsuite/gas/i386/optimize-3.s
+++ b/gas/testsuite/gas/i386/optimize-3.s
@@ -5,6 +5,9 @@
_start:
{nooptimize} testl $0x7f, %eax
+ {nooptimize} lock xchg %ecx, (%edx)
+ {nooptimize} lock xchg (%ecx), %edx
+
{nooptimize} vmovdqa32 %ymm1, %ymm2
{nooptimize} vmovdqa64 %ymm1, %ymm2
{nooptimize} vmovdqu8 %xmm1, %xmm2
prev parent reply other threads:[~2023-01-27 11:36 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-27 11:34 [PATCH 0/3] x86: small adjustments to optimization logic Jan Beulich
2023-01-27 11:35 ` [PATCH 1/3] x86: respect {nooptimize} for LEA Jan Beulich
2023-01-27 11:35 ` [PATCH 2/3] x86-64: respect {nooptimize} when building VEX prefix Jan Beulich
2023-01-27 11:36 ` Jan Beulich [this message]
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