* Re: [Binutils][AARCH64][1/2]Add group relocations to create PC-relative offset.
2018-01-18 15:34 [Binutils][AARCH64][0/2]Add group relocations to create PC-relative offset Renlin Li
@ 2018-01-18 15:38 ` Renlin Li
2018-01-22 13:22 ` Nick Clifton
2018-01-18 15:39 ` [Binutils][AARCH64][2/2]Add " Renlin Li
1 sibling, 1 reply; 6+ messages in thread
From: Renlin Li @ 2018-01-18 15:38 UTC (permalink / raw)
To: binutils, Ramana Radhakrishnan, Nicholas Clifton
[-- Attachment #1: Type: text/plain, Size: 3186 bytes --]
Hi all,
This is the assembler part support for the following relocations:
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3
Regards,
Renlin
bfd/
2018-01-18 Renlin Li <renlin.li@arm.com>
* reloc.c: Add BFD_RELOC_AARCH64_MOVW_PREL_G0,
BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1,
BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2,
BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Add entries for
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.
gas/
2018-01-18 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (reloc_table): add entries for
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.
(process_movw_reloc_info): Supports newly added MOVW_PREL relocations.
(md_apply_fix): Likewise
* testsuite/gas/aarch64/prel_g0.s: New.
* testsuite/gas/aarch64/prel_g0.d: New.
* testsuite/gas/aarch64/prel_g0_nc.s: New.
* testsuite/gas/aarch64/prel_g0_nc.d: New.
* testsuite/gas/aarch64/prel_g1.s: New.
* testsuite/gas/aarch64/prel_g1.d: New.
* testsuite/gas/aarch64/prel_g1_nc.s: New.
* testsuite/gas/aarch64/prel_g1_nc.d: New.
* testsuite/gas/aarch64/prel_g2.s: New.
* testsuite/gas/aarch64/prel_g2.d: New.
* testsuite/gas/aarch64/prel_g2_nc.s: New.
* testsuite/gas/aarch64/prel_g2_nc.d: New.
* testsuite/gas/aarch64/prel_g3.s: New.
* testsuite/gas/aarch64/prel_g3.d: New.
On 18/01/18 15:34, Renlin Li wrote:
> Hi all,
>
> This is a patch to add Group relocations to create a
> 16, 32, 48, or 64 bit PC-relative offset inline.
>
> The following relocations are added along with the test cases:
> BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
> BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
> BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
> BFD_RELOC_AARCH64_MOVW_PREL_G3.
>
>
> The operations for those relocations are: S + A - P.
> S is the address of the symbol.
> A is the addend for the relocation.
> P is the address of the place being relocated
>
> Those relocations are used to create PC-relative offset. For example,
> The following code sequence could get the full address of _start.
>
> .Ltmp1:
> movz   x0, :prel_g2: _start - .Ltmp1
> movk   x0, :prel_g1_nc: _start - .Ltmp1
> movk   x0, :prel_g0_nc: _start - .Ltmp1
> adr   x1, .Ltmp1
> add   x0, x0, x1
>
> binutils regression test checked OK, linux kernel link checked OK.
> OK to commit?
>
> Regards,
> Renlin
[-- Attachment #2: 0001-GAS-AARCH64-Add-group-relocations-to-create-PC-relat.patch --]
[-- Type: text/x-patch, Size: 21782 bytes --]
---
bfd/bfd-in2.h | 30 ++++++++
bfd/elfnn-aarch64.c | 108 +++++++++++++++++++++++++++
bfd/libbfd.h | 7 ++
bfd/reloc.c | 37 +++++++++
gas/config/tc-aarch64.c | 84 +++++++++++++++++++++
gas/testsuite/gas/aarch64/reloc-prel_g0.d | 13 ++++
gas/testsuite/gas/aarch64/reloc-prel_g0.s | 7 ++
gas/testsuite/gas/aarch64/reloc-prel_g0_nc.d | 15 ++++
gas/testsuite/gas/aarch64/reloc-prel_g0_nc.s | 8 ++
gas/testsuite/gas/aarch64/reloc-prel_g1.d | 13 ++++
gas/testsuite/gas/aarch64/reloc-prel_g1.s | 7 ++
gas/testsuite/gas/aarch64/reloc-prel_g1_nc.d | 15 ++++
gas/testsuite/gas/aarch64/reloc-prel_g1_nc.s | 8 ++
gas/testsuite/gas/aarch64/reloc-prel_g2.d | 15 ++++
gas/testsuite/gas/aarch64/reloc-prel_g2.s | 8 ++
gas/testsuite/gas/aarch64/reloc-prel_g2_nc.d | 15 ++++
gas/testsuite/gas/aarch64/reloc-prel_g2_nc.s | 8 ++
gas/testsuite/gas/aarch64/reloc-prel_g3.d | 15 ++++
gas/testsuite/gas/aarch64/reloc-prel_g3.s | 8 ++
21 files changed, 459 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g0.d
create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g0.s
create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g0_nc.d
create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g0_nc.s
create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g1.d
create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g1.s
create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g1_nc.d
create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g1_nc.s
create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g2.d
create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g2.s
create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g2_nc.d
create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g2_nc.s
create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g3.d
create mode 100644 gas/testsuite/gas/aarch64/reloc-prel_g3.s
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index f4b3720..42991e7 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -5957,6 +5957,36 @@ of a signed value. Changes instruction to MOVZ or MOVN depending on the
value's sign. */
BFD_RELOC_AARCH64_MOVW_G2_S,
+/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15
+of a signed value. Changes instruction to MOVZ or MOVN depending on the
+value's sign. */
+ BFD_RELOC_AARCH64_MOVW_PREL_G0,
+
+/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15
+of a signed value. Changes instruction to MOVZ or MOVN depending on the
+value's sign. */
+ BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
+
+/* AArch64 MOVK instruction with most significant bits 16 to 31
+of a signed value. */
+ BFD_RELOC_AARCH64_MOVW_PREL_G1,
+
+/* AArch64 MOVK instruction with most significant bits 16 to 31
+of a signed value. */
+ BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
+
+/* AArch64 MOVK instruction with most significant bits 32 to 47
+of a signed value. */
+ BFD_RELOC_AARCH64_MOVW_PREL_G2,
+
+/* AArch64 MOVK instruction with most significant bits 32 to 47
+of a signed value. */
+ BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
+
+/* AArch64 MOVK instruction with most significant bits 47 to 63
+of a signed value. */
+ BFD_RELOC_AARCH64_MOVW_PREL_G3,
+
/* AArch64 Load Literal instruction, holding a 19 bit pc-relative word
offset. The lowest two bits must be zero and are not stored in the
instruction, giving a 21 bit signed byte offset. */
diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c
index d5711e0..b84c8ba 100644
--- a/bfd/elfnn-aarch64.c
+++ b/bfd/elfnn-aarch64.c
@@ -617,6 +617,114 @@ static reloc_howto_type elfNN_aarch64_howto_table[] =
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
+ /* Group relocations to create a 16, 32, 48 or 64 bit
+ PC relative address inline. */
+
+ /* MOV[NZ]: ((S+A-P) >> 0) & 0xffff */
+ HOWTO64 (AARCH64_R (MOVW_PREL_G0), /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 17, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ AARCH64_R_STR (MOVW_PREL_G0), /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* MOVK: ((S+A-P) >> 0) & 0xffff [no overflow check] */
+ HOWTO64 (AARCH64_R (MOVW_PREL_G0_NC), /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ AARCH64_R_STR (MOVW_PREL_G0_NC), /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* MOV[NZ]: ((S+A-P) >> 16) & 0xffff */
+ HOWTO64 (AARCH64_R (MOVW_PREL_G1), /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 17, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ AARCH64_R_STR (MOVW_PREL_G1), /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* MOVK: ((S+A-P) >> 16) & 0xffff [no overflow check] */
+ HOWTO64 (AARCH64_R (MOVW_PREL_G1_NC), /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ AARCH64_R_STR (MOVW_PREL_G1_NC), /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* MOV[NZ]: ((S+A-P) >> 32) & 0xffff */
+ HOWTO64 (AARCH64_R (MOVW_PREL_G2), /* type */
+ 32, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 17, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ AARCH64_R_STR (MOVW_PREL_G2), /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* MOVK: ((S+A-P) >> 32) & 0xffff [no overflow check] */
+ HOWTO64 (AARCH64_R (MOVW_PREL_G2_NC), /* type */
+ 32, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ AARCH64_R_STR (MOVW_PREL_G2_NC), /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* MOV[NZ]: ((S+A-P) >> 48) & 0xffff */
+ HOWTO64 (AARCH64_R (MOVW_PREL_G3), /* type */
+ 48, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ AARCH64_R_STR (MOVW_PREL_G3), /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
/* Relocations to generate 19, 21 and 33 bit PC-relative load/store
addresses: PG(x) is (x & ~0xfff). */
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 2f5f16e..8746d9c 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -2887,6 +2887,13 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_AARCH64_MOVW_G0_S",
"BFD_RELOC_AARCH64_MOVW_G1_S",
"BFD_RELOC_AARCH64_MOVW_G2_S",
+ "BFD_RELOC_AARCH64_MOVW_PREL_G0",
+ "BFD_RELOC_AARCH64_MOVW_PREL_G0_NC",
+ "BFD_RELOC_AARCH64_MOVW_PREL_G1",
+ "BFD_RELOC_AARCH64_MOVW_PREL_G1_NC",
+ "BFD_RELOC_AARCH64_MOVW_PREL_G2",
+ "BFD_RELOC_AARCH64_MOVW_PREL_G2_NC",
+ "BFD_RELOC_AARCH64_MOVW_PREL_G3",
"BFD_RELOC_AARCH64_LD_LO19_PCREL",
"BFD_RELOC_AARCH64_ADR_LO21_PCREL",
"BFD_RELOC_AARCH64_ADR_HI21_PCREL",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index a1353a2..301199a 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -7071,6 +7071,43 @@ ENUMDOC
of a signed value. Changes instruction to MOVZ or MOVN depending on the
value's sign.
ENUM
+ BFD_RELOC_AARCH64_MOVW_PREL_G0
+ENUMDOC
+ AArch64 MOV[NZ] instruction with most significant bits 0 to 15
+ of a signed value. Changes instruction to MOVZ or MOVN depending on the
+ value's sign.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
+ENUMDOC
+ AArch64 MOV[NZ] instruction with most significant bits 0 to 15
+ of a signed value. Changes instruction to MOVZ or MOVN depending on the
+ value's sign.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_PREL_G1
+ENUMDOC
+ AArch64 MOVK instruction with most significant bits 16 to 31
+ of a signed value.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
+ENUMDOC
+ AArch64 MOVK instruction with most significant bits 16 to 31
+ of a signed value.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_PREL_G2
+ENUMDOC
+ AArch64 MOVK instruction with most significant bits 32 to 47
+ of a signed value.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
+ENUMDOC
+ AArch64 MOVK instruction with most significant bits 32 to 47
+ of a signed value.
+ENUM
+ BFD_RELOC_AARCH64_MOVW_PREL_G3
+ENUMDOC
+ AArch64 MOVK instruction with most significant bits 47 to 63
+ of a signed value.
+ENUM
BFD_RELOC_AARCH64_LD_LO19_PCREL
ENUMDOC
AArch64 Load Literal instruction, holding a 19 bit pc-relative word
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 8af3137..3a0cde9 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -2577,6 +2577,69 @@ static struct reloc_table_entry reloc_table[] = {
0,
0},
+ /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
+ {"prel_g0", 1,
+ 0, /* adr_type */
+ 0,
+ BFD_RELOC_AARCH64_MOVW_PREL_G0,
+ 0,
+ 0,
+ 0},
+
+ /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
+ {"prel_g0_nc", 1,
+ 0, /* adr_type */
+ 0,
+ BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
+ 0,
+ 0,
+ 0},
+
+ /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
+ {"prel_g1", 1,
+ 0, /* adr_type */
+ 0,
+ BFD_RELOC_AARCH64_MOVW_PREL_G1,
+ 0,
+ 0,
+ 0},
+
+ /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
+ {"prel_g1_nc", 1,
+ 0, /* adr_type */
+ 0,
+ BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
+ 0,
+ 0,
+ 0},
+
+ /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
+ {"prel_g2", 1,
+ 0, /* adr_type */
+ 0,
+ BFD_RELOC_AARCH64_MOVW_PREL_G2,
+ 0,
+ 0,
+ 0},
+
+ /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
+ {"prel_g2_nc", 1,
+ 0, /* adr_type */
+ 0,
+ BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
+ 0,
+ 0,
+ 0},
+
+ /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
+ {"prel_g3", 1,
+ 0, /* adr_type */
+ 0,
+ BFD_RELOC_AARCH64_MOVW_PREL_G3,
+ 0,
+ 0,
+ 0},
+
/* Get to the page containing GOT entry for a symbol. */
{"got", 1,
0, /* adr_type */
@@ -5079,6 +5142,10 @@ process_movw_reloc_info (void)
case BFD_RELOC_AARCH64_MOVW_G0_S:
case BFD_RELOC_AARCH64_MOVW_G1_S:
case BFD_RELOC_AARCH64_MOVW_G2_S:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G0:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G1:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G2:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G3:
case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
@@ -5096,6 +5163,8 @@ process_movw_reloc_info (void)
case BFD_RELOC_AARCH64_MOVW_G0_NC:
case BFD_RELOC_AARCH64_MOVW_G0_S:
case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G0:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:
case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
@@ -5109,6 +5178,8 @@ process_movw_reloc_info (void)
case BFD_RELOC_AARCH64_MOVW_G1_NC:
case BFD_RELOC_AARCH64_MOVW_G1_S:
case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G1:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:
case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
@@ -5121,6 +5192,8 @@ process_movw_reloc_info (void)
case BFD_RELOC_AARCH64_MOVW_G2:
case BFD_RELOC_AARCH64_MOVW_G2_NC:
case BFD_RELOC_AARCH64_MOVW_G2_S:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G2:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:
case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
if (is32)
@@ -5133,6 +5206,7 @@ process_movw_reloc_info (void)
shift = 32;
break;
case BFD_RELOC_AARCH64_MOVW_G3:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G3:
if (is32)
{
set_fatal_syntax_error
@@ -7608,12 +7682,16 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
case BFD_RELOC_AARCH64_MOVW_G0_NC:
case BFD_RELOC_AARCH64_MOVW_G0_S:
case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G0:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:
scale = 0;
goto movw_common;
case BFD_RELOC_AARCH64_MOVW_G1:
case BFD_RELOC_AARCH64_MOVW_G1_NC:
case BFD_RELOC_AARCH64_MOVW_G1_S:
case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G1:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:
scale = 16;
goto movw_common;
case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
@@ -7635,9 +7713,12 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
case BFD_RELOC_AARCH64_MOVW_G2:
case BFD_RELOC_AARCH64_MOVW_G2_NC:
case BFD_RELOC_AARCH64_MOVW_G2_S:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G2:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:
scale = 32;
goto movw_common;
case BFD_RELOC_AARCH64_MOVW_G3:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G3:
scale = 48;
movw_common:
if (fixP->fx_done || !seg->use_rela_p)
@@ -7669,6 +7750,9 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
case BFD_RELOC_AARCH64_MOVW_G0_S:
case BFD_RELOC_AARCH64_MOVW_G1_S:
case BFD_RELOC_AARCH64_MOVW_G2_S:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G0:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G1:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G2:
/* NOTE: We can only come here with movz or movn. */
if (signed_overflow (value, scale + 16))
as_bad_where (fixP->fx_file, fixP->fx_line,
diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g0.d b/gas/testsuite/gas/aarch64/reloc-prel_g0.d
new file mode 100644
index 0000000..9ba990e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g0.d
@@ -0,0 +1,13 @@
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 8a000000 and x0, x0, x0
+ 4: 92400000 and x0, x0, #0x1
+ 8: d2800004 mov x4, #0x0 // #0
+ 8: R_AARCH64_MOVW_PREL_G0 tempy
+ c: d2800011 mov x17, #0x0 // #0
+ c: R_AARCH64_MOVW_PREL_G0 tempy2
diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g0.s b/gas/testsuite/gas/aarch64/reloc-prel_g0.s
new file mode 100644
index 0000000..4cbb287
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g0.s
@@ -0,0 +1,7 @@
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movz x4, :prel_g0:tempy
+ movz x17, :prel_g0:tempy2
diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g0_nc.d b/gas/testsuite/gas/aarch64/reloc-prel_g0_nc.d
new file mode 100644
index 0000000..4127ce7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g0_nc.d
@@ -0,0 +1,15 @@
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 8a000000 and x0, x0, x0
+ 4: 92400000 and x0, x0, #0x1
+ 8: f2800004 movk x4, #0x0
+ 8: R_AARCH64_MOVW_PREL_G0_NC tempy
+ c: f2800007 movk x7, #0x0
+ c: R_AARCH64_MOVW_PREL_G0_NC tempy2
+ 10: f2800011 movk x17, #0x0
+ 10: R_AARCH64_MOVW_PREL_G0_NC tempy3
diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g0_nc.s b/gas/testsuite/gas/aarch64/reloc-prel_g0_nc.s
new file mode 100644
index 0000000..6b4c2e9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g0_nc.s
@@ -0,0 +1,8 @@
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movk x4, :prel_g0_nc:tempy
+ movk x7, :prel_g0_nc:tempy2
+ movk x17, :prel_g0_nc:tempy3
diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g1.d b/gas/testsuite/gas/aarch64/reloc-prel_g1.d
new file mode 100644
index 0000000..1a161f8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g1.d
@@ -0,0 +1,13 @@
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 8a000000 and x0, x0, x0
+ 4: 92400000 and x0, x0, #0x1
+ 8: d2a00004 movz x4, #0x0, lsl #16
+ 8: R_AARCH64_MOVW_PREL_G1 tempy
+ c: d2a00011 movz x17, #0x0, lsl #16
+ c: R_AARCH64_MOVW_PREL_G1 tempy2
diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g1.s b/gas/testsuite/gas/aarch64/reloc-prel_g1.s
new file mode 100644
index 0000000..fd7e216
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g1.s
@@ -0,0 +1,7 @@
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movz x4, :prel_g1:tempy
+ movz x17, :prel_g1:tempy2
diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g1_nc.d b/gas/testsuite/gas/aarch64/reloc-prel_g1_nc.d
new file mode 100644
index 0000000..4c0a1d9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g1_nc.d
@@ -0,0 +1,15 @@
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 8a000000 and x0, x0, x0
+ 4: 92400000 and x0, x0, #0x1
+ 8: f2a00004 movk x4, #0x0, lsl #16
+ 8: R_AARCH64_MOVW_PREL_G1_NC tempy
+ c: f2a00007 movk x7, #0x0, lsl #16
+ c: R_AARCH64_MOVW_PREL_G1_NC tempy2
+ 10: f2a00011 movk x17, #0x0, lsl #16
+ 10: R_AARCH64_MOVW_PREL_G1_NC tempy3
diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g1_nc.s b/gas/testsuite/gas/aarch64/reloc-prel_g1_nc.s
new file mode 100644
index 0000000..6c5b72f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g1_nc.s
@@ -0,0 +1,8 @@
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movk x4, :prel_g1_nc:tempy
+ movk x7, :prel_g1_nc:tempy2
+ movk x17, :prel_g1_nc:tempy3
diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g2.d b/gas/testsuite/gas/aarch64/reloc-prel_g2.d
new file mode 100644
index 0000000..80d1870
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g2.d
@@ -0,0 +1,15 @@
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 8a000000 and x0, x0, x0
+ 4: 92400000 and x0, x0, #0x1
+ 8: d2c00004 movz x4, #0x0, lsl #32
+ 8: R_AARCH64_MOVW_PREL_G2 tempy
+ c: d2c00007 movz x7, #0x0, lsl #32
+ c: R_AARCH64_MOVW_PREL_G2 tempy2
+ 10: d2c00011 movz x17, #0x0, lsl #32
+ 10: R_AARCH64_MOVW_PREL_G2 tempy3
diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g2.s b/gas/testsuite/gas/aarch64/reloc-prel_g2.s
new file mode 100644
index 0000000..716bf29
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g2.s
@@ -0,0 +1,8 @@
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movz x4, :prel_g2:tempy
+ movz x7, :prel_g2:tempy2
+ movz x17, :prel_g2:tempy3
diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g2_nc.d b/gas/testsuite/gas/aarch64/reloc-prel_g2_nc.d
new file mode 100644
index 0000000..dc3c58e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g2_nc.d
@@ -0,0 +1,15 @@
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 8a000000 and x0, x0, x0
+ 4: 92400000 and x0, x0, #0x1
+ 8: f2c00004 movk x4, #0x0, lsl #32
+ 8: R_AARCH64_MOVW_PREL_G2_NC tempy
+ c: f2c00007 movk x7, #0x0, lsl #32
+ c: R_AARCH64_MOVW_PREL_G2_NC tempy2
+ 10: f2c00011 movk x17, #0x0, lsl #32
+ 10: R_AARCH64_MOVW_PREL_G2_NC tempy3
diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g2_nc.s b/gas/testsuite/gas/aarch64/reloc-prel_g2_nc.s
new file mode 100644
index 0000000..7327faa
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g2_nc.s
@@ -0,0 +1,8 @@
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movk x4, :prel_g2_nc:tempy
+ movk x7, :prel_g2_nc:tempy2
+ movk x17, :prel_g2_nc:tempy3
diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g3.d b/gas/testsuite/gas/aarch64/reloc-prel_g3.d
new file mode 100644
index 0000000..4a476ab
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g3.d
@@ -0,0 +1,15 @@
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 8a000000 and x0, x0, x0
+ 4: 92400000 and x0, x0, #0x1
+ 8: d2e00004 movz x4, #0x0, lsl #48
+ 8: R_AARCH64_MOVW_PREL_G3 tempy
+ c: d2e00007 movz x7, #0x0, lsl #48
+ c: R_AARCH64_MOVW_PREL_G3 tempy2
+ 10: d2e00011 movz x17, #0x0, lsl #48
+ 10: R_AARCH64_MOVW_PREL_G3 tempy3
diff --git a/gas/testsuite/gas/aarch64/reloc-prel_g3.s b/gas/testsuite/gas/aarch64/reloc-prel_g3.s
new file mode 100644
index 0000000..2850e49
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reloc-prel_g3.s
@@ -0,0 +1,8 @@
+.comm gempy,4,4
+.text
+
+ and x0,x0,x0
+ and x0,x0,#0x1
+ movz x4, :prel_g3:tempy
+ movz x7, :prel_g3:tempy2
+ movz x17, :prel_g3:tempy3
--
1.9.1
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [Binutils][AARCH64][2/2]Add group relocations to create PC-relative offset.
2018-01-18 15:34 [Binutils][AARCH64][0/2]Add group relocations to create PC-relative offset Renlin Li
2018-01-18 15:38 ` [Binutils][AARCH64][1/2]Add " Renlin Li
@ 2018-01-18 15:39 ` Renlin Li
2018-01-22 13:24 ` Nick Clifton
1 sibling, 1 reply; 6+ messages in thread
From: Renlin Li @ 2018-01-18 15:39 UTC (permalink / raw)
To: binutils, Ramana Radhakrishnan, Nicholas Clifton
[-- Attachment #1: Type: text/plain, Size: 2823 bytes --]
Hi all,
This is the lnker part support for the following relocations:
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3
Regards,
Renlin
bfd/
2018-01-18 Renlin Li <renlin.li@arm.com>
* elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Add support.
* elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise.
(_bfd_aarch64_elf_resolve_relocation): Likewise.
ld/
2018-01-18 Renlin Li <renlin.li@arm.com>
* testsuite/ld-aarch64/aarch64-elf.exp: Run new testes.
* testsuite/ld-aarch64/emit-relocs-287.s: Fix test case.
* testsuite/ld-aarch64/emit-relocs-287.d: Fix expected output.
* testsuite/ld-aarch64/emit-relocs-287-overflow.s: New.
* testsuite/ld-aarch64/emit-relocs-287-overflow.d: New.
* testsuite/ld-aarch64/emit-relocs-288.d: New.
* testsuite/ld-aarch64/emit-relocs-288.s: New.
* testsuite/ld-aarch64/emit-relocs-289.d: New.
* testsuite/ld-aarch64/emit-relocs-289.s: New.
* testsuite/ld-aarch64/emit-relocs-289-overflow.s: New.
* testsuite/ld-aarch64/emit-relocs-289-overflow.d: New.
* testsuite/ld-aarch64/emit-relocs-290.d: New.
* testsuite/ld-aarch64/emit-relocs-290.s: New.
* testsuite/ld-aarch64/emit-relocs-291.d: New.
* testsuite/ld-aarch64/emit-relocs-291.s: New.
* testsuite/ld-aarch64/emit-relocs-291-overflow.s: New.
* testsuite/ld-aarch64/emit-relocs-291-overflow.d: New.
* testsuite/ld-aarch64/emit-relocs-292.d: New.
* testsuite/ld-aarch64/emit-relocs-292.s: New.
* testsuite/ld-aarch64/emit-relocs-293.d: New.
* testsuite/ld-aarch64/emit-relocs-293.s: New.
On 18/01/18 15:34, Renlin Li wrote:
> Hi all,
>
> This is a patch to add Group relocations to create a
> 16, 32, 48, or 64 bit PC-relative offset inline.
>
> The following relocations are added along with the test cases:
> BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
> BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
> BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
> BFD_RELOC_AARCH64_MOVW_PREL_G3.
>
>
> The operations for those relocations are: S + A - P.
> S is the address of the symbol.
> A is the addend for the relocation.
> P is the address of the place being relocated
>
> Those relocations are used to create PC-relative offset. For example,
> The following code sequence could get the full address of _start.
>
> .Ltmp1:
> movz   x0, :prel_g2: _start - .Ltmp1
> movk   x0, :prel_g1_nc: _start - .Ltmp1
> movk   x0, :prel_g0_nc: _start - .Ltmp1
> adr   x1, .Ltmp1
> add   x0, x0, x1
>
> binutils regression test checked OK, linux kernel link checked OK.
> OK to commit?
>
> Regards,
> Renlin
[-- Attachment #2: 0002-LD-AARCH64-Add-group-relocations-to-create-PC-relati.patch --]
[-- Type: text/x-patch, Size: 16075 bytes --]
---
bfd/elfnn-aarch64.c | 7 +++++++
bfd/elfxx-aarch64.c | 14 +++++++++++++
ld/testsuite/ld-aarch64/aarch64-elf.exp | 12 ++++++++++-
ld/testsuite/ld-aarch64/emit-relocs-287-overflow.d | 5 +++++
ld/testsuite/ld-aarch64/emit-relocs-287-overflow.s | 5 +++++
ld/testsuite/ld-aarch64/emit-relocs-287.d | 14 +++++--------
ld/testsuite/ld-aarch64/emit-relocs-287.s | 8 ++------
ld/testsuite/ld-aarch64/emit-relocs-288.d | 11 ++++++++++
ld/testsuite/ld-aarch64/emit-relocs-288.s | 5 +++++
ld/testsuite/ld-aarch64/emit-relocs-289-overflow.d | 4 ++++
ld/testsuite/ld-aarch64/emit-relocs-289-overflow.s | 4 ++++
ld/testsuite/ld-aarch64/emit-relocs-289.d | 10 +++++++++
ld/testsuite/ld-aarch64/emit-relocs-289.s | 4 ++++
ld/testsuite/ld-aarch64/emit-relocs-290.d | 11 ++++++++++
ld/testsuite/ld-aarch64/emit-relocs-290.s | 5 +++++
ld/testsuite/ld-aarch64/emit-relocs-291-overflow.d | 4 ++++
ld/testsuite/ld-aarch64/emit-relocs-291-overflow.s | 4 ++++
ld/testsuite/ld-aarch64/emit-relocs-291.d | 11 ++++++++++
ld/testsuite/ld-aarch64/emit-relocs-291.s | 5 +++++
ld/testsuite/ld-aarch64/emit-relocs-292.d | 11 ++++++++++
ld/testsuite/ld-aarch64/emit-relocs-292.s | 6 ++++++
ld/testsuite/ld-aarch64/emit-relocs-293.d | 9 ++++++++
ld/testsuite/ld-aarch64/emit-relocs-293.s | 5 +++++
25 files changed, 188 insertions(+), 16 deletions(-)
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-287-overflow.d
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-287-overflow.s
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-288.d
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-288.s
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-289-overflow.d
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-289-overflow.s
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-289.d
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-289.s
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-290.d
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-290.s
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-291-overflow.d
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-291-overflow.s
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-291.d
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-291.s
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-292.d
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-292.s
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-293.d
create mode 100644 ld/testsuite/ld-aarch64/emit-relocs-293.s
diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c
index b84c8ba..af448f9 100644
--- a/bfd/elfnn-aarch64.c
+++ b/bfd/elfnn-aarch64.c
@@ -5462,6 +5462,13 @@ bad_ifunc_reloc:
case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
case BFD_RELOC_AARCH64_LD_LO19_PCREL:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G0:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G1:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G2:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G3:
if (bfd_link_pic (info)
&& (input_section->flags & SEC_ALLOC) != 0
&& (input_section->flags & SEC_READONLY) != 0
diff --git a/bfd/elfxx-aarch64.c b/bfd/elfxx-aarch64.c
index 9d4aa8f..4fa5682 100644
--- a/bfd/elfxx-aarch64.c
+++ b/bfd/elfxx-aarch64.c
@@ -301,6 +301,10 @@ _bfd_aarch64_elf_put_addend (bfd *abfd,
case BFD_RELOC_AARCH64_MOVW_G0_S:
case BFD_RELOC_AARCH64_MOVW_G1_S:
case BFD_RELOC_AARCH64_MOVW_G2_S:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G0:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G1:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G2:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G3:
case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
@@ -333,6 +337,9 @@ _bfd_aarch64_elf_put_addend (bfd *abfd,
case BFD_RELOC_AARCH64_MOVW_G3:
case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:
case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
@@ -395,6 +402,13 @@ _bfd_aarch64_elf_resolve_relocation (bfd_reloc_code_real_type r_type,
case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
case BFD_RELOC_AARCH64_BRANCH19:
case BFD_RELOC_AARCH64_LD_LO19_PCREL:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G0:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G1:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G2:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:
+ case BFD_RELOC_AARCH64_MOVW_PREL_G3:
case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21:
diff --git a/ld/testsuite/ld-aarch64/aarch64-elf.exp b/ld/testsuite/ld-aarch64/aarch64-elf.exp
index f310893..2602a43 100644
--- a/ld/testsuite/ld-aarch64/aarch64-elf.exp
+++ b/ld/testsuite/ld-aarch64/aarch64-elf.exp
@@ -143,7 +143,17 @@ run_dump_test_lp64 "emit-relocs-284"
run_dump_test_lp64 "emit-relocs-285"
run_dump_test_lp64 "emit-relocs-286"
run_dump_test_lp64 "emit-relocs-286-bad"
-# 287-298 are not done yet
+run_dump_test_lp64 "emit-relocs-287"
+run_dump_test_lp64 "emit-relocs-287-overflow"
+run_dump_test_lp64 "emit-relocs-288"
+run_dump_test_lp64 "emit-relocs-289"
+run_dump_test_lp64 "emit-relocs-289-overflow"
+run_dump_test_lp64 "emit-relocs-290"
+run_dump_test_lp64 "emit-relocs-291"
+run_dump_test_lp64 "emit-relocs-291-overflow"
+run_dump_test_lp64 "emit-relocs-292"
+run_dump_test_lp64 "emit-relocs-293"
+# 294-298 are not done yet
run_dump_test_lp64 "emit-relocs-299"
# 300 is not done yet
run_dump_test_lp64 "emit-relocs-301"
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-287-overflow.d b/ld/testsuite/ld-aarch64/emit-relocs-287-overflow.d
new file mode 100644
index 0000000..54f42c6
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-287-overflow.d
@@ -0,0 +1,5 @@
+#source: emit-relocs-287-overflow.s
+#ld: -T relocs.ld --defsym tempy=0x20000 --defsym tempy2=0x0 -e0 --emit-relocs
+#objdump: -dr
+#error: .*\(.text\+0x\d+\): relocation truncated to fit: R_AARCH64_MOVW_PREL_G0 against symbol `tempy' .*
+#error: .*\(.text\+0x\d+\): relocation truncated to fit: R_AARCH64_MOVW_PREL_G0 against symbol `tempy2' .*
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-287-overflow.s b/ld/testsuite/ld-aarch64/emit-relocs-287-overflow.s
new file mode 100644
index 0000000..999cd15
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-287-overflow.s
@@ -0,0 +1,5 @@
+.comm gempy,4,4
+.text
+
+ movz x4, :prel_g0:tempy
+ movz x4, :prel_g0:tempy2
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-287.d b/ld/testsuite/ld-aarch64/emit-relocs-287.d
index 4d5fd43..a76e0e6 100644
--- a/ld/testsuite/ld-aarch64/emit-relocs-287.d
+++ b/ld/testsuite/ld-aarch64/emit-relocs-287.d
@@ -1,14 +1,10 @@
#source: emit-relocs-287.s
-#ld: -T relocs.ld --defsym tempy=0x11000 --defsym tempy2=0x45000 --defsym tempy3=0x1234 --defsym _GOT_=0x10000 -e0 --emit-relocs
+#ld: -T relocs.ld --defsym tempy=0x1ffff --defsym tempy2=0x4 -e0 --emit-relocs
#objdump: -dr
#...
- +10000: 8a000000 and x0, x0, x0
- +10004: 92400000 and x0, x0, #0x1
- +10008: d2820004 movz x4, #0x1000
- +10008: R_AARCH64_MOVW_PREL_G0 _GOT_
- +1000c: d28a0007 movz x7, #0x5000
- +1000c: R_AARCH64_MOVW_PREL_G0 _GOT_
- +10010: d2824691 movz x17, #0x1234
- +10010: R_AARCH64_MOVW_PREL_G0 _GOT_
+ +10000: d29fffe4 mov x4, #0xffff // #65535
+ 10000: R_AARCH64_MOVW_PREL_G0 tempy
+ +10004: 929ffff1 mov x17, #0xffffffffffff0000 // #-65536
+ 10004: R_AARCH64_MOVW_PREL_G0 tempy2
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-287.s b/ld/testsuite/ld-aarch64/emit-relocs-287.s
index ae9476f..f9e53dc 100644
--- a/ld/testsuite/ld-aarch64/emit-relocs-287.s
+++ b/ld/testsuite/ld-aarch64/emit-relocs-287.s
@@ -1,9 +1,5 @@
.comm gempy,4,4
.text
-
- and x0,x0,x0
- and x0,x0,#0x1
- movz x4, :prel_g0:tempy
- movz x7, :prel_g0:tempy2
- movz x17, :prel_g0:tempy3
+ movz x4, :prel_g0:tempy
+ movz x17, :prel_g0:tempy2
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-288.d b/ld/testsuite/ld-aarch64/emit-relocs-288.d
new file mode 100644
index 0000000..d57f1b3
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-288.d
@@ -0,0 +1,11 @@
+#source: emit-relocs-288.s
+#ld: -T relocs.ld --defsym tempy=0x1ffff --defsym tempy2=0x20000 --defsym tempy3=0x0 -e0 --emit-relocs
+#objdump: -dr
+
+#...
+ +10000: f29fffe4 movk x4, #0xffff
+ 10000: R_AARCH64_MOVW_PREL_G0_NC tempy
+ +10004: f29fff87 movk x7, #0xfffc
+ 10004: R_AARCH64_MOVW_PREL_G0_NC tempy2
+ +10008: f29fff11 movk x17, #0xfff8
+ 10008: R_AARCH64_MOVW_PREL_G0_NC tempy3
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-288.s b/ld/testsuite/ld-aarch64/emit-relocs-288.s
new file mode 100644
index 0000000..8f556ed
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-288.s
@@ -0,0 +1,5 @@
+.comm gempy,4,4
+.text
+ movk x4, :prel_g0_nc:tempy
+ movk x7, :prel_g0_nc:tempy2
+ movk x17, :prel_g0_nc:tempy3
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-289-overflow.d b/ld/testsuite/ld-aarch64/emit-relocs-289-overflow.d
new file mode 100644
index 0000000..77a6d2a
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-289-overflow.d
@@ -0,0 +1,4 @@
+#source: emit-relocs-289-overflow.s
+#ld: -T relocs.ld --defsym tempy=0x1100000000 -e0 --emit-relocs
+#objdump: -dr
+#error: .*\(.text\+0x\d+\): relocation truncated to fit: R_AARCH64_MOVW_PREL_G1 against symbol `tempy' .*
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-289-overflow.s b/ld/testsuite/ld-aarch64/emit-relocs-289-overflow.s
new file mode 100644
index 0000000..7d9f25e
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-289-overflow.s
@@ -0,0 +1,4 @@
+.comm gempy,4,4
+.text
+
+ movz x4, :prel_g1:tempy
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-289.d b/ld/testsuite/ld-aarch64/emit-relocs-289.d
new file mode 100644
index 0000000..6c5ba23
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-289.d
@@ -0,0 +1,10 @@
+#source: emit-relocs-289.s
+#ld: -Ttext 0x100000000 --defsym tempy=0x1ffffffff --defsym tempy2=0x4 -e0 --emit-relocs
+#objdump: -dr
+
+#...
+ +100000000: d2bfffe4 mov x4, #0xffff0000 // #4294901760
+ 100000000: R_AARCH64_MOVW_PREL_G1 tempy
+ +100000004: 92bffff1 mov x17, #0xffffffff0000ffff // #-4294901761
+ 100000004: R_AARCH64_MOVW_PREL_G1 tempy2
+
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-289.s b/ld/testsuite/ld-aarch64/emit-relocs-289.s
new file mode 100644
index 0000000..ae1da9c
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-289.s
@@ -0,0 +1,4 @@
+.comm gempy,4,4
+.text
+ movz x4, :prel_g1:tempy
+ movz x17, :prel_g1:tempy2
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-290.d b/ld/testsuite/ld-aarch64/emit-relocs-290.d
new file mode 100644
index 0000000..bc2c6fc
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-290.d
@@ -0,0 +1,11 @@
+#source: emit-relocs-290.s
+#ld: -Ttext=0x100000000 --defsym tempy=0x200000000 --defsym tempy2=0x1ffff0000 --defsym tempy3=0x8 -e0 --emit-relocs
+#objdump: -dr
+
+#...
+ +100000000: f2a00004 movk x4, #0x0, lsl #16
+ 100000000: R_AARCH64_MOVW_PREL_G1_NC tempy
+ +100000004: f2bfffc7 movk x7, #0xfffe, lsl #16
+ 100000004: R_AARCH64_MOVW_PREL_G1_NC tempy2
+ +100000008: f2a00011 movk x17, #0x0, lsl #16
+ 100000008: R_AARCH64_MOVW_PREL_G1_NC tempy3
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-290.s b/ld/testsuite/ld-aarch64/emit-relocs-290.s
new file mode 100644
index 0000000..066ad64
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-290.s
@@ -0,0 +1,5 @@
+.comm gempy,4,4
+.text
+ movk x4, :prel_g1_nc:tempy
+ movk x7, :prel_g1_nc:tempy2
+ movk x17, :prel_g1_nc:tempy3
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-291-overflow.d b/ld/testsuite/ld-aarch64/emit-relocs-291-overflow.d
new file mode 100644
index 0000000..0ea3e50
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-291-overflow.d
@@ -0,0 +1,4 @@
+#source: emit-relocs-291-overflow.s
+#ld: -T relocs.ld --defsym tempy=0x10000000000000 -e0 --emit-relocs
+#objdump: -dr
+#error: .*\(.text\+0x\d+\): relocation truncated to fit: R_AARCH64_MOVW_PREL_G2 against symbol `tempy' .*
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-291-overflow.s b/ld/testsuite/ld-aarch64/emit-relocs-291-overflow.s
new file mode 100644
index 0000000..02649fa
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-291-overflow.s
@@ -0,0 +1,4 @@
+.comm gempy,4,4
+.text
+
+ movz x4, :prel_g2:tempy
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-291.d b/ld/testsuite/ld-aarch64/emit-relocs-291.d
new file mode 100644
index 0000000..53eb0e9
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-291.d
@@ -0,0 +1,11 @@
+#source: emit-relocs-291.s
+#ld: -Ttext 0x1000000000000 --defsym tempy=0x1ffffffffffff --defsym tempy2=0x1ffff00000000 -defsym tempy3=0x8 -e0 --emit-relocs
+#objdump: -dr
+
+#...
+ +1000000000000: d2dfffe4 mov x4, #0xffff00000000 // #281470681743360
+ 1000000000000: R_AARCH64_MOVW_PREL_G2 tempy
+ +1000000000004: d2dfffc7 mov x7, #0xfffe00000000 // #281466386776064
+ 1000000000004: R_AARCH64_MOVW_PREL_G2 tempy2
+ +1000000000008: 92dffff1 mov x17, #0xffff0000ffffffff // #-281470681743361
+ 1000000000008: R_AARCH64_MOVW_PREL_G2 tempy3
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-291.s b/ld/testsuite/ld-aarch64/emit-relocs-291.s
new file mode 100644
index 0000000..955fe1b
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-291.s
@@ -0,0 +1,5 @@
+.comm gempy,4,4
+.text
+ movz x4, :prel_g2:tempy
+ movz x7, :prel_g2:tempy2
+ movz x17, :prel_g2:tempy3
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-292.d b/ld/testsuite/ld-aarch64/emit-relocs-292.d
new file mode 100644
index 0000000..3fbde20
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-292.d
@@ -0,0 +1,11 @@
+#source: emit-relocs-292.s
+#ld: -Ttext 0x1000000000000 --defsym tempy=0x2000000000000 --defsym tempy2=0x1ffff00000004 --defsym tempy3=0x4 -e0 --emit-relocs
+#objdump: -dr
+
+#...
+ +1000000000000: f2c00004 movk x4, #0x0, lsl #32
+ 1000000000000: R_AARCH64_MOVW_PREL_G2_NC tempy
+ +1000000000004: f2dfffe7 movk x7, #0xffff, lsl #32
+ 1000000000004: R_AARCH64_MOVW_PREL_G2_NC tempy2
+ +1000000000008: f2dffff1 movk x17, #0xffff, lsl #32
+ 1000000000008: R_AARCH64_MOVW_PREL_G2_NC tempy3
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-292.s b/ld/testsuite/ld-aarch64/emit-relocs-292.s
new file mode 100644
index 0000000..82972df
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-292.s
@@ -0,0 +1,6 @@
+.comm gempy,4,4
+.text
+
+ movk x4, :prel_g2_nc:tempy
+ movk x7, :prel_g2_nc:tempy2
+ movk x17, :prel_g2_nc:tempy3
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-293.d b/ld/testsuite/ld-aarch64/emit-relocs-293.d
new file mode 100644
index 0000000..1e15f18
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-293.d
@@ -0,0 +1,9 @@
+#source: emit-relocs-293.s
+#ld: -Ttext 0x1000000000000 --defsym tempy=0x2000000000000000 --defsym tempy2=0x8 -e0 --emit-relocs
+#objdump: -dr
+
+#...
+ +1000000000000: d2e3ffe4 mov x4, #0x1fff000000000000 // #2305561534236983296
+ 1000000000000: R_AARCH64_MOVW_PREL_G3 tempy
+ +1000000000004: 92e00007 movn x7, #0x0, lsl #48
+ 1000000000004: R_AARCH64_MOVW_PREL_G3 tempy2
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-293.s b/ld/testsuite/ld-aarch64/emit-relocs-293.s
new file mode 100644
index 0000000..d5803c1
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-293.s
@@ -0,0 +1,5 @@
+.comm gempy,4,4
+.text
+
+ movz x4, :prel_g3:tempy
+ movz x7, :prel_g3:tempy2
--
1.9.1
^ permalink raw reply [flat|nested] 6+ messages in thread