* [PATCH 00/12] x86: disassembler fixes and some consolidation
@ 2021-07-21 10:07 Jan Beulich
2021-07-21 10:18 ` [PATCH 01/12] x86: drop OP_Mask() Jan Beulich
` (12 more replies)
0 siblings, 13 replies; 16+ messages in thread
From: Jan Beulich @ 2021-07-21 10:07 UTC (permalink / raw)
To: Binutils
This has started by me noticing that OP_G() handles "bytemode"
values it never gets passed. But here you go - I've found a
couple of bugs as I was going, and extended / better ways of
cleaning up some code. But the duplication of register printing
was something that has been puzzling me for a while, not the
least because with about every other ISA extension two places
have been getting touched when just one should have done.
01: drop OP_Mask()
02: correct VCVT{,U}SI2SD rounding mode handling
03: generalize OP_G()'s EVEX.R' handling
04: properly bounds-check %bnd<N> in OP_G()
05: fold duplicate register printing code
06: fold duplicate code in MOVSXD_Fixup()
07: correct EVEX.V' handling outside of 64-bit mode
08: drop vex_mode and vex_scalar_mode
09: fold duplicate vector register printing code
10: drop xmm_m{b,w,d,q}_mode
11: drop vex_scalar_w_dq_mode
12: drop dq{b,d}_mode
Jan
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 01/12] x86: drop OP_Mask()
2021-07-21 10:07 [PATCH 00/12] x86: disassembler fixes and some consolidation Jan Beulich
@ 2021-07-21 10:18 ` Jan Beulich
2021-07-21 10:19 ` [PATCH 02/12] x86: correct VCVT{,U}SI2SD rounding mode handling Jan Beulich
` (11 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Jan Beulich @ 2021-07-21 10:18 UTC (permalink / raw)
To: Binutils
By moving its vex.r check there it becomes fully redundant with OP_G().
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -151,9 +151,9 @@
},
/* PREFIX_EVEX_0FC2 */
{
- { "vcmppX", { XMask, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
+ { "vcmppX", { MaskG, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
{ VEX_W_TABLE (EVEX_W_0FC2_P_1) },
- { "vcmppX", { XMask, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
+ { "vcmppX", { MaskG, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
{ VEX_W_TABLE (EVEX_W_0FC2_P_3) },
},
/* PREFIX_EVEX_0FE6 */
@@ -238,14 +238,14 @@
/* PREFIX_EVEX_0F3826 */
{
{ Bad_Opcode },
- { "vptestnm%BW", { XMask, Vex, EXx }, 0 },
- { "vptestm%BW", { XMask, Vex, EXx }, 0 },
+ { "vptestnm%BW", { MaskG, Vex, EXx }, 0 },
+ { "vptestm%BW", { MaskG, Vex, EXx }, 0 },
},
/* PREFIX_EVEX_0F3827 */
{
{ Bad_Opcode },
- { "vptestnm%DQ", { XMask, Vex, EXx }, 0 },
- { "vptestm%DQ", { XMask, Vex, EXx }, 0 },
+ { "vptestnm%DQ", { MaskG, Vex, EXx }, 0 },
+ { "vptestm%DQ", { MaskG, Vex, EXx }, 0 },
},
/* PREFIX_EVEX_0F3828 */
{
@@ -256,7 +256,7 @@
/* PREFIX_EVEX_0F3829 */
{
{ Bad_Opcode },
- { "vpmov%BW2m", { XMask, EXx }, 0 },
+ { "vpmov%BW2m", { MaskG, EXx }, 0 },
{ VEX_W_TABLE (EVEX_W_0F3829_P_2) },
},
/* PREFIX_EVEX_0F382A */
@@ -310,7 +310,7 @@
/* PREFIX_EVEX_0F3839 */
{
{ Bad_Opcode },
- { "vpmov%DQ2m", { XMask, EXx }, 0 },
+ { "vpmov%DQ2m", { MaskG, EXx }, 0 },
{ "vpmins%DQ", { XM, Vex, EXx }, 0 },
},
/* PREFIX_EVEX_0F383A */
@@ -338,7 +338,7 @@
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vp2intersect%DQ", { XMask, Vex, EXx, EXxEVexS }, 0 },
+ { "vp2intersect%DQ", { MaskG, Vex, EXx, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_0F3872 */
{
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -142,7 +142,7 @@
},
/* EVEX_W_0F66 */
{
- { "vpcmpgtd", { XMask, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpgtd", { MaskG, Vex, EXx }, PREFIX_DATA },
},
/* EVEX_W_0F6A */
{
@@ -201,7 +201,7 @@
},
/* EVEX_W_0F76 */
{
- { "vpcmpeqd", { XMask, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpeqd", { MaskG, Vex, EXx }, PREFIX_DATA },
},
/* EVEX_W_0F78_P_0 */
{
@@ -270,12 +270,12 @@
},
/* EVEX_W_0FC2_P_1 */
{
- { "vcmpss", { XMask, VexScalar, EXxmm_md, EXxEVexS, CMP }, 0 },
+ { "vcmpss", { MaskG, VexScalar, EXxmm_md, EXxEVexS, CMP }, 0 },
},
/* EVEX_W_0FC2_P_3 */
{
{ Bad_Opcode },
- { "vcmpsd", { XMask, VexScalar, EXxmm_mq, EXxEVexS, CMP }, 0 },
+ { "vcmpsd", { MaskG, VexScalar, EXxmm_mq, EXxEVexS, CMP }, 0 },
},
/* EVEX_W_0FD2 */
{
@@ -450,7 +450,7 @@
/* EVEX_W_0F3829_P_2 */
{
{ Bad_Opcode },
- { "vpcmpeqq", { XMask, Vex, EXx }, 0 },
+ { "vpcmpeqq", { MaskG, Vex, EXx }, 0 },
},
/* EVEX_W_0F382A_P_1 */
{
@@ -496,7 +496,7 @@
/* EVEX_W_0F3837 */
{
{ Bad_Opcode },
- { "vpcmpgtq", { XMask, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpgtq", { MaskG, Vex, EXx }, PREFIX_DATA },
},
/* EVEX_W_0F383A_P_1 */
{
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -114,8 +114,8 @@ static const struct dis386 evex_table[][
{ "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
{ VEX_W_TABLE (EVEX_W_0F62) },
{ "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
- { "vpcmpgtb", { XMask, Vex, EXx }, PREFIX_DATA },
- { "vpcmpgtw", { XMask, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpgtb", { MaskG, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpgtw", { MaskG, Vex, EXx }, PREFIX_DATA },
{ VEX_W_TABLE (EVEX_W_0F66) },
{ "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
/* 68 */
@@ -132,8 +132,8 @@ static const struct dis386 evex_table[][
{ REG_TABLE (REG_EVEX_0F71) },
{ REG_TABLE (REG_EVEX_0F72) },
{ REG_TABLE (REG_EVEX_0F73) },
- { "vpcmpeqb", { XMask, Vex, EXx }, PREFIX_DATA },
- { "vpcmpeqw", { XMask, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpeqb", { MaskG, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpeqw", { MaskG, Vex, EXx }, PREFIX_DATA },
{ VEX_W_TABLE (EVEX_W_0F76) },
{ Bad_Opcode },
/* 78 */
@@ -453,7 +453,7 @@ static const struct dis386 evex_table[][
{ Bad_Opcode },
{ "vperm%BW", { XM, Vex, EXx }, PREFIX_DATA },
{ Bad_Opcode },
- { "vpshufbitqmb", { XMask, Vex, EXx }, PREFIX_DATA },
+ { "vpshufbitqmb", { MaskG, Vex, EXx }, PREFIX_DATA },
/* 90 */
{ "vpgatherd%DQ", { XMGatherD, MVexVSIBDWpX }, PREFIX_DATA },
{ "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX }, PREFIX_DATA },
@@ -617,8 +617,8 @@ static const struct dis386 evex_table[][
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A1B) },
{ Bad_Opcode },
{ VEX_W_TABLE (VEX_W_0F3A1D) },
- { "vpcmpu%DQ", { XMask, Vex, EXx, VPCMP }, PREFIX_DATA },
- { "vpcmp%DQ", { XMask, Vex, EXx, VPCMP }, PREFIX_DATA },
+ { "vpcmpu%DQ", { MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
+ { "vpcmp%DQ", { MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
/* 20 */
{ VEX_LEN_TABLE (VEX_LEN_0F3A20) },
{ VEX_W_TABLE (EVEX_W_0F3A21) },
@@ -653,8 +653,8 @@ static const struct dis386 evex_table[][
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A3B) },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpcmpu%BW", { XMask, Vex, EXx, VPCMP }, PREFIX_DATA },
- { "vpcmp%BW", { XMask, Vex, EXx, VPCMP }, PREFIX_DATA },
+ { "vpcmpu%BW", { MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
+ { "vpcmp%BW", { MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
/* 40 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -698,8 +698,8 @@ static const struct dis386 evex_table[][
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfpclassp%XW%XZ", { XMask, EXx, Ib }, PREFIX_DATA },
- { "vfpclasss%XW", { XMask, EXVexWdqScalar, Ib }, PREFIX_DATA },
+ { "vfpclassp%XW%XZ", { MaskG, EXx, Ib }, PREFIX_DATA },
+ { "vfpclasss%XW", { MaskG, EXVexWdqScalar, Ib }, PREFIX_DATA },
/* 68 */
{ Bad_Opcode },
{ Bad_Opcode },
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -116,8 +116,6 @@ static void FXSAVE_Fixup (int, int);
static void MOVSXD_Fixup (int, int);
-static void OP_Mask (int, int);
-
struct dis_private {
/* Points to first byte not fetched. */
bfd_byte *max_fetched;
@@ -406,7 +404,6 @@ fetch_data (struct disassemble_info *inf
#define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
#define EXxEVexS { OP_Rounding, evex_sae_mode }
-#define XMask { OP_Mask, mask_mode }
#define MaskG { OP_G, mask_mode }
#define MaskE { OP_E, mask_mode }
#define MaskBDE { OP_E, mask_bd_mode }
@@ -12017,12 +12014,12 @@ OP_G (int bytemode, int sizeflag)
break;
case mask_bd_mode:
case mask_mode:
- if ((modrm.reg + add) > 0x7)
+ if (add || (vex.evex && !vex.r))
{
oappend ("(bad)");
return;
}
- oappend (names_mask[modrm.reg + add]);
+ oappend (names_mask[modrm.reg]);
break;
default:
oappend (INTERNAL_DISASSEMBLER_ERROR);
@@ -13721,23 +13718,6 @@ MOVSXD_Fixup (int bytemode, int sizeflag
}
static void
-OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
-{
- if (!vex.evex
- || (bytemode != mask_mode && bytemode != mask_bd_mode))
- abort ();
-
- USED_REX (REX_R);
- if ((rex & REX_R) != 0 || !vex.r)
- {
- BadOp ();
- return;
- }
-
- oappend (names_mask [modrm.reg]);
-}
-
-static void
OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
if (modrm.mod == 3 && vex.b)
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 02/12] x86: correct VCVT{,U}SI2SD rounding mode handling
2021-07-21 10:07 [PATCH 00/12] x86: disassembler fixes and some consolidation Jan Beulich
2021-07-21 10:18 ` [PATCH 01/12] x86: drop OP_Mask() Jan Beulich
@ 2021-07-21 10:19 ` Jan Beulich
2021-07-22 11:18 ` Jan Beulich
2021-07-21 10:19 ` [PATCH 03/12] x86-64: generalize OP_G()'s EVEX.R' handling Jan Beulich
` (10 subsequent siblings)
12 siblings, 1 reply; 16+ messages in thread
From: Jan Beulich @ 2021-07-21 10:19 UTC (permalink / raw)
To: Binutils
With EVEX.W clear the instruction doesn't ignore the rounding mode, but
(like for other insns without rounding semantics) EVEX.b set causes #UD.
Hence the handling of EVEX.W needs to be done when processing
evex_rounding_64_mode, not at the decode stages.
Derive a new 64-bit testcase from the 32-bit one to cover the different
EVEX.W treatment in both cases.
---
This demonstrates a broader problem: Instructions not permitting
rounding control at all (which #UD if such was specified in the
encoding) get displayed without any hint to the badness, merely by there
not being any respective operand at all. While OP_E_memory() handles
EVEX.b (broadcast) wrongly being set (in an unhelpful way, in that not
all of the opcode bytes get consumed), there's nowhere that EVEX.b
(rounding) would be checked except for the three EXxEVexR, EXxEVexR64,
and EXxEVexS ones.
--- a/gas/testsuite/gas/i386/evex.d
+++ b/gas/testsuite/gas/i386/evex.d
@@ -1,5 +1,5 @@
#objdump: -dw -Msuffix
-#name: i386 EVX insns
+#name: i386 EVEX insns
.*: +file format .*
@@ -8,9 +8,12 @@ Disassembly of section .text:
0+ <_start>:
+[a-f0-9]+: 62 f1 d6 38 2a f0 vcvtsi2ssl %eax,\{rd-sae\},%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 57 38 2a f0 vcvtsi2sdl %eax,\(bad\),%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d7 38 2a f0 vcvtsi2sdl %eax,\(bad\),%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d6 08 7b f0 vcvtusi2ssl %eax,%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 57 08 7b f0 vcvtusi2sdl %eax,%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d7 08 7b f0 vcvtusi2sdl %eax,%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ssl %eax,\{rd-sae\},%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sdl %eax,\(bad\),%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sdl %eax,\(bad\),%xmm5,%xmm6
#pass
--- a/gas/testsuite/gas/i386/evex.s
+++ b/gas/testsuite/gas/i386/evex.s
@@ -4,8 +4,11 @@
.text
_start:
.byte 0x62, 0xf1, 0xd6, 0x38, 0x2a, 0xf0
+ .byte 0x62, 0xf1, 0x57, 0x38, 0x2a, 0xf0
.byte 0x62, 0xf1, 0xd7, 0x38, 0x2a, 0xf0
.byte 0x62, 0xf1, 0xd6, 0x08, 0x7b, 0xf0
+ .byte 0x62, 0xf1, 0x57, 0x08, 0x7b, 0xf0
.byte 0x62, 0xf1, 0xd7, 0x08, 0x7b, 0xf0
.byte 0x62, 0xf1, 0xd6, 0x38, 0x7b, 0xf0
+ .byte 0x62, 0xf1, 0x57, 0x38, 0x7b, 0xf0
.byte 0x62, 0xf1, 0xd7, 0x38, 0x7b, 0xf0
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -929,6 +929,7 @@ if [gas_64_check] then {
run_dump_test "x86-64-avx512er-intel"
run_dump_test "x86-64-avx512pf"
run_dump_test "x86-64-avx512pf-intel"
+ run_dump_test "x86-64-evex"
run_dump_test "x86-64-evex-lig256"
run_dump_test "x86-64-evex-lig512"
run_dump_test "x86-64-evex-lig256-intel"
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-evex.d
@@ -0,0 +1,20 @@
+#objdump: -dw
+#name: x86-64 EVEX insns
+#source: evex.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: 62 f1 d6 38 2a f0 vcvtsi2ss %rax,\{rd-sae\},%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 57 38 2a f0 vcvtsi2sd %eax,\(bad\),%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 d7 38 2a f0 vcvtsi2sd %rax,\{rd-sae\},%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 d6 08 7b f0 vcvtusi2ss %rax,%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 57 08 7b f0 vcvtusi2sd %eax,%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 d7 08 7b f0 vcvtusi2sd %rax,%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ss %rax,\{rd-sae\},%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sd %eax,\(bad\),%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sd %rax,\{rd-sae\},%xmm5,%xmm6
+#pass
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -30,7 +30,7 @@
{ Bad_Opcode },
{ "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
{ Bad_Opcode },
- { VEX_W_TABLE (EVEX_W_0F2A_P_3) },
+ { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
},
/* PREFIX_EVEX_0F51 */
{
@@ -134,7 +134,7 @@
{ Bad_Opcode },
{ "vcvtusi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
{ VEX_W_TABLE (EVEX_W_0F7B_P_2) },
- { VEX_W_TABLE (EVEX_W_0F7B_P_3) },
+ { "vcvtusi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
},
/* PREFIX_EVEX_0F7E */
{
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -37,11 +37,6 @@
{
{ "vmovshdup", { XM, EXx }, 0 },
},
- /* EVEX_W_0F2A_P_3 */
- {
- { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Ed }, 0 },
- { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
- },
/* EVEX_W_0F51_P_1 */
{
{ "vsqrtss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 },
@@ -243,11 +238,6 @@
{ "vcvtps2qq", { XM, EXEvexHalfBcstXmmq, EXxEVexR }, 0 },
{ "vcvtpd2qq", { XM, EXx, EXxEVexR }, 0 },
},
- /* EVEX_W_0F7B_P_3 */
- {
- { "vcvtusi2sd{%LQ|}", { XMScalar, VexScalar, Ed }, 0 },
- { "vcvtusi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
- },
/* EVEX_W_0F7E_P_1 */
{
{ Bad_Opcode },
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1476,7 +1476,6 @@ enum
EVEX_W_0F12_P_3,
EVEX_W_0F16_P_0_M_1,
EVEX_W_0F16_P_1,
- EVEX_W_0F2A_P_3,
EVEX_W_0F51_P_1,
EVEX_W_0F51_P_3,
EVEX_W_0F58_P_1,
@@ -1521,7 +1520,6 @@ enum
EVEX_W_0F7A_P_2,
EVEX_W_0F7A_P_3,
EVEX_W_0F7B_P_2,
- EVEX_W_0F7B_P_3,
EVEX_W_0F7E_P_1,
EVEX_W_0F7F_P_1,
EVEX_W_0F7F_P_2,
@@ -13724,7 +13722,7 @@ OP_Rounding (int bytemode, int sizeflag
switch (bytemode)
{
case evex_rounding_64_mode:
- if (address_mode != mode_64bit)
+ if (address_mode != mode_64bit || !vex.w)
{
oappend ("(bad)");
break;
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 03/12] x86-64: generalize OP_G()'s EVEX.R' handling
2021-07-21 10:07 [PATCH 00/12] x86: disassembler fixes and some consolidation Jan Beulich
2021-07-21 10:18 ` [PATCH 01/12] x86: drop OP_Mask() Jan Beulich
2021-07-21 10:19 ` [PATCH 02/12] x86: correct VCVT{,U}SI2SD rounding mode handling Jan Beulich
@ 2021-07-21 10:19 ` Jan Beulich
2021-07-21 10:19 ` [PATCH 04/12] x86-64: properly bounds-check %bnd<N> in OP_G() Jan Beulich
` (9 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Jan Beulich @ 2021-07-21 10:19 UTC (permalink / raw)
To: Binutils
EVEX.R' is invalid to be clear not only for mask registers, but also for
GPRs - IOW everything handled in this function.
--- a/gas/testsuite/gas/i386/evex.d
+++ b/gas/testsuite/gas/i386/evex.d
@@ -16,4 +16,6 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ssl %eax,\{rd-sae\},%xmm5,%xmm6
+[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sdl %eax,\(bad\),%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sdl %eax,\(bad\),%xmm5,%xmm6
+ +[a-f0-9]+: 62 e1 7e 08 2d c0 vcvtss2si %xmm0,%eax
+ +[a-f0-9]+: 62 e1 7c 08 c2 c0 00 vcmpeqps %xmm0,%xmm0,%k0
#pass
--- a/gas/testsuite/gas/i386/evex.s
+++ b/gas/testsuite/gas/i386/evex.s
@@ -12,3 +12,5 @@ _start:
.byte 0x62, 0xf1, 0xd6, 0x38, 0x7b, 0xf0
.byte 0x62, 0xf1, 0x57, 0x38, 0x7b, 0xf0
.byte 0x62, 0xf1, 0xd7, 0x38, 0x7b, 0xf0
+ .byte 0x62, 0xe1, 0x7e, 0x08, 0x2d, 0xc0
+ .byte 0x62, 0xe1, 0x7c, 0x08, 0xc2, 0xc0, 0x00
--- a/gas/testsuite/gas/i386/x86-64-evex.d
+++ b/gas/testsuite/gas/i386/x86-64-evex.d
@@ -17,4 +17,6 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ss %rax,\{rd-sae\},%xmm5,%xmm6
+[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sd %eax,\(bad\),%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sd %rax,\{rd-sae\},%xmm5,%xmm6
+ +[a-f0-9]+: 62 e1 7e 08 2d c0 vcvtss2si %xmm0,\(bad\)
+ +[a-f0-9]+: 62 e1 7c 08 c2 c0 00 vcmpeqps %xmm0,%xmm0,\(bad\)
#pass
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -11934,6 +11934,13 @@ OP_G (int bytemode, int sizeflag)
{
int add = 0;
const char **names;
+
+ if (vex.evex && !vex.r && address_mode == mode_64bit)
+ {
+ oappend ("(bad)");
+ return;
+ }
+
USED_REX (REX_R);
if (rex & REX_R)
add += 8;
@@ -12012,7 +12019,7 @@ OP_G (int bytemode, int sizeflag)
break;
case mask_bd_mode:
case mask_mode:
- if (add || (vex.evex && !vex.r))
+ if (add)
{
oappend ("(bad)");
return;
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 04/12] x86-64: properly bounds-check %bnd<N> in OP_G()
2021-07-21 10:07 [PATCH 00/12] x86: disassembler fixes and some consolidation Jan Beulich
` (2 preceding siblings ...)
2021-07-21 10:19 ` [PATCH 03/12] x86-64: generalize OP_G()'s EVEX.R' handling Jan Beulich
@ 2021-07-21 10:19 ` Jan Beulich
2021-07-21 10:20 ` [PATCH 05/12] x86: fold duplicate register printing code Jan Beulich
` (8 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Jan Beulich @ 2021-07-21 10:19 UTC (permalink / raw)
To: Binutils
The restriction to %bnd0-%bnd3 requires to also check REX.R is clear,
just like OP_E_Register() also includes REX.B in its check.
--- a/gas/testsuite/gas/i386/x86-64-mpx.d
+++ b/gas/testsuite/gas/i386/x86-64-mpx.d
@@ -191,5 +191,7 @@ Disassembly of section .text:
[a-f0-9]+ <bad>:
[ ]*[a-f0-9]+: 0f 1a 30 bndldx \(%rax\),\(bad\)
[ ]*[a-f0-9]+: 66 0f 1a c4 bndmov \(bad\),%bnd0
+[ ]*[a-f0-9]+: 66 41 0f 1a c0 bndmov \(bad\),%bnd0
+[ ]*[a-f0-9]+: 66 44 0f 1a c0 bndmov %bnd0,\(bad\)
[ ]*[a-f0-9]+: f3 0f 1b 05 90 90 90 90 bndmk \(bad\),%bnd0
#pass
--- a/gas/testsuite/gas/i386/x86-64-mpx.s
+++ b/gas/testsuite/gas/i386/x86-64-mpx.s
@@ -227,6 +227,20 @@ bad:
.byte 0x1a
.byte 0xc4
+ # bndmov with REX.B set
+ .byte 0x66
+ .byte 0x41
+ .byte 0x0f
+ .byte 0x1a
+ .byte 0xc0
+
+ # bndmov with REX.R set
+ .byte 0x66
+ .byte 0x44
+ .byte 0x0f
+ .byte 0x1a
+ .byte 0xc0
+
# bndmk (bad),%bnd0
.byte 0xf3
.byte 0x0f
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -11966,7 +11966,7 @@ OP_G (int bytemode, int sizeflag)
oappend (names64[modrm.reg + add]);
break;
case bnd_mode:
- if (modrm.reg > 0x3)
+ if (modrm.reg + add > 0x3)
{
oappend ("(bad)");
return;
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 05/12] x86: fold duplicate register printing code
2021-07-21 10:07 [PATCH 00/12] x86: disassembler fixes and some consolidation Jan Beulich
` (3 preceding siblings ...)
2021-07-21 10:19 ` [PATCH 04/12] x86-64: properly bounds-check %bnd<N> in OP_G() Jan Beulich
@ 2021-07-21 10:20 ` Jan Beulich
2021-07-21 10:20 ` [PATCH 06/12] x86: fold duplicate code in MOVSXD_Fixup() Jan Beulich
` (7 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Jan Beulich @ 2021-07-21 10:20 UTC (permalink / raw)
To: Binutils
What so far was OP_E_register() can be easily reused also for OP_G().
Add suitable parameters to the function and move the invocation of
swap_operand() to OP_E(). Adjust MOVSXD's first operand: There never was
a need to use movsxd_mode there, and its use gets in the way of the code
folding.
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -50,7 +50,6 @@ static void oappend (const char *);
static void append_seg (void);
static void OP_indirE (int, int);
static void print_operand_value (char *, int, bfd_vma);
-static void OP_E_register (int, int);
static void OP_E_memory (int, int);
static void print_displacement (char *, bfd_vma);
static void OP_E (int, int);
@@ -4180,7 +4179,7 @@ static const struct dis386 x86_64_table[
/* X86_64_63 */
{
{ "arpl", { Ew, Gw }, 0 },
- { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
+ { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
},
/* X86_64_6D */
@@ -11290,21 +11289,14 @@ intel_operand_size (int bytemode, int si
}
static void
-OP_E_register (int bytemode, int sizeflag)
+print_register (unsigned int reg, unsigned int rexmask, int bytemode, int sizeflag)
{
- int reg = modrm.rm;
const char **names;
- USED_REX (REX_B);
- if ((rex & REX_B))
+ USED_REX (rexmask);
+ if (rex & rexmask)
reg += 8;
- if ((sizeflag & SUFFIX_ALWAYS)
- && (bytemode == b_swap_mode
- || bytemode == bnd_swap_mode
- || bytemode == v_swap_mode))
- swap_operand ();
-
switch (bytemode)
{
case b_mode:
@@ -11924,7 +11916,15 @@ OP_E (int bytemode, int sizeflag)
codep++;
if (modrm.mod == 3)
- OP_E_register (bytemode, sizeflag);
+ {
+ if ((sizeflag & SUFFIX_ALWAYS)
+ && (bytemode == b_swap_mode
+ || bytemode == bnd_swap_mode
+ || bytemode == v_swap_mode))
+ swap_operand ();
+
+ print_register (modrm.rm, REX_B, bytemode, sizeflag);
+ }
else
OP_E_memory (bytemode, sizeflag);
}
@@ -11932,104 +11932,13 @@ OP_E (int bytemode, int sizeflag)
static void
OP_G (int bytemode, int sizeflag)
{
- int add = 0;
- const char **names;
-
if (vex.evex && !vex.r && address_mode == mode_64bit)
{
oappend ("(bad)");
return;
}
- USED_REX (REX_R);
- if (rex & REX_R)
- add += 8;
- switch (bytemode)
- {
- case b_mode:
- if (modrm.reg & 4)
- USED_REX (0);
- if (rex)
- oappend (names8rex[modrm.reg + add]);
- else
- oappend (names8[modrm.reg + add]);
- break;
- case w_mode:
- oappend (names16[modrm.reg + add]);
- break;
- case d_mode:
- case db_mode:
- case dw_mode:
- oappend (names32[modrm.reg + add]);
- break;
- case q_mode:
- oappend (names64[modrm.reg + add]);
- break;
- case bnd_mode:
- if (modrm.reg + add > 0x3)
- {
- oappend ("(bad)");
- return;
- }
- oappend (names_bnd[modrm.reg]);
- break;
- case v_mode:
- case dq_mode:
- case dqb_mode:
- case dqd_mode:
- case dqw_mode:
- case movsxd_mode:
- USED_REX (REX_W);
- if (rex & REX_W)
- oappend (names64[modrm.reg + add]);
- else if (bytemode != v_mode && bytemode != movsxd_mode)
- oappend (names32[modrm.reg + add]);
- else
- {
- if (sizeflag & DFLAG)
- oappend (names32[modrm.reg + add]);
- else
- oappend (names16[modrm.reg + add]);
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
- case va_mode:
- names = (address_mode == mode_64bit
- ? names64 : names32);
- if (!(prefixes & PREFIX_ADDR))
- {
- if (address_mode == mode_16bit)
- names = names16;
- }
- else
- {
- /* Remove "addr16/addr32". */
- all_prefixes[last_addr_prefix] = 0;
- names = (address_mode != mode_32bit
- ? names32 : names16);
- used_prefixes |= PREFIX_ADDR;
- }
- oappend (names[modrm.reg + add]);
- break;
- case m_mode:
- if (address_mode == mode_64bit)
- oappend (names64[modrm.reg + add]);
- else
- oappend (names32[modrm.reg + add]);
- break;
- case mask_bd_mode:
- case mask_mode:
- if (add)
- {
- oappend ("(bad)");
- return;
- }
- oappend (names_mask[modrm.reg]);
- break;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- break;
- }
+ print_register (modrm.reg, REX_R, bytemode, sizeflag);
}
static bfd_vma
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 06/12] x86: fold duplicate code in MOVSXD_Fixup()
2021-07-21 10:07 [PATCH 00/12] x86: disassembler fixes and some consolidation Jan Beulich
` (4 preceding siblings ...)
2021-07-21 10:20 ` [PATCH 05/12] x86: fold duplicate register printing code Jan Beulich
@ 2021-07-21 10:20 ` Jan Beulich
2021-07-21 10:21 ` [PATCH 07/12] x86: correct EVEX.V' handling outside of 64-bit mode Jan Beulich
` (6 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Jan Beulich @ 2021-07-21 10:20 UTC (permalink / raw)
To: Binutils
There's no need to have two paths printing the "xd" mnemonic suffix.
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -13601,31 +13601,25 @@ MOVSXD_Fixup (int bytemode, int sizeflag
switch (bytemode)
{
case movsxd_mode:
- if (intel_syntax)
+ if (!intel_syntax)
{
- *p++ = 'x';
- *p++ = 'd';
- goto skip;
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ {
+ *p++ = 'l';
+ *p++ = 'q';
+ break;
+ }
}
- USED_REX (REX_W);
- if (rex & REX_W)
- {
- *p++ = 'l';
- *p++ = 'q';
- }
- else
- {
- *p++ = 'x';
- *p++ = 'd';
- }
+ *p++ = 'x';
+ *p++ = 'd';
break;
default:
oappend (INTERNAL_DISASSEMBLER_ERROR);
break;
}
- skip:
mnemonicendp = p;
*p = '\0';
OP_E (bytemode, sizeflag);
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 07/12] x86: correct EVEX.V' handling outside of 64-bit mode
2021-07-21 10:07 [PATCH 00/12] x86: disassembler fixes and some consolidation Jan Beulich
` (5 preceding siblings ...)
2021-07-21 10:20 ` [PATCH 06/12] x86: fold duplicate code in MOVSXD_Fixup() Jan Beulich
@ 2021-07-21 10:21 ` Jan Beulich
2021-07-21 10:22 ` [PATCH 08/12] x86: drop vex_mode and vex_scalar_mode Jan Beulich
` (5 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Jan Beulich @ 2021-07-21 10:21 UTC (permalink / raw)
To: Binutils
Unlike the high bit of VEX.vvvv / EVEX.vvvv, EVEX.V' is not ignored
outside of 64-bit. Oddly enough there already are tests for these cases,
but their expectations were wrong. (This may have been based on an old
SDM version, where the restriction wasn't properly spelled out.)
--- a/gas/testsuite/gas/i386/noextreg.d
+++ b/gas/testsuite/gas/i386/noextreg.d
@@ -13,14 +13,14 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 f1 7d 08 db c0 vpandd %xmm0,%xmm0,%xmm0
[ ]*[a-f0-9]+: 62 d1 7d 08 db c0 vpandd %xmm0,%xmm0,%xmm0
[ ]*[a-f0-9]+: 62 f1 3d 08 db c0 vpandd %xmm0,%xmm0,%xmm0
-[ ]*[a-f0-9]+: 62 f1 7d 00 db c0 vpandd %xmm0,%xmm0,%xmm0
+[ ]*[a-f0-9]+: 62 f1 7d 00 db c0 vpandd %xmm0,\(bad\),%xmm0
[ ]*[a-f0-9]+: c4 e3 79 4c c0 00 vpblendvb %xmm0,%xmm0,%xmm0,%xmm0
[ ]*[a-f0-9]+: c4 c3 79 4c c0 00 vpblendvb %xmm0,%xmm0,%xmm0,%xmm0
[ ]*[a-f0-9]+: c4 e3 39 4c c0 00 vpblendvb %xmm0,%xmm0,%xmm0,%xmm0
[ ]*[a-f0-9]+: c4 e3 79 4c c0 80 vpblendvb %xmm0,%xmm0,%xmm0,%xmm0
[ ]*[a-f0-9]+: 62 f2 7d 0f 90 0c 00 vpgatherdd \(%eax,%xmm0,1\),%xmm1\{%k7\}
[ ]*[a-f0-9]+: 62 d2 7d 0f 90 0c 00 vpgatherdd \(%eax,%xmm0,1\),%xmm1\{%k7\}
-[ ]*[a-f0-9]+: 62 f2 7d 07 90 0c 00 vpgatherdd \(%eax,%xmm0,1\),%xmm1\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 7d 07 90 0c 00 vpgatherdd \(%eax,\(bad\),1\),%xmm1\{%k7\}
[ ]*[a-f0-9]+: c4 e2 78 f2 00 andn \(%eax\),%eax,%eax
[ ]*[a-f0-9]+: c4 e2 38 f2 00 andn \(%eax\),%eax,%eax
[ ]*[a-f0-9]+: c4 c2 78 f2 00 andn \(%eax\),%eax,%eax
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -9316,7 +9316,6 @@ get_valid_dis386 (const struct dis386 *d
/* In 16/32-bit mode silently ignore following bits. */
rex &= ~REX_B;
vex.r = 1;
- vex.v = 1;
}
need_vex = 1;
@@ -11718,8 +11717,13 @@ OP_E_memory (int bytemode, int sizeflag)
*obufp = '\0';
}
if (haveindex)
- oappend (address_mode == mode_64bit && !addr32flag
- ? indexes64[vindex] : indexes32[vindex]);
+ {
+ if (address_mode == mode_64bit || vindex < 16)
+ oappend (address_mode == mode_64bit && !addr32flag
+ ? indexes64[vindex] : indexes32[vindex]);
+ else
+ oappend ("(bad)");
+ }
else
oappend (address_mode == mode_64bit && !addr32flag
? index64 : index32);
@@ -13256,7 +13260,15 @@ OP_VEX (int bytemode, int sizeflag ATTRI
reg = vex.register_specifier;
vex.register_specifier = 0;
if (address_mode != mode_64bit)
- reg &= 7;
+ {
+ if (vex.evex && !vex.v)
+ {
+ oappend ("(bad)");
+ return;
+ }
+
+ reg &= 7;
+ }
else if (vex.evex && !vex.v)
reg += 16;
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 08/12] x86: drop vex_mode and vex_scalar_mode
2021-07-21 10:07 [PATCH 00/12] x86: disassembler fixes and some consolidation Jan Beulich
` (6 preceding siblings ...)
2021-07-21 10:21 ` [PATCH 07/12] x86: correct EVEX.V' handling outside of 64-bit mode Jan Beulich
@ 2021-07-21 10:22 ` Jan Beulich
2021-07-21 10:22 ` [PATCH 09/12] x86: fold duplicate vector register printing code Jan Beulich
` (4 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Jan Beulich @ 2021-07-21 10:22 UTC (permalink / raw)
To: Binutils
These are fully redundant with, respectively, x_mode and scalar_mode.
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -384,10 +384,10 @@ fetch_data (struct disassemble_info *inf
#define XMM0 { XMM_Fixup, 0 }
#define FXSAVE { FXSAVE_Fixup, 0 }
-#define Vex { OP_VEX, vex_mode }
-#define VexW { OP_VexW, vex_mode }
-#define VexScalar { OP_VEX, vex_scalar_mode }
-#define VexScalarR { OP_VexR, vex_scalar_mode }
+#define Vex { OP_VEX, x_mode }
+#define VexW { OP_VexW, x_mode }
+#define VexScalar { OP_VEX, scalar_mode }
+#define VexScalarR { OP_VexR, scalar_mode }
#define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
#define VexGdq { OP_VEX, dq_mode }
@@ -546,8 +546,6 @@ enum
dw_mode,
/* registers like dq_mode, memory like d_mode. */
dqd_mode,
- /* normal vex mode */
- vex_mode,
/* Operand size depends on the VEX.W bit, with VSIB dword indices. */
vex_vsib_d_w_dq_mode,
@@ -558,8 +556,6 @@ enum
/* scalar, ignore vector length. */
scalar_mode,
- /* like vex_mode, ignore vector length. */
- vex_scalar_mode,
/* Operand size depends on the VEX.W bit, ignore vector length. */
vex_scalar_w_dq_mode,
@@ -13274,7 +13270,7 @@ OP_VEX (int bytemode, int sizeflag ATTRI
switch (bytemode)
{
- case vex_scalar_mode:
+ case scalar_mode:
oappend (names_xmm[reg]);
return;
@@ -13343,7 +13339,7 @@ OP_VEX (int bytemode, int sizeflag ATTRI
case 128:
switch (bytemode)
{
- case vex_mode:
+ case x_mode:
names = names_xmm;
break;
case dq_mode:
@@ -13369,7 +13365,7 @@ OP_VEX (int bytemode, int sizeflag ATTRI
case 256:
switch (bytemode)
{
- case vex_mode:
+ case x_mode:
names = names_ymm;
break;
case mask_bd_mode:
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 09/12] x86: fold duplicate vector register printing code
2021-07-21 10:07 [PATCH 00/12] x86: disassembler fixes and some consolidation Jan Beulich
` (7 preceding siblings ...)
2021-07-21 10:22 ` [PATCH 08/12] x86: drop vex_mode and vex_scalar_mode Jan Beulich
@ 2021-07-21 10:22 ` Jan Beulich
2021-07-21 10:22 ` [PATCH 10/12] x86: drop xmm_m{b,w,d,q}_mode Jan Beulich
` (3 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Jan Beulich @ 2021-07-21 10:22 UTC (permalink / raw)
To: Binutils
The bulk of OP_XMM() can be easily reused also for OP_EX(). Break the
shared logic out of the function, and invoke the new helper from both
places.
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -12530,20 +12530,10 @@ OP_MMX (int bytemode ATTRIBUTE_UNUSED, i
}
static void
-OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
+print_vector_reg (unsigned int reg, int bytemode)
{
- int reg = modrm.reg;
const char **names;
- USED_REX (REX_R);
- if (rex & REX_R)
- reg += 8;
- if (vex.evex)
- {
- if (!vex.r)
- reg += 16;
- }
-
if (bytemode == xmmq_mode
|| bytemode == evex_half_bcst_xmmq_mode)
{
@@ -12564,7 +12554,6 @@ OP_XMM (int bytemode, int sizeflag ATTRI
names = names_ymm;
else if (bytemode == tmm_mode)
{
- modrm.reg = reg;
if (reg >= 8)
{
oappend ("(bad)");
@@ -12574,7 +12563,14 @@ OP_XMM (int bytemode, int sizeflag ATTRI
}
else if (need_vex
&& bytemode != xmm_mode
- && bytemode != scalar_mode)
+ && bytemode != scalar_mode
+ && bytemode != xmmdw_mode
+ && bytemode != xmmqd_mode
+ && bytemode != xmm_mb_mode
+ && bytemode != xmm_mw_mode
+ && bytemode != xmm_md_mode
+ && bytemode != xmm_mq_mode
+ && bytemode != vex_scalar_w_dq_mode)
{
switch (vex.length)
{
@@ -12605,6 +12601,26 @@ OP_XMM (int bytemode, int sizeflag ATTRI
}
static void
+OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
+{
+ unsigned int reg = modrm.reg;
+
+ USED_REX (REX_R);
+ if (rex & REX_R)
+ reg += 8;
+ if (vex.evex)
+ {
+ if (!vex.r)
+ reg += 16;
+ }
+
+ if (bytemode == tmm_mode)
+ modrm.reg = reg;
+
+ print_vector_reg (reg, bytemode);
+}
+
+static void
OP_EM (int bytemode, int sizeflag)
{
int reg;
@@ -12679,7 +12695,6 @@ static void
OP_EX (int bytemode, int sizeflag)
{
int reg;
- const char **names;
/* Skip mod/rm byte. */
MODRM_CHECK;
@@ -12708,66 +12723,10 @@ OP_EX (int bytemode, int sizeflag)
|| bytemode == q_swap_mode))
swap_operand ();
- if (need_vex
- && bytemode != xmm_mode
- && bytemode != xmmdw_mode
- && bytemode != xmmqd_mode
- && bytemode != xmm_mb_mode
- && bytemode != xmm_mw_mode
- && bytemode != xmm_md_mode
- && bytemode != xmm_mq_mode
- && bytemode != xmmq_mode
- && bytemode != evex_half_bcst_xmmq_mode
- && bytemode != ymm_mode
- && bytemode != tmm_mode
- && bytemode != vex_scalar_w_dq_mode)
- {
- switch (vex.length)
- {
- case 128:
- names = names_xmm;
- break;
- case 256:
- names = names_ymm;
- break;
- case 512:
- names = names_zmm;
- break;
- default:
- abort ();
- }
- }
- else if (bytemode == xmmq_mode
- || bytemode == evex_half_bcst_xmmq_mode)
- {
- switch (vex.length)
- {
- case 128:
- case 256:
- names = names_xmm;
- break;
- case 512:
- names = names_ymm;
- break;
- default:
- abort ();
- }
- }
- else if (bytemode == tmm_mode)
- {
- modrm.rm = reg;
- if (reg >= 8)
- {
- oappend ("(bad)");
- return;
- }
- names = names_tmm;
- }
- else if (bytemode == ymm_mode)
- names = names_ymm;
- else
- names = names_xmm;
- oappend (names[reg]);
+ if (bytemode == tmm_mode)
+ modrm.rm = reg;
+
+ print_vector_reg (reg, bytemode);
}
static void
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 10/12] x86: drop xmm_m{b,w,d,q}_mode
2021-07-21 10:07 [PATCH 00/12] x86: disassembler fixes and some consolidation Jan Beulich
` (8 preceding siblings ...)
2021-07-21 10:22 ` [PATCH 09/12] x86: fold duplicate vector register printing code Jan Beulich
@ 2021-07-21 10:22 ` Jan Beulich
2021-07-21 10:23 ` [PATCH 11/12] x86: drop vex_scalar_w_dq_mode Jan Beulich
` (2 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Jan Beulich @ 2021-07-21 10:22 UTC (permalink / raw)
To: Binutils
They're effectively redundant with {b,w,d,q}_mode.
--- a/opcodes/i386-dis-evex-mod.h
+++ b/opcodes/i386-dis-evex-mod.h
@@ -1,28 +1,28 @@
{
/* MOD_EVEX_0F12_PREFIX_0 */
- { "vmovlpX", { XMM, Vex, EXxmm_mq }, PREFIX_OPCODE },
+ { "vmovlpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
{ VEX_W_TABLE (EVEX_W_0F12_P_0_M_1) },
},
{
/* MOD_EVEX_0F12_PREFIX_2 */
- { "vmovlpX", { XMM, Vex, EXxmm_mq }, PREFIX_OPCODE },
+ { "vmovlpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
},
{
/* MOD_EVEX_0F13 */
- { "vmovlpX", { EXxmm_mq, XMM }, PREFIX_OPCODE },
+ { "vmovlpX", { EXq, XMM }, PREFIX_OPCODE },
},
{
/* MOD_EVEX_0F16_PREFIX_0 */
- { "vmovhpX", { XMM, Vex, EXxmm_mq }, PREFIX_OPCODE },
+ { "vmovhpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
{ VEX_W_TABLE (EVEX_W_0F16_P_0_M_1) },
},
{
/* MOD_EVEX_0F16_PREFIX_2 */
- { "vmovhpX", { XMM, Vex, EXxmm_mq }, PREFIX_OPCODE },
+ { "vmovhpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
},
{
/* MOD_EVEX_0F17 */
- { "vmovhpX", { EXxmm_mq, XMM }, PREFIX_OPCODE },
+ { "vmovhpX", { EXq, XMM }, PREFIX_OPCODE },
},
{
/* MOD_EVEX_0F2B */
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -111,16 +111,16 @@
/* PREFIX_EVEX_0F78 */
{
{ VEX_W_TABLE (EVEX_W_0F78_P_0) },
- { "vcvttss2usi", { Gdq, EXxmm_md, EXxEVexS }, 0 },
+ { "vcvttss2usi", { Gdq, EXd, EXxEVexS }, 0 },
{ VEX_W_TABLE (EVEX_W_0F78_P_2) },
- { "vcvttsd2usi", { Gdq, EXxmm_mq, EXxEVexS }, 0 },
+ { "vcvttsd2usi", { Gdq, EXq, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_0F79 */
{
{ VEX_W_TABLE (EVEX_W_0F79_P_0) },
- { "vcvtss2usi", { Gdq, EXxmm_md, EXxEVexR }, 0 },
+ { "vcvtss2usi", { Gdq, EXd, EXxEVexR }, 0 },
{ VEX_W_TABLE (EVEX_W_0F79_P_2) },
- { "vcvtsd2usi", { Gdq, EXxmm_mq, EXxEVexR }, 0 },
+ { "vcvtsd2usi", { Gdq, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F7A */
{
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -1,11 +1,11 @@
/* EVEX_W_0F10_P_1 */
{
- { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 },
+ { "vmovss", { XMScalar, VexScalarR, EXd }, 0 },
},
/* EVEX_W_0F10_P_3 */
{
{ Bad_Opcode },
- { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 },
+ { "vmovsd", { XMScalar, VexScalarR, EXq }, 0 },
},
/* EVEX_W_0F11_P_1 */
{
@@ -18,7 +18,7 @@
},
/* EVEX_W_0F12_P_0_M_1 */
{
- { "vmovhlps", { XMM, Vex, EXxmm_mq }, 0 },
+ { "vmovhlps", { XMM, Vex, EXq }, 0 },
},
/* EVEX_W_0F12_P_1 */
{
@@ -39,30 +39,30 @@
},
/* EVEX_W_0F51_P_1 */
{
- { "vsqrtss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 },
+ { "vsqrtss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
},
/* EVEX_W_0F51_P_3 */
{
{ Bad_Opcode },
- { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 },
+ { "vsqrtsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* EVEX_W_0F58_P_1 */
{
- { "vaddss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 },
+ { "vaddss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
},
/* EVEX_W_0F58_P_3 */
{
{ Bad_Opcode },
- { "vaddsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 },
+ { "vaddsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* EVEX_W_0F59_P_1 */
{
- { "vmulss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 },
+ { "vmulss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
},
/* EVEX_W_0F59_P_3 */
{
{ Bad_Opcode },
- { "vmulsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 },
+ { "vmulsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* EVEX_W_0F5A_P_0 */
{
@@ -70,7 +70,7 @@
},
/* EVEX_W_0F5A_P_1 */
{
- { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md, EXxEVexS }, 0 },
+ { "vcvtss2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
},
/* EVEX_W_0F5A_P_2 */
{
@@ -80,7 +80,7 @@
/* EVEX_W_0F5A_P_3 */
{
{ Bad_Opcode },
- { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 },
+ { "vcvtsd2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* EVEX_W_0F5B_P_0 */
{
@@ -97,39 +97,39 @@
},
/* EVEX_W_0F5C_P_1 */
{
- { "vsubss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 },
+ { "vsubss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
},
/* EVEX_W_0F5C_P_3 */
{
{ Bad_Opcode },
- { "vsubsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 },
+ { "vsubsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* EVEX_W_0F5D_P_1 */
{
- { "vminss", { XMScalar, VexScalar, EXxmm_md, EXxEVexS }, 0 },
+ { "vminss", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
},
/* EVEX_W_0F5D_P_3 */
{
{ Bad_Opcode },
- { "vminsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexS }, 0 },
+ { "vminsd", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
},
/* EVEX_W_0F5E_P_1 */
{
- { "vdivss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 },
+ { "vdivss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
},
/* EVEX_W_0F5E_P_3 */
{
{ Bad_Opcode },
- { "vdivsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 },
+ { "vdivsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* EVEX_W_0F5F_P_1 */
{
- { "vmaxss", { XMScalar, VexScalar, EXxmm_md, EXxEVexS }, 0 },
+ { "vmaxss", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
},
/* EVEX_W_0F5F_P_3 */
{
{ Bad_Opcode },
- { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexS }, 0 },
+ { "vmaxsd", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
},
/* EVEX_W_0F62 */
{
@@ -260,12 +260,12 @@
},
/* EVEX_W_0FC2_P_1 */
{
- { "vcmpss", { MaskG, VexScalar, EXxmm_md, EXxEVexS, CMP }, 0 },
+ { "vcmpss", { MaskG, VexScalar, EXd, EXxEVexS, CMP }, 0 },
},
/* EVEX_W_0FC2_P_3 */
{
{ Bad_Opcode },
- { "vcmpsd", { MaskG, VexScalar, EXxmm_mq, EXxEVexS, CMP }, 0 },
+ { "vcmpsd", { MaskG, VexScalar, EXq, EXxEVexS, CMP }, 0 },
},
/* EVEX_W_0FD2 */
{
@@ -382,8 +382,8 @@
},
/* EVEX_W_0F3819_L_n */
{
- { "vbroadcastf32x2", { XM, EXxmm_mq }, PREFIX_DATA },
- { "vbroadcastsd", { XM, EXxmm_mq }, PREFIX_DATA },
+ { "vbroadcastf32x2", { XM, EXq }, PREFIX_DATA },
+ { "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
},
/* EVEX_W_0F381A_M_0_L_n */
{
@@ -499,8 +499,8 @@
},
/* EVEX_W_0F3859 */
{
- { "vbroadcasti32x2", { XM, EXxmm_mq }, PREFIX_DATA },
- { "vpbroadcastq", { XM, EXxmm_mq }, PREFIX_DATA },
+ { "vbroadcasti32x2", { XM, EXq }, PREFIX_DATA },
+ { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
},
/* EVEX_W_0F385A_M_0_L_n */
{
@@ -561,12 +561,12 @@
},
/* EVEX_W_0F3A0A */
{
- { "vrndscaless", { XMScalar, VexScalar, EXxmm_md, EXxEVexS, Ib }, PREFIX_DATA },
+ { "vrndscaless", { XMScalar, VexScalar, EXd, EXxEVexS, Ib }, PREFIX_DATA },
},
/* EVEX_W_0F3A0B */
{
{ Bad_Opcode },
- { "vrndscalesd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexS, Ib }, PREFIX_DATA },
+ { "vrndscalesd", { XMScalar, VexScalar, EXq, EXxEVexS, Ib }, PREFIX_DATA },
},
/* EVEX_W_0F3A18_L_n */
{
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -352,6 +352,7 @@ fetch_data (struct disassemble_info *inf
#define EMd { OP_EM, d_mode }
#define EMx { OP_EM, x_mode }
#define EXbwUnit { OP_EX, bw_unit_mode }
+#define EXb { OP_EX, b_mode }
#define EXw { OP_EX, w_mode }
#define EXd { OP_EX, d_mode }
#define EXdS { OP_EX, d_swap_mode }
@@ -364,10 +365,6 @@ fetch_data (struct disassemble_info *inf
#define EXtmm { OP_EX, tmm_mode }
#define EXxmmq { OP_EX, xmmq_mode }
#define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
-#define EXxmm_mb { OP_EX, xmm_mb_mode }
-#define EXxmm_mw { OP_EX, xmm_mw_mode }
-#define EXxmm_md { OP_EX, xmm_md_mode }
-#define EXxmm_mq { OP_EX, xmm_mq_mode }
#define EXxmmdw { OP_EX, xmmdw_mode }
#define EXxmmqd { OP_EX, xmmqd_mode }
#define EXymmq { OP_EX, ymmq_mode }
@@ -488,14 +485,6 @@ enum
xmmq_mode,
/* Same as xmmq_mode, but broadcast is allowed. */
evex_half_bcst_xmmq_mode,
- /* XMM register or byte memory operand */
- xmm_mb_mode,
- /* XMM register or word memory operand */
- xmm_mw_mode,
- /* XMM register or double word memory operand */
- xmm_md_mode,
- /* XMM register or quad word memory operand */
- xmm_mq_mode,
/* 16-byte XMM, word, double word or quad word operand. */
xmmdw_mode,
/* 16-byte XMM, double word, quad word operand or xmm word operand. */
@@ -3610,9 +3599,9 @@ static const struct dis386 prefix_table[
/* PREFIX_VEX_0F10 */
{
{ "vmovups", { XM, EXx }, 0 },
- { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 },
+ { "vmovss", { XMScalar, VexScalarR, EXd }, 0 },
{ "vmovupd", { XM, EXx }, 0 },
- { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 },
+ { "vmovsd", { XMScalar, VexScalarR, EXq }, 0 },
},
/* PREFIX_VEX_0F11 */
@@ -3649,31 +3638,31 @@ static const struct dis386 prefix_table[
/* PREFIX_VEX_0F2C */
{
{ Bad_Opcode },
- { "vcvttss2si", { Gdq, EXxmm_md, EXxEVexS }, 0 },
+ { "vcvttss2si", { Gdq, EXd, EXxEVexS }, 0 },
{ Bad_Opcode },
- { "vcvttsd2si", { Gdq, EXxmm_mq, EXxEVexS }, 0 },
+ { "vcvttsd2si", { Gdq, EXq, EXxEVexS }, 0 },
},
/* PREFIX_VEX_0F2D */
{
{ Bad_Opcode },
- { "vcvtss2si", { Gdq, EXxmm_md, EXxEVexR }, 0 },
+ { "vcvtss2si", { Gdq, EXd, EXxEVexR }, 0 },
{ Bad_Opcode },
- { "vcvtsd2si", { Gdq, EXxmm_mq, EXxEVexR }, 0 },
+ { "vcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F2E */
{
- { "vucomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
+ { "vucomisX", { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "vucomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
+ { "vucomisX", { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
},
/* PREFIX_VEX_0F2F */
{
- { "vcomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
+ { "vcomisX", { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "vcomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
+ { "vcomisX", { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
},
/* PREFIX_VEX_0F41_L_1_M_1_W_0 */
@@ -3789,45 +3778,45 @@ static const struct dis386 prefix_table[
/* PREFIX_VEX_0F51 */
{
{ "vsqrtps", { XM, EXx }, 0 },
- { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vsqrtss", { XMScalar, VexScalar, EXd }, 0 },
{ "vsqrtpd", { XM, EXx }, 0 },
- { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
+ { "vsqrtsd", { XMScalar, VexScalar, EXq }, 0 },
},
/* PREFIX_VEX_0F52 */
{
{ "vrsqrtps", { XM, EXx }, 0 },
- { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vrsqrtss", { XMScalar, VexScalar, EXd }, 0 },
},
/* PREFIX_VEX_0F53 */
{
{ "vrcpps", { XM, EXx }, 0 },
- { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vrcpss", { XMScalar, VexScalar, EXd }, 0 },
},
/* PREFIX_VEX_0F58 */
{
{ "vaddps", { XM, Vex, EXx }, 0 },
- { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vaddss", { XMScalar, VexScalar, EXd }, 0 },
{ "vaddpd", { XM, Vex, EXx }, 0 },
- { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
+ { "vaddsd", { XMScalar, VexScalar, EXq }, 0 },
},
/* PREFIX_VEX_0F59 */
{
{ "vmulps", { XM, Vex, EXx }, 0 },
- { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vmulss", { XMScalar, VexScalar, EXd }, 0 },
{ "vmulpd", { XM, Vex, EXx }, 0 },
- { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
+ { "vmulsd", { XMScalar, VexScalar, EXq }, 0 },
},
/* PREFIX_VEX_0F5A */
{
{ "vcvtps2pd", { XM, EXxmmq }, 0 },
- { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vcvtss2sd", { XMScalar, VexScalar, EXd }, 0 },
{ "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
- { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 },
+ { "vcvtsd2ss", { XMScalar, VexScalar, EXq }, 0 },
},
/* PREFIX_VEX_0F5B */
@@ -3840,33 +3829,33 @@ static const struct dis386 prefix_table[
/* PREFIX_VEX_0F5C */
{
{ "vsubps", { XM, Vex, EXx }, 0 },
- { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vsubss", { XMScalar, VexScalar, EXd }, 0 },
{ "vsubpd", { XM, Vex, EXx }, 0 },
- { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
+ { "vsubsd", { XMScalar, VexScalar, EXq }, 0 },
},
/* PREFIX_VEX_0F5D */
{
{ "vminps", { XM, Vex, EXx }, 0 },
- { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vminss", { XMScalar, VexScalar, EXd }, 0 },
{ "vminpd", { XM, Vex, EXx }, 0 },
- { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
+ { "vminsd", { XMScalar, VexScalar, EXq }, 0 },
},
/* PREFIX_VEX_0F5E */
{
{ "vdivps", { XM, Vex, EXx }, 0 },
- { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vdivss", { XMScalar, VexScalar, EXd }, 0 },
{ "vdivpd", { XM, Vex, EXx }, 0 },
- { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
+ { "vdivsd", { XMScalar, VexScalar, EXq }, 0 },
},
/* PREFIX_VEX_0F5F */
{
{ "vmaxps", { XM, Vex, EXx }, 0 },
- { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vmaxss", { XMScalar, VexScalar, EXd }, 0 },
{ "vmaxpd", { XM, Vex, EXx }, 0 },
- { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
+ { "vmaxsd", { XMScalar, VexScalar, EXq }, 0 },
},
/* PREFIX_VEX_0F6F */
@@ -4005,9 +3994,9 @@ static const struct dis386 prefix_table[
/* PREFIX_VEX_0FC2 */
{
{ "vcmpps", { XM, Vex, EXx, CMP }, 0 },
- { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
+ { "vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
{ "vcmppd", { XM, Vex, EXx, CMP }, 0 },
- { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
+ { "vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
},
/* PREFIX_VEX_0FD0 */
@@ -6441,8 +6430,8 @@ static const struct dis386 vex_table[][2
/* 08 */
{ "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
{ "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
- { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
- { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
+ { "vroundss", { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
+ { "vroundsd", { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
{ "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
{ "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
{ "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
@@ -6549,12 +6538,12 @@ static const struct dis386 vex_table[][2
/* 68 */
{ "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
{ "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
- { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
- { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
{ "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
{ "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
- { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
- { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
/* 70 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -6567,12 +6556,12 @@ static const struct dis386 vex_table[][2
/* 78 */
{ "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
{ "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
- { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
- { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfnmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfnmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
{ "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
{ "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
- { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
- { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfnmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfnmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
/* 80 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -6813,7 +6802,7 @@ static const struct dis386 vex_len_table
/* VEX_LEN_0F7E_P_1 */
{
- { "vmovq", { XMScalar, EXxmm_mq }, 0 },
+ { "vmovq", { XMScalar, EXq }, 0 },
},
/* VEX_LEN_0F7E_P_2 */
@@ -7533,11 +7522,11 @@ static const struct dis386 vex_w_table[]
},
{
/* VEX_W_0F3818 */
- { "vbroadcastss", { XM, EXxmm_md }, PREFIX_DATA },
+ { "vbroadcastss", { XM, EXd }, PREFIX_DATA },
},
{
/* VEX_W_0F3819_L_1 */
- { "vbroadcastsd", { XM, EXxmm_mq }, PREFIX_DATA },
+ { "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
},
{
/* VEX_W_0F381A_M_0_L_1 */
@@ -7609,11 +7598,11 @@ static const struct dis386 vex_w_table[]
},
{
/* VEX_W_0F3858 */
- { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
+ { "vpbroadcastd", { XM, EXd }, PREFIX_DATA },
},
{
/* VEX_W_0F3859 */
- { "vpbroadcastq", { XM, EXxmm_mq }, PREFIX_DATA },
+ { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
},
{
/* VEX_W_0F385A_M_0_L_0 */
@@ -7641,11 +7630,11 @@ static const struct dis386 vex_w_table[]
},
{
/* VEX_W_0F3878 */
- { "vpbroadcastb", { XM, EXxmm_mb }, PREFIX_DATA },
+ { "vpbroadcastb", { XM, EXb }, PREFIX_DATA },
},
{
/* VEX_W_0F3879 */
- { "vpbroadcastw", { XM, EXxmm_mw }, PREFIX_DATA },
+ { "vpbroadcastw", { XM, EXw }, PREFIX_DATA },
},
{
/* VEX_W_0F38CF */
@@ -11107,66 +11096,6 @@ intel_operand_size (int bytemode, int si
abort ();
}
break;
- case xmm_mb_mode:
- if (!need_vex)
- abort ();
-
- switch (vex.length)
- {
- case 128:
- case 256:
- case 512:
- oappend ("BYTE PTR ");
- break;
- default:
- abort ();
- }
- break;
- case xmm_mw_mode:
- if (!need_vex)
- abort ();
-
- switch (vex.length)
- {
- case 128:
- case 256:
- case 512:
- oappend ("WORD PTR ");
- break;
- default:
- abort ();
- }
- break;
- case xmm_md_mode:
- if (!need_vex)
- abort ();
-
- switch (vex.length)
- {
- case 128:
- case 256:
- case 512:
- oappend ("DWORD PTR ");
- break;
- default:
- abort ();
- }
- break;
- case xmm_mq_mode:
- if (!need_vex)
- abort ();
-
- switch (vex.length)
- {
- case 128:
- case 256:
- case 512:
- oappend ("QWORD PTR ");
- break;
- default:
- abort ();
- }
- break;
case xmmdw_mode:
if (!need_vex)
abort ();
@@ -11424,19 +11353,18 @@ OP_E_memory (int bytemode, int sizeflag)
{
case dqw_mode:
case dw_mode:
- case xmm_mw_mode:
+ case w_mode:
shift = 1;
break;
case dqb_mode:
case db_mode:
- case xmm_mb_mode:
+ case b_mode:
shift = 0;
break;
case dq_mode:
if (address_mode != mode_64bit)
{
case dqd_mode:
- case xmm_md_mode:
case d_mode:
case d_swap_mode:
shift = 2;
@@ -11493,7 +11421,6 @@ OP_E_memory (int bytemode, int sizeflag)
case xmm_mode:
shift = 4;
break;
- case xmm_mq_mode:
case q_mode:
case q_swap_mode:
shift = 3;
@@ -12566,10 +12493,10 @@ print_vector_reg (unsigned int reg, int
&& bytemode != scalar_mode
&& bytemode != xmmdw_mode
&& bytemode != xmmqd_mode
- && bytemode != xmm_mb_mode
- && bytemode != xmm_mw_mode
- && bytemode != xmm_md_mode
- && bytemode != xmm_mq_mode
+ && bytemode != b_mode
+ && bytemode != w_mode
+ && bytemode != d_mode
+ && bytemode != q_mode
&& bytemode != vex_scalar_w_dq_mode)
{
switch (vex.length)
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 11/12] x86: drop vex_scalar_w_dq_mode
2021-07-21 10:07 [PATCH 00/12] x86: disassembler fixes and some consolidation Jan Beulich
` (9 preceding siblings ...)
2021-07-21 10:22 ` [PATCH 10/12] x86: drop xmm_m{b,w,d,q}_mode Jan Beulich
@ 2021-07-21 10:23 ` Jan Beulich
2021-07-21 10:23 ` [PATCH 12/12] x86: drop dq{b,d}_mode Jan Beulich
2021-07-21 12:56 ` [PATCH 00/12] x86: disassembler fixes and some consolidation H.J. Lu
12 siblings, 0 replies; 16+ messages in thread
From: Jan Beulich @ 2021-07-21 10:23 UTC (permalink / raw)
To: Binutils
It has only a single use and can easily be represented by dq_mode
instead. Plus its handling in intel_operand_size() was duplicating
that of vex_vsib_{d,q}_w_dq_mode anyway.
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -358,7 +358,7 @@
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
+ { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
{ "v4fmaddss", { XMScalar, VexScalar, Mxmm }, 0 },
},
/* PREFIX_EVEX_0F38AA */
@@ -372,6 +372,6 @@
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
+ { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
{ "v4fnmaddss", { XMScalar, VexScalar, Mxmm }, 0 },
},
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -343,7 +343,7 @@ static const struct dis386 evex_table[][
{ PREFIX_TABLE (PREFIX_EVEX_0F382A) },
{ VEX_W_TABLE (EVEX_W_0F382B) },
{ "vscalefp%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vscalefs%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vscalefs%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
/* 30 */
@@ -368,7 +368,7 @@ static const struct dis386 evex_table[][
{ "vpmull%DQ", { XM, Vex, EXx }, PREFIX_DATA },
{ Bad_Opcode },
{ "vgetexpp%XW", { XM, EXx, EXxEVexS }, PREFIX_DATA },
- { "vgetexps%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexS }, PREFIX_DATA },
+ { "vgetexps%XW", { XMScalar, VexScalar, EXdq, EXxEVexS }, PREFIX_DATA },
{ "vplzcnt%DQ", { XM, EXx }, PREFIX_DATA },
{ "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpsrav%DQ", { XM, Vex, EXx }, PREFIX_DATA },
@@ -379,9 +379,9 @@ static const struct dis386 evex_table[][
{ Bad_Opcode },
{ Bad_Opcode },
{ "vrcp14p%XW", { XM, EXx }, PREFIX_DATA },
- { "vrcp14s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vrcp14s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vrsqrt14p%XW", { XM, EXx }, 0 },
- { "vrsqrt14s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vrsqrt14s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
/* 50 */
{ "vpdpbusd", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpdpbusds", { XM, Vex, EXx }, PREFIX_DATA },
@@ -465,13 +465,13 @@ static const struct dis386 evex_table[][
{ "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
/* 98 */
{ "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ PREFIX_TABLE (PREFIX_EVEX_0F389A) },
{ PREFIX_TABLE (PREFIX_EVEX_0F389B) },
{ "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
/* A0 */
{ "vpscatterd%DQ", { MVexVSIBDWpX, XM }, PREFIX_DATA },
{ "vpscatterq%DQ", { MVexVSIBQWpX, XMGatherQ }, PREFIX_DATA },
@@ -483,13 +483,13 @@ static const struct dis386 evex_table[][
{ "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
/* A8 */
{ "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ PREFIX_TABLE (PREFIX_EVEX_0F38AA) },
{ PREFIX_TABLE (PREFIX_EVEX_0F38AB) },
{ "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
/* B0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -501,13 +501,13 @@ static const struct dis386 evex_table[][
{ "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
/* B8 */
{ "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
/* C0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -521,9 +521,9 @@ static const struct dis386 evex_table[][
{ "vexp2p%XW", { XM, EXx, EXxEVexS }, PREFIX_DATA },
{ Bad_Opcode },
{ "vrcp28p%XW", { XM, EXx, EXxEVexS }, PREFIX_DATA },
- { "vrcp28s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexS }, PREFIX_DATA },
+ { "vrcp28s%XW", { XMScalar, VexScalar, EXdq, EXxEVexS }, PREFIX_DATA },
{ "vrsqrt28p%XW", { XM, EXx, EXxEVexS }, PREFIX_DATA },
- { "vrsqrt28s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexS }, PREFIX_DATA },
+ { "vrsqrt28s%XW", { XMScalar, VexScalar, EXdq, EXxEVexS }, PREFIX_DATA },
{ Bad_Opcode },
{ VEX_W_TABLE (VEX_W_0F38CF) },
/* D0 */
@@ -627,7 +627,7 @@ static const struct dis386 evex_table[][
{ Bad_Opcode },
{ "vpternlog%DQ", { XM, Vex, EXx, Ib }, PREFIX_DATA },
{ "vgetmantp%XW", { XM, EXx, EXxEVexS, Ib }, PREFIX_DATA },
- { "vgetmants%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexS, Ib }, PREFIX_DATA },
+ { "vgetmants%XW", { XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, PREFIX_DATA },
/* 28 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -675,13 +675,13 @@ static const struct dis386 evex_table[][
{ Bad_Opcode },
/* 50 */
{ "vrangep%XW", { XM, Vex, EXx, EXxEVexS, Ib }, PREFIX_DATA },
- { "vranges%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexS, Ib }, PREFIX_DATA },
+ { "vranges%XW", { XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
{ "vfixupimmp%XW", { XM, Vex, EXx, EXxEVexS, Ib }, PREFIX_DATA },
- { "vfixupimms%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexS, Ib }, PREFIX_DATA },
+ { "vfixupimms%XW", { XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, PREFIX_DATA },
{ "vreducep%XW", { XM, EXx, EXxEVexS, Ib }, PREFIX_DATA },
- { "vreduces%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexS, Ib }, PREFIX_DATA },
+ { "vreduces%XW", { XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, PREFIX_DATA },
/* 58 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -699,7 +699,7 @@ static const struct dis386 evex_table[][
{ Bad_Opcode },
{ Bad_Opcode },
{ "vfpclassp%XW%XZ", { MaskG, EXx, Ib }, PREFIX_DATA },
- { "vfpclasss%XW", { MaskG, EXVexWdqScalar, Ib }, PREFIX_DATA },
+ { "vfpclasss%XW", { MaskG, EXdq, Ib }, PREFIX_DATA },
/* 68 */
{ Bad_Opcode },
{ Bad_Opcode },
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -358,6 +358,7 @@ fetch_data (struct disassemble_info *inf
#define EXdS { OP_EX, d_swap_mode }
#define EXq { OP_EX, q_mode }
#define EXqS { OP_EX, q_swap_mode }
+#define EXdq { OP_EX, dq_mode }
#define EXx { OP_EX, x_mode }
#define EXxS { OP_EX, x_swap_mode }
#define EXxmm { OP_EX, xmm_mode }
@@ -368,7 +369,6 @@ fetch_data (struct disassemble_info *inf
#define EXxmmdw { OP_EX, xmmdw_mode }
#define EXxmmqd { OP_EX, xmmqd_mode }
#define EXymmq { OP_EX, ymmq_mode }
-#define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
#define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
#define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
#define MS { OP_MS, v_mode }
@@ -507,7 +507,7 @@ enum
v_bnd_mode,
/* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
v_bndmk_mode,
- /* operand size depends on REX prefixes. */
+ /* operand size depends on REX.W / VEX.W. */
dq_mode,
/* registers like dq_mode, memory like w_mode, displacements like
v_mode without considering Intel64 ISA. */
@@ -545,8 +545,6 @@ enum
/* scalar, ignore vector length. */
scalar_mode,
- /* Operand size depends on the VEX.W bit, ignore vector length. */
- vex_scalar_w_dq_mode,
/* Static rounding. */
evex_rounding_mode,
@@ -6300,13 +6298,13 @@ static const struct dis386 vex_table[][2
{ "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
/* 98 */
{ "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
/* a0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -6318,13 +6316,13 @@ static const struct dis386 vex_table[][2
{ "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
/* a8 */
{ "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
/* b0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -6336,13 +6334,13 @@ static const struct dis386 vex_table[][2
{ "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
/* b8 */
{ "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
/* c0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -11170,15 +11168,6 @@ intel_operand_size (int bytemode, int si
case o_mode:
oappend ("OWORD PTR ");
break;
- case vex_scalar_w_dq_mode:
- if (!need_vex)
- abort ();
-
- if (vex.w)
- oappend ("QWORD PTR ");
- else
- oappend ("DWORD PTR ");
- break;
case vex_vsib_d_w_dq_mode:
case vex_vsib_q_w_dq_mode:
if (!need_vex)
@@ -11371,7 +11360,6 @@ OP_E_memory (int bytemode, int sizeflag)
break;
}
/* fall through */
- case vex_scalar_w_dq_mode:
case vex_vsib_d_w_dq_mode:
case vex_vsib_q_w_dq_mode:
case evex_x_gscat_mode:
@@ -12496,8 +12484,7 @@ print_vector_reg (unsigned int reg, int
&& bytemode != b_mode
&& bytemode != w_mode
&& bytemode != d_mode
- && bytemode != q_mode
- && bytemode != vex_scalar_w_dq_mode)
+ && bytemode != q_mode)
{
switch (vex.length)
{
@@ -12627,6 +12614,9 @@ OP_EX (int bytemode, int sizeflag)
MODRM_CHECK;
codep++;
+ if (bytemode == dq_mode)
+ bytemode = vex.w ? q_mode : d_mode;
+
if (modrm.mod != 3)
{
OP_E_memory (bytemode, sizeflag);
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 12/12] x86: drop dq{b,d}_mode
2021-07-21 10:07 [PATCH 00/12] x86: disassembler fixes and some consolidation Jan Beulich
` (10 preceding siblings ...)
2021-07-21 10:23 ` [PATCH 11/12] x86: drop vex_scalar_w_dq_mode Jan Beulich
@ 2021-07-21 10:23 ` Jan Beulich
2021-07-21 12:56 ` [PATCH 00/12] x86: disassembler fixes and some consolidation H.J. Lu
12 siblings, 0 replies; 16+ messages in thread
From: Jan Beulich @ 2021-07-21 10:23 UTC (permalink / raw)
To: Binutils
Their sole use is for {,V}EXTRACTPS / {,V}P{EXT,INS}RB respectively; for
consistency also limit use of dqw_mode to Jdqw. 64-bit disassembly
reflecting REX.W / VEX.W is not in line with the assembler's opcode
table having NoRex64 / VexWIG in all respective templates, i.e. assembly
input isn't being honored there either. Obviously the 0FC5 encodings of
{,V}PEXTRW then also need adjustment for consistency reasons.
--- a/gas/testsuite/gas/i386/x86-64-avx-wig.d
+++ b/gas/testsuite/gas/i386/x86-64-avx-wig.d
@@ -58,7 +58,7 @@ Disassembly of section .text:
+[a-f0-9]+: c4 e1 ca 5e d4 vdivss %xmm4,%xmm6,%xmm2
+[a-f0-9]+: c4 e3 c9 41 d4 07 vdppd \$0x7,%xmm4,%xmm6,%xmm2
+[a-f0-9]+: c4 e3 cd 40 d4 07 vdpps \$0x7,%ymm4,%ymm6,%ymm2
- +[a-f0-9]+: c4 e3 f9 17 e1 07 vextractps \$0x7,%xmm4,%rcx
+ +[a-f0-9]+: c4 e3 f9 17 e1 07 vextractps \$0x7,%xmm4,%ecx
+[a-f0-9]+: c4 e1 cd 7c d4 vhaddpd %ymm4,%ymm6,%ymm2
+[a-f0-9]+: c4 e1 cf 7c d4 vhaddps %ymm4,%ymm6,%ymm2
+[a-f0-9]+: c4 e1 cd 7d d4 vhsubpd %ymm4,%ymm6,%ymm2
@@ -157,10 +157,10 @@ Disassembly of section .text:
+[a-f0-9]+: c4 e1 c9 65 d4 vpcmpgtw %xmm4,%xmm6,%xmm2
+[a-f0-9]+: c4 e3 f9 63 f4 07 vpcmpistri \$0x7,%xmm4,%xmm6
+[a-f0-9]+: c4 e3 f9 62 f4 07 vpcmpistrm \$0x7,%xmm4,%xmm6
- +[a-f0-9]+: c4 e3 f9 14 c0 00 vpextrb \$0x0,%xmm0,%rax
+ +[a-f0-9]+: c4 e3 f9 14 c0 00 vpextrb \$0x0,%xmm0,%eax
+[a-f0-9]+: c4 e3 f9 14 00 00 vpextrb \$0x0,%xmm0,\(%rax\)
- +[a-f0-9]+: c4 e1 f9 c5 c0 00 vpextrw \$0x0,%xmm0,%rax
- +[a-f0-9]+: c4 e3 f9 15 c0 00 vpextrw \$0x0,%xmm0,%rax
+ +[a-f0-9]+: c4 e1 f9 c5 c0 00 vpextrw \$0x0,%xmm0,%eax
+ +[a-f0-9]+: c4 e3 f9 15 c0 00 vpextrw \$0x0,%xmm0,%eax
+[a-f0-9]+: c4 e3 f9 15 00 00 vpextrw \$0x0,%xmm0,\(%rax\)
+[a-f0-9]+: c4 e2 c9 02 d4 vphaddd %xmm4,%xmm6,%xmm2
+[a-f0-9]+: c4 e2 c9 03 d4 vphaddsw %xmm4,%xmm6,%xmm2
@@ -169,9 +169,9 @@ Disassembly of section .text:
+[a-f0-9]+: c4 e2 c9 06 d4 vphsubd %xmm4,%xmm6,%xmm2
+[a-f0-9]+: c4 e2 c9 07 d4 vphsubsw %xmm4,%xmm6,%xmm2
+[a-f0-9]+: c4 e2 c9 05 d4 vphsubw %xmm4,%xmm6,%xmm2
- +[a-f0-9]+: c4 e3 f9 20 c0 00 vpinsrb \$0x0,%rax,%xmm0,%xmm0
+ +[a-f0-9]+: c4 e3 f9 20 c0 00 vpinsrb \$0x0,%eax,%xmm0,%xmm0
+[a-f0-9]+: c4 e3 f9 20 00 00 vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
- +[a-f0-9]+: c4 e1 f9 c4 c0 00 vpinsrw \$0x0,%rax,%xmm0,%xmm0
+ +[a-f0-9]+: c4 e1 f9 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
+[a-f0-9]+: c4 e1 f9 c4 00 00 vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
+[a-f0-9]+: c4 e2 c9 04 d4 vpmaddubsw %xmm4,%xmm6,%xmm2
+[a-f0-9]+: c4 e1 c9 f5 d4 vpmaddwd %xmm4,%xmm6,%xmm2
--- a/gas/testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d
@@ -159,9 +159,9 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 aa 00 20 00 00[ ]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx\+0x2000\]
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 6a 80[ ]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx-0x2000\]
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 aa c0 df ff ff[ ]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx-0x2040\]
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb rax,xmm29,0xab
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb rax,xmm29,0x7b
-[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb r8,xmm29,0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb eax,xmm29,0xab
+[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb eax,xmm29,0x7b
+[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb r8d,xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 29 7b[ ]*vpextrb BYTE PTR \[rcx\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 23 fd 08 14 ac f0 23 01 00 00 7b[ ]*vpextrb BYTE PTR \[rax\+r14\*8\+0x123\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 6a 7f 7b[ ]*vpextrb BYTE PTR \[rdx\+0x7f\],xmm29,0x7b
@@ -174,23 +174,23 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 aa 00 01 00 00 7b[ ]*vpextrw WORD PTR \[rdx\+0x100\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 6a 80 7b[ ]*vpextrw WORD PTR \[rdx-0x100\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 aa fe fe ff ff 7b[ ]*vpextrw WORD PTR \[rdx-0x102\],xmm29,0x7b
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw rax,xmm30,0xab
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw rax,xmm30,0x7b
-[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw r8,xmm30,0x7b
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 ab[ ]*vpinsrb xmm30,xmm29,rax,0xab
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 7b[ ]*vpinsrb xmm30,xmm29,rax,0x7b
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,rbp,0x7b
-[ ]*[a-f0-9]+:[ ]*62 43 95 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,r13,0x7b
+[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw eax,xmm30,0xab
+[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw eax,xmm30,0x7b
+[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw r8d,xmm30,0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 ab[ ]*vpinsrb xmm30,xmm29,eax,0xab
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 7b[ ]*vpinsrb xmm30,xmm29,eax,0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,ebp,0x7b
+[ ]*[a-f0-9]+:[ ]*62 43 95 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,r13d,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 31 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rcx\],0x7b
[ ]*[a-f0-9]+:[ ]*62 23 95 00 20 b4 f0 23 01 00 00 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rax\+r14\*8\+0x123\],0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 72 7f 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx\+0x7f\],0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 b2 80 00 00 00 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx\+0x80\],0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 72 80 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx-0x80\],0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 b2 7f ff ff ff 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx-0x81\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 ab[ ]*vpinsrw xmm30,xmm29,rax,0xab
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 7b[ ]*vpinsrw xmm30,xmm29,rax,0x7b
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f5 7b[ ]*vpinsrw xmm30,xmm29,rbp,0x7b
-[ ]*[a-f0-9]+:[ ]*62 41 95 00 c4 f5 7b[ ]*vpinsrw xmm30,xmm29,r13,0x7b
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 ab[ ]*vpinsrw xmm30,xmm29,eax,0xab
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 7b[ ]*vpinsrw xmm30,xmm29,eax,0x7b
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f5 7b[ ]*vpinsrw xmm30,xmm29,ebp,0x7b
+[ ]*[a-f0-9]+:[ ]*62 41 95 00 c4 f5 7b[ ]*vpinsrw xmm30,xmm29,r13d,0x7b
[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 31 7b[ ]*vpinsrw xmm30,xmm29,WORD PTR \[rcx\],0x7b
[ ]*[a-f0-9]+:[ ]*62 21 95 00 c4 b4 f0 23 01 00 00 7b[ ]*vpinsrw xmm30,xmm29,WORD PTR \[rax\+r14\*8\+0x123\],0x7b
[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 72 7f 7b[ ]*vpinsrw xmm30,xmm29,WORD PTR \[rdx\+0xfe\],0x7b
@@ -690,9 +690,9 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 aa 00 20 00 00[ ]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx\+0x2000\]
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 6a 80[ ]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx-0x2000\]
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 aa c0 df ff ff[ ]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx-0x2040\]
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb rax,xmm29,0xab
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb rax,xmm29,0x7b
-[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb r8,xmm29,0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb eax,xmm29,0xab
+[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb eax,xmm29,0x7b
+[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb r8d,xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 29 7b[ ]*vpextrb BYTE PTR \[rcx\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 23 fd 08 14 ac f0 34 12 00 00 7b[ ]*vpextrb BYTE PTR \[rax\+r14\*8\+0x1234\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 6a 7f 7b[ ]*vpextrb BYTE PTR \[rdx\+0x7f\],xmm29,0x7b
@@ -705,23 +705,23 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 aa 00 01 00 00 7b[ ]*vpextrw WORD PTR \[rdx\+0x100\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 6a 80 7b[ ]*vpextrw WORD PTR \[rdx-0x100\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 aa fe fe ff ff 7b[ ]*vpextrw WORD PTR \[rdx-0x102\],xmm29,0x7b
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw rax,xmm30,0xab
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw rax,xmm30,0x7b
-[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw r8,xmm30,0x7b
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 ab[ ]*vpinsrb xmm30,xmm29,rax,0xab
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 7b[ ]*vpinsrb xmm30,xmm29,rax,0x7b
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,rbp,0x7b
-[ ]*[a-f0-9]+:[ ]*62 43 95 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,r13,0x7b
+[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw eax,xmm30,0xab
+[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw eax,xmm30,0x7b
+[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw r8d,xmm30,0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 ab[ ]*vpinsrb xmm30,xmm29,eax,0xab
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 7b[ ]*vpinsrb xmm30,xmm29,eax,0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,ebp,0x7b
+[ ]*[a-f0-9]+:[ ]*62 43 95 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,r13d,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 31 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rcx\],0x7b
[ ]*[a-f0-9]+:[ ]*62 23 95 00 20 b4 f0 34 12 00 00 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rax\+r14\*8\+0x1234\],0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 72 7f 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx\+0x7f\],0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 b2 80 00 00 00 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx\+0x80\],0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 72 80 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx-0x80\],0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 b2 7f ff ff ff 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx-0x81\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 ab[ ]*vpinsrw xmm30,xmm29,rax,0xab
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 7b[ ]*vpinsrw xmm30,xmm29,rax,0x7b
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f5 7b[ ]*vpinsrw xmm30,xmm29,rbp,0x7b
-[ ]*[a-f0-9]+:[ ]*62 41 95 00 c4 f5 7b[ ]*vpinsrw xmm30,xmm29,r13,0x7b
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 ab[ ]*vpinsrw xmm30,xmm29,eax,0xab
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 7b[ ]*vpinsrw xmm30,xmm29,eax,0x7b
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f5 7b[ ]*vpinsrw xmm30,xmm29,ebp,0x7b
+[ ]*[a-f0-9]+:[ ]*62 41 95 00 c4 f5 7b[ ]*vpinsrw xmm30,xmm29,r13d,0x7b
[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 31 7b[ ]*vpinsrw xmm30,xmm29,WORD PTR \[rcx\],0x7b
[ ]*[a-f0-9]+:[ ]*62 21 95 00 c4 b4 f0 34 12 00 00 7b[ ]*vpinsrw xmm30,xmm29,WORD PTR \[rax\+r14\*8\+0x1234\],0x7b
[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 72 7f 7b[ ]*vpinsrw xmm30,xmm29,WORD PTR \[rdx\+0xfe\],0x7b
--- a/gas/testsuite/gas/i386/x86-64-avx512bw-wig1.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512bw-wig1.d
@@ -159,9 +159,9 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 aa 00 20 00 00[ ]*vpcmpgtw 0x2000\(%rdx\),%zmm30,%k5
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 6a 80[ ]*vpcmpgtw -0x2000\(%rdx\),%zmm30,%k5
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 aa c0 df ff ff[ ]*vpcmpgtw -0x2040\(%rdx\),%zmm30,%k5
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb \$0xab,%xmm29,%rax
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%rax
-[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%r8
+[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb \$0xab,%xmm29,%eax
+[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%eax
+[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%r8d
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 29 7b[ ]*vpextrb \$0x7b,%xmm29,\(%rcx\)
[ ]*[a-f0-9]+:[ ]*62 23 fd 08 14 ac f0 23 01 00 00 7b[ ]*vpextrb \$0x7b,%xmm29,0x123\(%rax,%r14,8\)
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 6a 7f 7b[ ]*vpextrb \$0x7b,%xmm29,0x7f\(%rdx\)
@@ -174,23 +174,23 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 aa 00 01 00 00 7b[ ]*vpextrw \$0x7b,%xmm29,0x100\(%rdx\)
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 6a 80 7b[ ]*vpextrw \$0x7b,%xmm29,-0x100\(%rdx\)
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 aa fe fe ff ff 7b[ ]*vpextrw \$0x7b,%xmm29,-0x102\(%rdx\)
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw \$0xab,%xmm30,%rax
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%rax
-[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%r8
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 ab[ ]*vpinsrb \$0xab,%rax,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 7b[ ]*vpinsrb \$0x7b,%rax,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f5 7b[ ]*vpinsrb \$0x7b,%rbp,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 43 95 00 20 f5 7b[ ]*vpinsrb \$0x7b,%r13,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw \$0xab,%xmm30,%eax
+[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%eax
+[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%r8d
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 ab[ ]*vpinsrb \$0xab,%eax,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 7b[ ]*vpinsrb \$0x7b,%eax,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f5 7b[ ]*vpinsrb \$0x7b,%ebp,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 43 95 00 20 f5 7b[ ]*vpinsrb \$0x7b,%r13d,%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 31 7b[ ]*vpinsrb \$0x7b,\(%rcx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 23 95 00 20 b4 f0 23 01 00 00 7b[ ]*vpinsrb \$0x7b,0x123\(%rax,%r14,8\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 72 7f 7b[ ]*vpinsrb \$0x7b,0x7f\(%rdx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 b2 80 00 00 00 7b[ ]*vpinsrb \$0x7b,0x80\(%rdx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 72 80 7b[ ]*vpinsrb \$0x7b,-0x80\(%rdx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 b2 7f ff ff ff 7b[ ]*vpinsrb \$0x7b,-0x81\(%rdx\),%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 ab[ ]*vpinsrw \$0xab,%rax,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 7b[ ]*vpinsrw \$0x7b,%rax,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f5 7b[ ]*vpinsrw \$0x7b,%rbp,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 41 95 00 c4 f5 7b[ ]*vpinsrw \$0x7b,%r13,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 ab[ ]*vpinsrw \$0xab,%eax,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 7b[ ]*vpinsrw \$0x7b,%eax,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f5 7b[ ]*vpinsrw \$0x7b,%ebp,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 41 95 00 c4 f5 7b[ ]*vpinsrw \$0x7b,%r13d,%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 31 7b[ ]*vpinsrw \$0x7b,\(%rcx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 21 95 00 c4 b4 f0 23 01 00 00 7b[ ]*vpinsrw \$0x7b,0x123\(%rax,%r14,8\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 72 7f 7b[ ]*vpinsrw \$0x7b,0xfe\(%rdx\),%xmm29,%xmm30
@@ -690,9 +690,9 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 aa 00 20 00 00[ ]*vpcmpgtw 0x2000\(%rdx\),%zmm30,%k5
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 6a 80[ ]*vpcmpgtw -0x2000\(%rdx\),%zmm30,%k5
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 aa c0 df ff ff[ ]*vpcmpgtw -0x2040\(%rdx\),%zmm30,%k5
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb \$0xab,%xmm29,%rax
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%rax
-[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%r8
+[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb \$0xab,%xmm29,%eax
+[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%eax
+[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%r8d
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 29 7b[ ]*vpextrb \$0x7b,%xmm29,\(%rcx\)
[ ]*[a-f0-9]+:[ ]*62 23 fd 08 14 ac f0 34 12 00 00 7b[ ]*vpextrb \$0x7b,%xmm29,0x1234\(%rax,%r14,8\)
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 6a 7f 7b[ ]*vpextrb \$0x7b,%xmm29,0x7f\(%rdx\)
@@ -705,23 +705,23 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 aa 00 01 00 00 7b[ ]*vpextrw \$0x7b,%xmm29,0x100\(%rdx\)
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 6a 80 7b[ ]*vpextrw \$0x7b,%xmm29,-0x100\(%rdx\)
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 aa fe fe ff ff 7b[ ]*vpextrw \$0x7b,%xmm29,-0x102\(%rdx\)
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw \$0xab,%xmm30,%rax
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%rax
-[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%r8
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 ab[ ]*vpinsrb \$0xab,%rax,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 7b[ ]*vpinsrb \$0x7b,%rax,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f5 7b[ ]*vpinsrb \$0x7b,%rbp,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 43 95 00 20 f5 7b[ ]*vpinsrb \$0x7b,%r13,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw \$0xab,%xmm30,%eax
+[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%eax
+[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%r8d
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 ab[ ]*vpinsrb \$0xab,%eax,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 7b[ ]*vpinsrb \$0x7b,%eax,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f5 7b[ ]*vpinsrb \$0x7b,%ebp,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 43 95 00 20 f5 7b[ ]*vpinsrb \$0x7b,%r13d,%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 31 7b[ ]*vpinsrb \$0x7b,\(%rcx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 23 95 00 20 b4 f0 34 12 00 00 7b[ ]*vpinsrb \$0x7b,0x1234\(%rax,%r14,8\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 72 7f 7b[ ]*vpinsrb \$0x7b,0x7f\(%rdx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 b2 80 00 00 00 7b[ ]*vpinsrb \$0x7b,0x80\(%rdx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 72 80 7b[ ]*vpinsrb \$0x7b,-0x80\(%rdx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 b2 7f ff ff ff 7b[ ]*vpinsrb \$0x7b,-0x81\(%rdx\),%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 ab[ ]*vpinsrw \$0xab,%rax,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 7b[ ]*vpinsrw \$0x7b,%rax,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f5 7b[ ]*vpinsrw \$0x7b,%rbp,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 41 95 00 c4 f5 7b[ ]*vpinsrw \$0x7b,%r13,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 ab[ ]*vpinsrw \$0xab,%eax,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 7b[ ]*vpinsrw \$0x7b,%eax,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f5 7b[ ]*vpinsrw \$0x7b,%ebp,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 41 95 00 c4 f5 7b[ ]*vpinsrw \$0x7b,%r13d,%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 31 7b[ ]*vpinsrw \$0x7b,\(%rcx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 21 95 00 c4 b4 f0 34 12 00 00 7b[ ]*vpinsrw \$0x7b,0x1234\(%rax,%r14,8\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 72 7f 7b[ ]*vpinsrw \$0x7b,0xfe\(%rdx\),%xmm29,%xmm30
--- a/gas/testsuite/gas/i386/x86-64-evex-wig1-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-evex-wig1-intel.d
@@ -9,23 +9,23 @@
Disassembly of section .text:
0+ <_start>:
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps rax,xmm29,0xab
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps rax,xmm29,0x7b
-[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps r8,xmm29,0x7b
+[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps eax,xmm29,0xab
+[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps eax,xmm29,0x7b
+[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps r8d,xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 fd 08 17 29 7b vextractps DWORD PTR \[rcx\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 23 fd 08 17 ac f0 23 01 00 00 7b vextractps DWORD PTR \[rax\+r14\*8\+0x123\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 7f 7b vextractps DWORD PTR \[rdx\+0x1fc\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 fd 08 17 aa 00 02 00 00 7b vextractps DWORD PTR \[rdx\+0x200\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 80 7b vextractps DWORD PTR \[rdx-0x200\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 fd 08 17 aa fc fd ff ff 7b vextractps DWORD PTR \[rdx-0x204\],xmm29,0x7b
-[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 vpextrb rax,xmm0,0x0
+[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 vpextrb eax,xmm0,0x0
[ ]*[a-f0-9]+: 62 f3 fd 08 14 00 00 vpextrb BYTE PTR \[rax\],xmm0,0x0
-[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 vpextrw rax,xmm0,0x0
-[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 vpextrw rax,xmm0,0x0
+[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 vpextrw eax,xmm0,0x0
+[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 vpextrw eax,xmm0,0x0
[ ]*[a-f0-9]+: 62 f3 fd 08 15 00 00 vpextrw WORD PTR \[rax\],xmm0,0x0
-[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 vpinsrb xmm0,xmm0,rax,0x0
+[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 vpinsrb xmm0,xmm0,eax,0x0
[ ]*[a-f0-9]+: 62 f3 fd 08 20 00 00 vpinsrb xmm0,xmm0,BYTE PTR \[rax\],0x0
-[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw xmm0,xmm0,rax,0x0
+[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw xmm0,xmm0,eax,0x0
[ ]*[a-f0-9]+: 62 f1 fd 08 c4 00 00 vpinsrw xmm0,xmm0,WORD PTR \[rax\],0x0
[ ]*[a-f0-9]+: 62 02 fd 4f 21 f5 vpmovsxbd zmm30\{k7\},xmm29
[ ]*[a-f0-9]+: 62 02 fd cf 21 f5 vpmovsxbd zmm30\{k7\}\{z\},xmm29
@@ -91,9 +91,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 62 fd 4f 34 b2 00 08 00 00 vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rdx\+0x800\]
[ ]*[a-f0-9]+: 62 62 fd 4f 34 72 80 vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rdx-0x800\]
[ ]*[a-f0-9]+: 62 62 fd 4f 34 b2 f0 f7 ff ff vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rdx-0x810\]
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps rax,xmm29,0xab
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps rax,xmm29,0x7b
-[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps r8,xmm29,0x7b
+[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps eax,xmm29,0xab
+[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps eax,xmm29,0x7b
+[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps r8d,xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 fd 08 17 29 7b vextractps DWORD PTR \[rcx\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 23 fd 08 17 ac f0 34 12 00 00 7b vextractps DWORD PTR \[rax\+r14\*8\+0x1234\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 7f 7b vextractps DWORD PTR \[rdx\+0x1fc\],xmm29,0x7b
--- a/gas/testsuite/gas/i386/x86-64-evex-wig1.d
+++ b/gas/testsuite/gas/i386/x86-64-evex-wig1.d
@@ -9,23 +9,23 @@
Disassembly of section .text:
0+ <_start>:
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps \$0xab,%xmm29,%rax
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%rax
-[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%r8
+[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps \$0xab,%xmm29,%eax
+[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%eax
+[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%r8d
[ ]*[a-f0-9]+: 62 63 fd 08 17 29 7b vextractps \$0x7b,%xmm29,\(%rcx\)
[ ]*[a-f0-9]+: 62 23 fd 08 17 ac f0 23 01 00 00 7b vextractps \$0x7b,%xmm29,0x123\(%rax,%r14,8\)
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 7f 7b vextractps \$0x7b,%xmm29,0x1fc\(%rdx\)
[ ]*[a-f0-9]+: 62 63 fd 08 17 aa 00 02 00 00 7b vextractps \$0x7b,%xmm29,0x200\(%rdx\)
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 80 7b vextractps \$0x7b,%xmm29,-0x200\(%rdx\)
[ ]*[a-f0-9]+: 62 63 fd 08 17 aa fc fd ff ff 7b vextractps \$0x7b,%xmm29,-0x204\(%rdx\)
-[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 vpextrb \$0x0,%xmm0,%rax
+[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 vpextrb \$0x0,%xmm0,%eax
[ ]*[a-f0-9]+: 62 f3 fd 08 14 00 00 vpextrb \$0x0,%xmm0,\(%rax\)
-[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 vpextrw \$0x0,%xmm0,%rax
-[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 vpextrw \$0x0,%xmm0,%rax
+[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 vpextrw \$0x0,%xmm0,%eax
+[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 vpextrw \$0x0,%xmm0,%eax
[ ]*[a-f0-9]+: 62 f3 fd 08 15 00 00 vpextrw \$0x0,%xmm0,\(%rax\)
-[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 vpinsrb \$0x0,%rax,%xmm0,%xmm0
+[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 vpinsrb \$0x0,%eax,%xmm0,%xmm0
[ ]*[a-f0-9]+: 62 f3 fd 08 20 00 00 vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
-[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw \$0x0,%rax,%xmm0,%xmm0
+[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
[ ]*[a-f0-9]+: 62 f1 fd 08 c4 00 00 vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
[ ]*[a-f0-9]+: 62 02 fd 4f 21 f5 vpmovsxbd %xmm29,%zmm30\{%k7\}
[ ]*[a-f0-9]+: 62 02 fd cf 21 f5 vpmovsxbd %xmm29,%zmm30\{%k7\}\{z\}
@@ -91,9 +91,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 62 fd 4f 34 b2 00 08 00 00 vpmovzxwq 0x800\(%rdx\),%zmm30\{%k7\}
[ ]*[a-f0-9]+: 62 62 fd 4f 34 72 80 vpmovzxwq -0x800\(%rdx\),%zmm30\{%k7\}
[ ]*[a-f0-9]+: 62 62 fd 4f 34 b2 f0 f7 ff ff vpmovzxwq -0x810\(%rdx\),%zmm30\{%k7\}
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps \$0xab,%xmm29,%rax
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%rax
-[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%r8
+[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps \$0xab,%xmm29,%eax
+[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%eax
+[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%r8d
[ ]*[a-f0-9]+: 62 63 fd 08 17 29 7b vextractps \$0x7b,%xmm29,\(%rcx\)
[ ]*[a-f0-9]+: 62 23 fd 08 17 ac f0 34 12 00 00 7b vextractps \$0x7b,%xmm29,0x1234\(%rax,%r14,8\)
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 7f 7b vextractps \$0x7b,%xmm29,0x1fc\(%rdx\)
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -240,11 +240,8 @@ fetch_data (struct disassemble_info *inf
#define EvS { OP_E, v_swap_mode }
#define Ed { OP_E, d_mode }
#define Edq { OP_E, dq_mode }
-#define Edqw { OP_E, dqw_mode }
-#define Edqb { OP_E, dqb_mode }
#define Edb { OP_E, db_mode }
#define Edw { OP_E, dw_mode }
-#define Edqd { OP_E, dqd_mode }
#define Eq { OP_E, q_mode }
#define indirEv { OP_indirE, indir_v_mode }
#define indirEp { OP_indirE, f_mode }
@@ -509,8 +506,7 @@ enum
v_bndmk_mode,
/* operand size depends on REX.W / VEX.W. */
dq_mode,
- /* registers like dq_mode, memory like w_mode, displacements like
- v_mode without considering Intel64 ISA. */
+ /* Displacements like v_mode without considering Intel64 ISA. */
dqw_mode,
/* bounds operand */
bnd_mode,
@@ -527,14 +523,10 @@ enum
z_mode,
/* 16-byte operand */
o_mode,
- /* registers like dq_mode, memory like b_mode. */
- dqb_mode,
/* registers like d_mode, memory like b_mode. */
db_mode,
/* registers like d_mode, memory like w_mode. */
dw_mode,
- /* registers like dq_mode, memory like d_mode. */
- dqd_mode,
/* Operand size depends on the VEX.W bit, with VSIB dword indices. */
vex_vsib_d_w_dq_mode,
@@ -2182,8 +2174,8 @@ static const struct dis386 dis386_twobyt
{ "xaddS", { Evh1, Gv }, 0 },
{ PREFIX_TABLE (PREFIX_0FC2) },
{ MOD_TABLE (MOD_0FC3) },
- { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
- { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
+ { "pinsrw", { MX, Edw, Ib }, PREFIX_OPCODE },
+ { "pextrw", { Gd, MS, Ib }, PREFIX_OPCODE },
{ "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
{ REG_TABLE (REG_0FC7) },
/* c8 */
@@ -4687,10 +4679,10 @@ static const struct dis386 three_byte_ta
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
- { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
+ { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
+ { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
{ "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
- { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
+ { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
/* 18 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -4701,7 +4693,7 @@ static const struct dis386 three_byte_ta
{ Bad_Opcode },
{ Bad_Opcode },
/* 20 */
- { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
+ { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
{ "insertps", { XM, EXd, Ib }, PREFIX_DATA },
{ "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
{ Bad_Opcode },
@@ -6850,12 +6842,12 @@ static const struct dis386 vex_len_table
/* VEX_LEN_0FC4 */
{
- { "vpinsrw", { XM, Vex, Edqw, Ib }, PREFIX_DATA },
+ { "vpinsrw", { XM, Vex, Edw, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0FC5 */
{
- { "vpextrw", { Gdq, XS, Ib }, PREFIX_DATA },
+ { "vpextrw", { Gd, XS, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0FD6 */
@@ -7012,12 +7004,12 @@ static const struct dis386 vex_len_table
/* VEX_LEN_0F3A14 */
{
- { "vpextrb", { Edqb, XM, Ib }, PREFIX_DATA },
+ { "vpextrb", { Edb, XM, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0F3A15 */
{
- { "vpextrw", { Edqw, XM, Ib }, PREFIX_DATA },
+ { "vpextrw", { Edw, XM, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0F3A16 */
@@ -7027,7 +7019,7 @@ static const struct dis386 vex_len_table
/* VEX_LEN_0F3A17 */
{
- { "vextractps", { Edqd, XM, Ib }, PREFIX_DATA },
+ { "vextractps", { Ed, XM, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0F3A18 */
@@ -7044,7 +7036,7 @@ static const struct dis386 vex_len_table
/* VEX_LEN_0F3A20 */
{
- { "vpinsrb", { XM, Vex, Edqb, Ib }, PREFIX_DATA },
+ { "vpinsrb", { XM, Vex, Edb, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0F3A21 */
@@ -10957,13 +10949,11 @@ intel_operand_size (int bytemode, int si
{
case b_mode:
case b_swap_mode:
- case dqb_mode:
case db_mode:
oappend ("BYTE PTR ");
break;
case w_mode:
case dw_mode:
- case dqw_mode:
oappend ("WORD PTR ");
break;
case indir_v_mode:
@@ -11020,7 +11010,6 @@ intel_operand_size (int bytemode, int si
break;
case d_mode:
case d_swap_mode:
- case dqd_mode:
oappend ("DWORD PTR ");
break;
case q_mode:
@@ -11263,9 +11252,6 @@ print_register (unsigned int reg, unsign
case v_mode:
case v_swap_mode:
case dq_mode:
- case dqb_mode:
- case dqd_mode:
- case dqw_mode:
USED_REX (REX_W);
if (rex & REX_W)
names = names64;
@@ -11340,12 +11326,10 @@ OP_E_memory (int bytemode, int sizeflag)
}
switch (bytemode)
{
- case dqw_mode:
case dw_mode:
case w_mode:
shift = 1;
break;
- case dqb_mode:
case db_mode:
case b_mode:
shift = 0;
@@ -11353,7 +11337,6 @@ OP_E_memory (int bytemode, int sizeflag)
case dq_mode:
if (address_mode != mode_64bit)
{
- case dqd_mode:
case d_mode:
case d_swap_mode:
shift = 2;
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 00/12] x86: disassembler fixes and some consolidation
2021-07-21 10:07 [PATCH 00/12] x86: disassembler fixes and some consolidation Jan Beulich
` (11 preceding siblings ...)
2021-07-21 10:23 ` [PATCH 12/12] x86: drop dq{b,d}_mode Jan Beulich
@ 2021-07-21 12:56 ` H.J. Lu
12 siblings, 0 replies; 16+ messages in thread
From: H.J. Lu @ 2021-07-21 12:56 UTC (permalink / raw)
To: Jan Beulich; +Cc: Binutils
On Wed, Jul 21, 2021 at 3:07 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> This has started by me noticing that OP_G() handles "bytemode"
> values it never gets passed. But here you go - I've found a
> couple of bugs as I was going, and extended / better ways of
> cleaning up some code. But the duplication of register printing
> was something that has been puzzling me for a while, not the
> least because with about every other ISA extension two places
> have been getting touched when just one should have done.
>
> 01: drop OP_Mask()
> 02: correct VCVT{,U}SI2SD rounding mode handling
> 03: generalize OP_G()'s EVEX.R' handling
> 04: properly bounds-check %bnd<N> in OP_G()
> 05: fold duplicate register printing code
> 06: fold duplicate code in MOVSXD_Fixup()
> 07: correct EVEX.V' handling outside of 64-bit mode
> 08: drop vex_mode and vex_scalar_mode
> 09: fold duplicate vector register printing code
> 10: drop xmm_m{b,w,d,q}_mode
> 11: drop vex_scalar_w_dq_mode
> 12: drop dq{b,d}_mode
>
> Jan
>
OK for all.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 02/12] x86: correct VCVT{,U}SI2SD rounding mode handling
2021-07-21 10:19 ` [PATCH 02/12] x86: correct VCVT{,U}SI2SD rounding mode handling Jan Beulich
@ 2021-07-22 11:18 ` Jan Beulich
2021-07-22 11:31 ` H.J. Lu
0 siblings, 1 reply; 16+ messages in thread
From: Jan Beulich @ 2021-07-22 11:18 UTC (permalink / raw)
To: H.J. Lu; +Cc: Binutils
On 21.07.2021 12:19, Jan Beulich via Binutils wrote:
> With EVEX.W clear the instruction doesn't ignore the rounding mode, but
> (like for other insns without rounding semantics) EVEX.b set causes #UD.
> Hence the handling of EVEX.W needs to be done when processing
> evex_rounding_64_mode, not at the decode stages.
>
> Derive a new 64-bit testcase from the 32-bit one to cover the different
> EVEX.W treatment in both cases.
I've committed this and the other parts of this series, but I wonder ...
> ---
> This demonstrates a broader problem: Instructions not permitting
> rounding control at all (which #UD if such was specified in the
> encoding) get displayed without any hint to the badness, merely by there
> not being any respective operand at all. While OP_E_memory() handles
> EVEX.b (broadcast) wrongly being set (in an unhelpful way, in that not
> all of the opcode bytes get consumed), there's nowhere that EVEX.b
> (rounding) would be checked except for the three EXxEVexR, EXxEVexR64,
> and EXxEVexS ones.
... whether you have an opinion here. We could follow the model of
marking decoded bits used, but I'd like to avoid calling BadOp() from
the top level handler (I'd really like to get many of its uses dropped,
as it screws up disassembly of subsequent insns). Hence my preference
would be to express this as a pseudo-operand, e.g. {rn-bad} (to
parallel {rn-sae} and thus making visible what the two L'L bits are
set to in the encoding).
Jan
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 02/12] x86: correct VCVT{,U}SI2SD rounding mode handling
2021-07-22 11:18 ` Jan Beulich
@ 2021-07-22 11:31 ` H.J. Lu
0 siblings, 0 replies; 16+ messages in thread
From: H.J. Lu @ 2021-07-22 11:31 UTC (permalink / raw)
To: Jan Beulich; +Cc: Binutils
On Thu, Jul 22, 2021 at 4:18 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 21.07.2021 12:19, Jan Beulich via Binutils wrote:
> > With EVEX.W clear the instruction doesn't ignore the rounding mode, but
> > (like for other insns without rounding semantics) EVEX.b set causes #UD.
> > Hence the handling of EVEX.W needs to be done when processing
> > evex_rounding_64_mode, not at the decode stages.
> >
> > Derive a new 64-bit testcase from the 32-bit one to cover the different
> > EVEX.W treatment in both cases.
>
> I've committed this and the other parts of this series, but I wonder ...
>
> > ---
> > This demonstrates a broader problem: Instructions not permitting
> > rounding control at all (which #UD if such was specified in the
> > encoding) get displayed without any hint to the badness, merely by there
> > not being any respective operand at all. While OP_E_memory() handles
> > EVEX.b (broadcast) wrongly being set (in an unhelpful way, in that not
> > all of the opcode bytes get consumed), there's nowhere that EVEX.b
> > (rounding) would be checked except for the three EXxEVexR, EXxEVexR64,
> > and EXxEVexS ones.
>
> ... whether you have an opinion here. We could follow the model of
> marking decoded bits used, but I'd like to avoid calling BadOp() from
> the top level handler (I'd really like to get many of its uses dropped,
> as it screws up disassembly of subsequent insns). Hence my preference
> would be to express this as a pseudo-operand, e.g. {rn-bad} (to
> parallel {rn-sae} and thus making visible what the two L'L bits are
> set to in the encoding).
{rn-bad} sounds good to me.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2021-07-22 11:32 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-21 10:07 [PATCH 00/12] x86: disassembler fixes and some consolidation Jan Beulich
2021-07-21 10:18 ` [PATCH 01/12] x86: drop OP_Mask() Jan Beulich
2021-07-21 10:19 ` [PATCH 02/12] x86: correct VCVT{,U}SI2SD rounding mode handling Jan Beulich
2021-07-22 11:18 ` Jan Beulich
2021-07-22 11:31 ` H.J. Lu
2021-07-21 10:19 ` [PATCH 03/12] x86-64: generalize OP_G()'s EVEX.R' handling Jan Beulich
2021-07-21 10:19 ` [PATCH 04/12] x86-64: properly bounds-check %bnd<N> in OP_G() Jan Beulich
2021-07-21 10:20 ` [PATCH 05/12] x86: fold duplicate register printing code Jan Beulich
2021-07-21 10:20 ` [PATCH 06/12] x86: fold duplicate code in MOVSXD_Fixup() Jan Beulich
2021-07-21 10:21 ` [PATCH 07/12] x86: correct EVEX.V' handling outside of 64-bit mode Jan Beulich
2021-07-21 10:22 ` [PATCH 08/12] x86: drop vex_mode and vex_scalar_mode Jan Beulich
2021-07-21 10:22 ` [PATCH 09/12] x86: fold duplicate vector register printing code Jan Beulich
2021-07-21 10:22 ` [PATCH 10/12] x86: drop xmm_m{b,w,d,q}_mode Jan Beulich
2021-07-21 10:23 ` [PATCH 11/12] x86: drop vex_scalar_w_dq_mode Jan Beulich
2021-07-21 10:23 ` [PATCH 12/12] x86: drop dq{b,d}_mode Jan Beulich
2021-07-21 12:56 ` [PATCH 00/12] x86: disassembler fixes and some consolidation H.J. Lu
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