From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 45041385740F for ; Sat, 9 Jul 2022 08:53:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 45041385740F Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 9416B300089; Sat, 9 Jul 2022 08:53:36 +0000 (UTC) From: Tsukasa OI To: Tsukasa OI Cc: binutils@sourceware.org Subject: [REVIEW ONLY 1/1] UNRATIFIED RISC-V: Add 'Smrnmi' extension Date: Sat, 9 Jul 2022 17:53:24 +0900 Message-Id: <46197b6754f27f716f798cb1b2987c7a13422b5b.1657356767.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 09 Jul 2022 08:53:41 -0000 This commit adds `mnret' instruction and RNMI-related CSRs from Smrnmi extension. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add new instruction class handling. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add new CSR class. (riscv_csr_address): Add new CSR class handling. * testsuite/gas/riscv/csr.s: Add new CSR test. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/smrnmi.s: New test for mnret instruction. * testsuite/gas/riscv/smrnmi.d: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_MNRET, MASK_MNRET, CSR_MNSCRATCH, CSR_MNEPC, CSR_MNCAUSE, CSR_MNSTATUS): New. * opcode/riscv.h (enum riscv_insn_class): Add new instruction class. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add 'mnret' instruction. --- bfd/elfxx-riscv.c | 5 +++++ gas/config/tc-riscv.c | 4 ++++ gas/testsuite/gas/riscv/csr-dw-regnums.d | 4 ++++ gas/testsuite/gas/riscv/csr-dw-regnums.s | 5 +++++ gas/testsuite/gas/riscv/csr-version-1p10.d | 8 ++++++++ gas/testsuite/gas/riscv/csr-version-1p10.l | 8 ++++++++ gas/testsuite/gas/riscv/csr-version-1p11.d | 8 ++++++++ gas/testsuite/gas/riscv/csr-version-1p11.l | 8 ++++++++ gas/testsuite/gas/riscv/csr-version-1p12.d | 8 ++++++++ gas/testsuite/gas/riscv/csr-version-1p12.l | 8 ++++++++ gas/testsuite/gas/riscv/csr-version-1p9p1.d | 8 ++++++++ gas/testsuite/gas/riscv/csr-version-1p9p1.l | 8 ++++++++ gas/testsuite/gas/riscv/csr.s | 6 ++++++ gas/testsuite/gas/riscv/smrnmi.d | 10 ++++++++++ gas/testsuite/gas/riscv/smrnmi.s | 2 ++ include/opcode/riscv-opc.h | 14 ++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 3 +++ 18 files changed, 118 insertions(+) create mode 100644 gas/testsuite/gas/riscv/smrnmi.d create mode 100644 gas/testsuite/gas/riscv/smrnmi.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 0b2021f5cc7..ac4897ed364 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1233,6 +1233,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = static struct riscv_supported_ext riscv_supported_std_s_ext[] = { + {"smrnmi", ISA_SPEC_CLASS_DRAFT, 0, 4, 0 }, {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2398,6 +2399,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, || riscv_subset_supports (rps, "zve64d") || riscv_subset_supports (rps, "zve64f") || riscv_subset_supports (rps, "zve32f")); + case INSN_CLASS_SMRNMI: + return riscv_subset_supports (rps, "smrnmi"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2523,6 +2526,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("v' or `zve64x' or `zve32x"); case INSN_CLASS_ZVEF: return _("v' or `zve64d' or `zve64f' or `zve32f"); + case INSN_CLASS_SMRNMI: + return "smrnmi"; case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index a0e8456a0d1..9020132fcb8 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -68,6 +68,7 @@ enum riscv_csr_class CSR_CLASS_DEBUG, /* debug CSR */ CSR_CLASS_H, /* hypervisor */ CSR_CLASS_H_32, /* hypervisor, rv32 only */ + CSR_CLASS_SMRNMI, /* Smrnmi only */ CSR_CLASS_SMSTATEEN, /* Smstateen only */ CSR_CLASS_SMSTATEEN_AND_H, /* Smstateen only (with H) */ CSR_CLASS_SMSTATEEN_32, /* Smstateen RV32 only */ @@ -937,6 +938,9 @@ riscv_csr_address (const char *csr_name, case CSR_CLASS_V: extension = "v"; break; + case CSR_CLASS_SMRNMI: + extension = "smrnmi"; + break; case CSR_CLASS_SMSTATEEN: case CSR_CLASS_SMSTATEEN_AND_H: case CSR_CLASS_SMSTATEEN_32: diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d index b4b3806a085..a9a81130064 100644 --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d @@ -313,6 +313,10 @@ Contents of the .* section: DW_CFA_offset_extended_sf: r4675 \(vstval\) at cfa\+2316 DW_CFA_offset_extended_sf: r4676 \(vsip\) at cfa\+2320 DW_CFA_offset_extended_sf: r4736 \(vsatp\) at cfa\+2560 + DW_CFA_offset_extended_sf: r5952 \(mnscratch\) at cfa\+7424 + DW_CFA_offset_extended_sf: r5953 \(mnepc\) at cfa\+7428 + DW_CFA_offset_extended_sf: r5954 \(mncause\) at cfa\+7432 + DW_CFA_offset_extended_sf: r5956 \(mnstatus\) at cfa\+7440 DW_CFA_offset_extended_sf: r4876 \(mstateen0\) at cfa\+3120 DW_CFA_offset_extended_sf: r4877 \(mstateen1\) at cfa\+3124 DW_CFA_offset_extended_sf: r4878 \(mstateen2\) at cfa\+3128 diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s index 6cfa415ebc2..d46164007b9 100644 --- a/gas/testsuite/gas/riscv/csr-dw-regnums.s +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s @@ -307,6 +307,11 @@ _start: .cfi_offset vstval, 2316 .cfi_offset vsip, 2320 .cfi_offset vsatp, 2560 + # Smrnmi extension + .cfi_offset mnscratch, 7424 + .cfi_offset mnepc, 7428 + .cfi_offset mncause, 7432 + .cfi_offset mnstatus, 7440 # Smstateen extension .cfi_offset mstateen0, 3120 .cfi_offset mstateen1, 3124 diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d index bd8b10302e3..e0393c532a7 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.d +++ b/gas/testsuite/gas/riscv/csr-version-1p10.d @@ -601,6 +601,14 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1 [ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp [ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1 +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l index b778453b556..6f7c6ea1f87 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.l +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l @@ -411,6 +411,14 @@ .*Warning: invalid CSR `vsip', needs `h' extension .*Warning: invalid CSR `vsatp', needs `h' extension .*Warning: invalid CSR `vsatp', needs `h' extension +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension .*Warning: invalid CSR `mstateen0', needs `smstateen' extension .*Warning: invalid CSR `mstateen0', needs `smstateen' extension .*Warning: invalid CSR `mstateen1', needs `smstateen' extension diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d index 5d6333884f1..09d23bb7d77 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.d +++ b/gas/testsuite/gas/riscv/csr-version-1p11.d @@ -601,6 +601,14 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1 [ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp [ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1 +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l index 78bae817470..b0671ec3fc5 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.l +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l @@ -409,6 +409,14 @@ .*Warning: invalid CSR `vsip', needs `h' extension .*Warning: invalid CSR `vsatp', needs `h' extension .*Warning: invalid CSR `vsatp', needs `h' extension +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension .*Warning: invalid CSR `mstateen0', needs `smstateen' extension .*Warning: invalid CSR `mstateen0', needs `smstateen' extension .*Warning: invalid CSR `mstateen1', needs `smstateen' extension diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d index 728e647c552..ed121f9569b 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.d +++ b/gas/testsuite/gas/riscv/csr-version-1p12.d @@ -601,6 +601,14 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1 [ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp [ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1 +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l index cb026bb55e0..7fe7ab962a8 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.l +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l @@ -271,6 +271,14 @@ .*Warning: invalid CSR `vsip', needs `h' extension .*Warning: invalid CSR `vsatp', needs `h' extension .*Warning: invalid CSR `vsatp', needs `h' extension +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension .*Warning: invalid CSR `mstateen0', needs `smstateen' extension .*Warning: invalid CSR `mstateen0', needs `smstateen' extension .*Warning: invalid CSR `mstateen1', needs `smstateen' extension diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d index a34b99f4632..e5ac11addf3 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d @@ -601,6 +601,14 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1 [ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp [ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1 +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l index 4fac40fb589..de965606a2b 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l @@ -461,6 +461,14 @@ .*Warning: invalid CSR `vsip', needs `h' extension .*Warning: invalid CSR `vsatp', needs `h' extension .*Warning: invalid CSR `vsatp', needs `h' extension +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Warning: invalid CSR `mncause', needs `smrnmi' extension +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension .*Warning: invalid CSR `mstateen0', needs `smstateen' extension .*Warning: invalid CSR `mstateen0', needs `smstateen' extension .*Warning: invalid CSR `mstateen1', needs `smstateen' extension diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s index 128aeb83a04..c80716d511e 100644 --- a/gas/testsuite/gas/riscv/csr.s +++ b/gas/testsuite/gas/riscv/csr.s @@ -337,6 +337,12 @@ csr vsip csr vsatp + # Smrnmi extension + csr mnscratch + csr mnepc + csr mncause + csr mnstatus + # Smstateen extension csr mstateen0 csr mstateen1 diff --git a/gas/testsuite/gas/riscv/smrnmi.d b/gas/testsuite/gas/riscv/smrnmi.d new file mode 100644 index 00000000000..f2be1e2e34d --- /dev/null +++ b/gas/testsuite/gas/riscv/smrnmi.d @@ -0,0 +1,10 @@ +#as: -march=rv64i_smrnmi +#source: smrnmi.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+70200073[ ]+mnret diff --git a/gas/testsuite/gas/riscv/smrnmi.s b/gas/testsuite/gas/riscv/smrnmi.s new file mode 100644 index 00000000000..f2008bd8704 --- /dev/null +++ b/gas/testsuite/gas/riscv/smrnmi.s @@ -0,0 +1,2 @@ +target: + mnret diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 88b8d7ff595..49fa236bd64 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2055,6 +2055,9 @@ #define MASK_VDOTUVV 0xfc00707f #define MATCH_VFDOTVV 0xe4001057 #define MASK_VFDOTVV 0xfc00707f +/* Smrnmi instruction. */ +#define MATCH_MNRET 0x70200073 +#define MASK_MNRET 0xffffffff /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -2432,6 +2435,11 @@ #define CSR_UIP 0x44 #define CSR_SEDELEG 0x102 #define CSR_SIDELEG 0x103 +/* Smrnmi extension */ +#define CSR_MNSCRATCH 0x740 +#define CSR_MNEPC 0x741 +#define CSR_MNCAUSE 0x742 +#define CSR_MNSTATUS 0x744 /* Smstateen extension */ #define CSR_MSTATEEN0 0x30c #define CSR_MSTATEEN1 0x30d @@ -2823,6 +2831,7 @@ DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET) DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA) DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL) DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR) @@ -3154,6 +3163,11 @@ DECLARE_CSR(vscause, CSR_VSCAUSE, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_C DECLARE_CSR(vstval, CSR_VSTVAL, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(vsip, CSR_VSIP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(vsatp, CSR_VSATP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +/* Smrnmi extension */ +DECLARE_CSR(mnscratch, CSR_MNSCRATCH, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mnepc, CSR_MNEPC, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mncause, CSR_MNCAUSE, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(mnstatus, CSR_MNSTATUS, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) /* Smstateen extension */ DECLARE_CSR(mstateen0, CSR_MSTATEEN0, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mstateen1, CSR_MSTATEEN1, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index b115e338a05..5814565acf1 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -392,6 +392,7 @@ enum riscv_insn_class INSN_CLASS_ZKND_OR_ZKNE, INSN_CLASS_V, INSN_CLASS_ZVEF, + INSN_CLASS_SMRNMI, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 2f9945aa930..942b851fa79 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1797,6 +1797,9 @@ const struct riscv_opcode riscv_opcodes[] = {"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_opcode, 0}, {"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_opcode, 0}, +/* Smrnmi instructions. */ +{"mnret", 0, INSN_CLASS_SMRNMI, "", MATCH_MNRET, MASK_MNRET, match_opcode, 0 }, + /* Svinval instructions. */ {"sinval.vma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 }, {"sfence.w.inval", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 }, -- 2.34.1