* [m68k] RAMBAR confusion
@ 2007-04-13 13:31 Nathan Sidwell
2007-04-20 14:02 ` Nick Clifton
2007-04-23 6:50 ` Ben Elliston
0 siblings, 2 replies; 4+ messages in thread
From: Nathan Sidwell @ 2007-04-13 13:31 UTC (permalink / raw)
To: binutils; +Cc: bje
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The ColdFire chips can have RAMBAR0 and/or RAMBAR1 control registers. these are
numbered c04 and c05.
When only one is implemented, it is referred to as 'RAMBAR' in the ColdFire
documentation. Unfortunately, some ColdFire CPUs call 0xc04 RAMBAR and others
call 0xc05 RAMBAR :(
This patch fixes things up so that
1) We always have a 'RAMBAR' register, this maps onto 0xc04 or 0xc05 as
appropriate for the particular CPU. Thus matching the documentation.
2) We always disassemble as RAMBAR0 and RAMBAR1, to be unambiguous.
3) Fixes some CPUs where we had the wrong settings.
built and tested on m68k-elf, ok?
nathan
--
Nathan Sidwell :: http://www.codesourcery.com :: CodeSourcery
nathan@codesourcery.com :: http://www.planetfall.pwp.blueyonder.co.uk
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2007-04-13 Nathan Sidwell <nathan@codesourcery.com>
gas/
* config/m68k-parse.h (RAMBAR_ALT): New.
* config/tc-m68k.c (mcf5206_ctrl, mcf5307_ctrl): New.
(mcf_ctrl, mcf5208_ctrl, mcf5210a_ctrl, mcf5213_ctrl, mcf52235_ctrl,
mcf5225_ctrl, mcf5235_ctrl, mcf5271_ctrl, mcf5275_ctrl,
mcf5282_ctrl, mcf5329_ctrl, mcf5373_ctrl, mcfv4e_ctrl,
mcf5475_ctrl, mcf5485_ctrl): Add RAMBAR synonym for
RAMBAR1.
(mcf5272_ctrl): Add RAMBAR0, replace add RAMBAR with RAMBAR_ALT.
(m68k_cpus): Adjust 5206, 5206e & 5307 entries.
(m68k_ip) <Case J>: Detect when RAMBAR_ALT should be used. Add it
to control register mapping.
gas/testsuite/
* gas/m68k/ctrl-1.d, gas/m68k/ctrl-1.s: New.
* gas/m68k/ctrl-2.d, gas/m68k/ctrl-2.s: New.
* gas/m68k/all.exp: Add them.
opcodes/
* m68k-dis.c (print_insn_arg): Show c04 as rambar0 and c05 as
rambar1.
Index: gas/config/m68k-parse.h
===================================================================
RCS file: /cvs/src/src/gas/config/m68k-parse.h,v
retrieving revision 1.11
diff -c -3 -p -r1.11 m68k-parse.h
*** gas/config/m68k-parse.h 15 Feb 2007 18:37:08 -0000 1.11
--- gas/config/m68k-parse.h 13 Apr 2007 11:11:56 -0000
*************** enum m68k_register
*** 113,118 ****
--- 113,120 ----
BUSCR, /* 68060 added these. */
PCR,
ROMBAR, /* mcf5200 added these. */
+ RAMBAR_ALT, /* Some CF chips have RAMBAR using
+ RAMBAR0's number */
RAMBAR0,
RAMBAR1,
MMUBAR, /* mcfv4e added these. */
Index: gas/config/tc-m68k.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-m68k.c,v
retrieving revision 1.86
diff -c -3 -p -r1.86 tc-m68k.c
*** gas/config/tc-m68k.c 4 Apr 2007 22:10:34 -0000 1.86
--- gas/config/tc-m68k.c 13 Apr 2007 11:12:00 -0000
*************** static const enum m68k_register m68060_c
*** 173,211 ****
};
static const enum m68k_register mcf_ctrl[] = {
CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
! RAMBAR0, RAMBAR1, MBAR,
0
};
static const enum m68k_register mcf5208_ctrl[] = {
! CACR, ACR0, ACR1, VBR, RAMBAR1,
0
};
static const enum m68k_register mcf5210a_ctrl[] = {
! VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
0
};
static const enum m68k_register mcf5213_ctrl[] = {
! VBR, RAMBAR, FLASHBAR,
0
};
static const enum m68k_register mcf5216_ctrl[] = {
! VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
0
};
static const enum m68k_register mcf52235_ctrl[] = {
! VBR, FLASHBAR, RAMBAR,
0
};
static const enum m68k_register mcf5225_ctrl[] = {
! VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR,
0
};
static const enum m68k_register mcf5235_ctrl[] = {
! VBR, CACR, ACR0, ACR1, RAMBAR,
0
};
static const enum m68k_register mcf5249_ctrl[] = {
! VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR, MBAR2,
0
};
static const enum m68k_register mcf5250_ctrl[] = {
--- 173,215 ----
};
static const enum m68k_register mcf_ctrl[] = {
CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
! RAMBAR0, RAMBAR1, RAMBAR, MBAR,
! 0
! };
! static const enum m68k_register mcf5206_ctrl[] = {
! CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
0
};
static const enum m68k_register mcf5208_ctrl[] = {
! CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
0
};
static const enum m68k_register mcf5210a_ctrl[] = {
! VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
0
};
static const enum m68k_register mcf5213_ctrl[] = {
! VBR, RAMBAR, RAMBAR1, FLASHBAR,
0
};
static const enum m68k_register mcf5216_ctrl[] = {
! VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
0
};
static const enum m68k_register mcf52235_ctrl[] = {
! VBR, FLASHBAR, RAMBAR, RAMBAR1,
0
};
static const enum m68k_register mcf5225_ctrl[] = {
! VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
0
};
static const enum m68k_register mcf5235_ctrl[] = {
! VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
0
};
static const enum m68k_register mcf5249_ctrl[] = {
! VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
0
};
static const enum m68k_register mcf5250_ctrl[] = {
*************** static const enum m68k_register mcf5250_
*** 213,239 ****
0
};
static const enum m68k_register mcf5271_ctrl[] = {
! VBR, CACR, ACR0, ACR1, RAMBAR,
0
};
static const enum m68k_register mcf5272_ctrl[] = {
! VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
0
};
static const enum m68k_register mcf5275_ctrl[] = {
! VBR, CACR, ACR0, ACR1, RAMBAR,
0
};
static const enum m68k_register mcf5282_ctrl[] = {
! VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
0
};
static const enum m68k_register mcf5329_ctrl[] = {
! VBR, CACR, ACR0, ACR1, RAMBAR,
0
};
static const enum m68k_register mcf5373_ctrl[] = {
! VBR, CACR, ACR0, ACR1, RAMBAR,
0
};
static const enum m68k_register mcfv4e_ctrl[] = {
--- 217,247 ----
0
};
static const enum m68k_register mcf5271_ctrl[] = {
! VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
0
};
static const enum m68k_register mcf5272_ctrl[] = {
! VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
0
};
static const enum m68k_register mcf5275_ctrl[] = {
! VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
0
};
static const enum m68k_register mcf5282_ctrl[] = {
! VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
! 0
! };
! static const enum m68k_register mcf5307_ctrl[] = {
! CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
0
};
static const enum m68k_register mcf5329_ctrl[] = {
! VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
0
};
static const enum m68k_register mcf5373_ctrl[] = {
! VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
0
};
static const enum m68k_register mcfv4e_ctrl[] = {
*************** static const enum m68k_register mcfv4e_c
*** 249,255 ****
TC /* ASID */, BUSCR /* MMUBAR */,
ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
! ROMBAR /* ROMBAR0 */,
0
};
static const enum m68k_register mcf5475_ctrl[] = {
--- 257,263 ----
TC /* ASID */, BUSCR /* MMUBAR */,
ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
! ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
0
};
static const enum m68k_register mcf5475_ctrl[] = {
*************** static const enum m68k_register mcf5475_
*** 258,264 ****
/* Legacy names */
TC /* ASID */, BUSCR /* MMUBAR */,
ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
! MBAR1 /* MBAR */, ROMBAR /* ROMBAR0 */,
0
};
static const enum m68k_register mcf5485_ctrl[] = {
--- 266,272 ----
/* Legacy names */
TC /* ASID */, BUSCR /* MMUBAR */,
ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
! MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
0
};
static const enum m68k_register mcf5485_ctrl[] = {
*************** static const enum m68k_register mcf5485_
*** 267,273 ****
/* Legacy names */
TC /* ASID */, BUSCR /* MMUBAR */,
ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
! MBAR1 /* MBAR */, ROMBAR /* ROMBAR0 */,
0
};
static const enum m68k_register fido_ctrl[] = {
--- 275,281 ----
/* Legacy names */
TC /* ASID */, BUSCR /* MMUBAR */,
ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
! MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
0
};
static const enum m68k_register fido_ctrl[] = {
*************** static const struct m68k_cpu m68k_cpus[]
*** 530,538 ****
{mcfisa_a, mcf_ctrl, "5200", 0},
{mcfisa_a, mcf_ctrl, "5202", 1},
{mcfisa_a, mcf_ctrl, "5204", 1},
! {mcfisa_a, mcf_ctrl, "5206", 1},
! {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5206e", 0},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
--- 538,546 ----
{mcfisa_a, mcf_ctrl, "5200", 0},
{mcfisa_a, mcf_ctrl, "5202", 1},
{mcfisa_a, mcf_ctrl, "5204", 1},
! {mcfisa_a, mcf5206_ctrl, "5206", 1},
! {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
*************** static const struct m68k_cpu m68k_cpus[]
*** 578,584 ****
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
! {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5307", 0},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
--- 586,592 ----
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
! {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
*************** m68k_ip (char *instring)
*** 1743,1750 ****
const enum m68k_register *rp;
for (rp = control_regs; *rp; rp++)
! if (*rp == opP->reg)
! break;
if (*rp == 0)
losing++;
}
--- 1751,1768 ----
const enum m68k_register *rp;
for (rp = control_regs; *rp; rp++)
! {
! if (*rp == opP->reg)
! break;
! /* In most CPUs RAMBAR refers to control reg
! c05 (RAMBAR1), but a few CPUs have it
! refer to c04 (RAMBAR0). */
! else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
! {
! opP->reg = RAMBAR_ALT;
! break;
! }
! }
if (*rp == 0)
losing++;
}
*************** m68k_ip (char *instring)
*** 3075,3080 ****
--- 3093,3099 ----
break;
case FLASHBAR:
case RAMBAR0:
+ case RAMBAR_ALT:
tmpreg = 0xC04;
break;
case RAMBAR:
Index: gas/testsuite/gas/m68k/all.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/m68k/all.exp,v
retrieving revision 1.11
diff -c -3 -p -r1.11 all.exp
*** gas/testsuite/gas/m68k/all.exp 4 Jan 2007 17:14:50 -0000 1.11
--- gas/testsuite/gas/m68k/all.exp 13 Apr 2007 11:12:03 -0000
*************** if { [istarget m68*-*-*] || [istarget fi
*** 52,57 ****
--- 52,60 ----
run_dump_test arch-cpu-1
run_dump_test cpu32
+ run_dump_test ctrl-1
+ run_dump_test ctrl-2
+
set testname "68000 operands"
gas_run "operands.s" "-m68000" "2>err.out"
if ![string match "child process exited abnormally" $comp_output] then {
Index: opcodes/m68k-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/m68k-dis.c,v
retrieving revision 1.25
diff -c -3 -p -r1.25 m68k-dis.c
*** opcodes/m68k-dis.c 9 Apr 2007 17:09:56 -0000 1.25
--- opcodes/m68k-dis.c 13 Apr 2007 11:12:05 -0000
*************** print_insn_arg (const char *d,
*** 645,651 ****
{"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
{"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
{"%msp", 0x803}, {"%isp", 0x804},
! {"%flashbar", 0xc04}, {"%rambar", 0xc05}, /* mcf528x added these. */
/* Should we be calling this psr like we do in case 'Y'? */
{"%mmusr",0x805},
--- 645,653 ----
{"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
{"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
{"%msp", 0x803}, {"%isp", 0x804},
! /* reg c04 is sometimes called flashbar or rambar.
! rec c05 is also sometimes called rambar. */
! {"%rambar0", 0xc04}, {"%rambar1", 0xc05},
/* Should we be calling this psr like we do in case 'Y'? */
{"%mmusr",0x805},
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [m68k] RAMBAR confusion
2007-04-13 13:31 [m68k] RAMBAR confusion Nathan Sidwell
@ 2007-04-20 14:02 ` Nick Clifton
2007-04-23 6:50 ` Ben Elliston
1 sibling, 0 replies; 4+ messages in thread
From: Nick Clifton @ 2007-04-20 14:02 UTC (permalink / raw)
To: Nathan Sidwell; +Cc: binutils, bje
Hi Nathan,
> This patch fixes things up so that
> 1) We always have a 'RAMBAR' register, this maps onto 0xc04 or 0xc05 as
> appropriate for the particular CPU. Thus matching the documentation.
>
> 2) We always disassemble as RAMBAR0 and RAMBAR1, to be unambiguous.
>
> 3) Fixes some CPUs where we had the wrong settings.
>
> built and tested on m68k-elf, ok?
Approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [m68k] RAMBAR confusion
2007-04-13 13:31 [m68k] RAMBAR confusion Nathan Sidwell
2007-04-20 14:02 ` Nick Clifton
@ 2007-04-23 6:50 ` Ben Elliston
2007-04-23 7:00 ` Nathan Sidwell
1 sibling, 1 reply; 4+ messages in thread
From: Ben Elliston @ 2007-04-23 6:50 UTC (permalink / raw)
To: Nathan Sidwell; +Cc: binutils, bje
On Fri, 2007-04-13 at 12:36 +0100, Nathan Sidwell wrote:
> 2007-04-13 Nathan Sidwell <nathan@codesourcery.com>
OK (although I see Nick has already approved it; so sorry for taking so
long!)
Ben
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [m68k] RAMBAR confusion
2007-04-23 6:50 ` Ben Elliston
@ 2007-04-23 7:00 ` Nathan Sidwell
0 siblings, 0 replies; 4+ messages in thread
From: Nathan Sidwell @ 2007-04-23 7:00 UTC (permalink / raw)
To: Ben Elliston; +Cc: binutils, bje
Ben Elliston wrote:
> On Fri, 2007-04-13 at 12:36 +0100, Nathan Sidwell wrote:
>
>> 2007-04-13 Nathan Sidwell <nathan@codesourcery.com>
>
> OK (although I see Nick has already approved it; so sorry for taking so
> long!)
Thanks to both you and Nick. You'll see there's now an ISAC patch, which is the
last one in my queue right now.
nathan
--
Nathan Sidwell :: http://www.codesourcery.com :: CodeSourcery
nathan@codesourcery.com :: http://www.planetfall.pwp.blueyonder.co.uk
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2007-04-23 6:50 UTC | newest]
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2007-04-13 13:31 [m68k] RAMBAR confusion Nathan Sidwell
2007-04-20 14:02 ` Nick Clifton
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2007-04-23 7:00 ` Nathan Sidwell
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