From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH 1/1] RISC-V: Add testcase for DWARF register numbers
Date: Fri, 23 Sep 2022 08:41:45 +0000 [thread overview]
Message-ID: <46e470b377bd9c23c121687ea3c94fdc3da36c6a.1663922476.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1663922476.git.research_trasio@irq.a4lg.com>
Although it had csr-dw-regnums.d (for CSRs), it didn't have DWARF register
number test for GPRs/FPRs.
This commit adds dw-regnums.{s,d} to test such registers.
gas/ChangeLog:
* testsuite/gas/riscv/dw-regnums.s: New DWARF register number test
for GPRs/FPRs.
* testsuite/gas/riscv/dw-regnums.d: Likewise.
---
gas/testsuite/gas/riscv/dw-regnums.d | 149 ++++++++++++++++++++++++++
gas/testsuite/gas/riscv/dw-regnums.s | 151 +++++++++++++++++++++++++++
2 files changed, 300 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/dw-regnums.d
create mode 100644 gas/testsuite/gas/riscv/dw-regnums.s
diff --git a/gas/testsuite/gas/riscv/dw-regnums.d b/gas/testsuite/gas/riscv/dw-regnums.d
new file mode 100644
index 00000000000..f67c26f10fb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dw-regnums.d
@@ -0,0 +1,149 @@
+#as: -march=rv32if
+#objdump: --dwarf=frames
+
+
+.*: file format elf.*-.*riscv
+
+Contents of the .* section:
+
+
+00000000 [a-zA-Z0-9]+ [a-zA-Z0-9]+ CIE
+ Version: .*
+ Augmentation: .*
+ Code alignment factor: .*
+ Data alignment factor: .*
+ Return address column: .*
+ Augmentation data: .*
+#...
+[a-zA-Z0-9]+ [a-zA-Z0-9]+ [a-zA-Z0-9]+ FDE cie=00000000 pc=[a-zA-Z0-9]+\.\.[a-zA-Z0-9]+
+ DW_CFA_advance_loc: 4 to 0+0000020
+ DW_CFA_offset_extended_sf: r0 \(zero\) at cfa\+4
+ DW_CFA_offset_extended_sf: r1 \(ra\) at cfa\+8
+ DW_CFA_offset_extended_sf: r2 \(sp\) at cfa\+12
+ DW_CFA_offset_extended_sf: r3 \(gp\) at cfa\+16
+ DW_CFA_offset_extended_sf: r4 \(tp\) at cfa\+20
+ DW_CFA_offset_extended_sf: r5 \(t0\) at cfa\+24
+ DW_CFA_offset_extended_sf: r6 \(t1\) at cfa\+28
+ DW_CFA_offset_extended_sf: r7 \(t2\) at cfa\+32
+ DW_CFA_offset_extended_sf: r8 \(s0\) at cfa\+36
+ DW_CFA_offset_extended_sf: r9 \(s1\) at cfa\+40
+ DW_CFA_offset_extended_sf: r10 \(a0\) at cfa\+44
+ DW_CFA_offset_extended_sf: r11 \(a1\) at cfa\+48
+ DW_CFA_offset_extended_sf: r12 \(a2\) at cfa\+52
+ DW_CFA_offset_extended_sf: r13 \(a3\) at cfa\+56
+ DW_CFA_offset_extended_sf: r14 \(a4\) at cfa\+60
+ DW_CFA_offset_extended_sf: r15 \(a5\) at cfa\+64
+ DW_CFA_offset_extended_sf: r16 \(a6\) at cfa\+68
+ DW_CFA_offset_extended_sf: r17 \(a7\) at cfa\+72
+ DW_CFA_offset_extended_sf: r18 \(s2\) at cfa\+76
+ DW_CFA_offset_extended_sf: r19 \(s3\) at cfa\+80
+ DW_CFA_offset_extended_sf: r20 \(s4\) at cfa\+84
+ DW_CFA_offset_extended_sf: r21 \(s5\) at cfa\+88
+ DW_CFA_offset_extended_sf: r22 \(s6\) at cfa\+92
+ DW_CFA_offset_extended_sf: r23 \(s7\) at cfa\+96
+ DW_CFA_offset_extended_sf: r24 \(s8\) at cfa\+100
+ DW_CFA_offset_extended_sf: r25 \(s9\) at cfa\+104
+ DW_CFA_offset_extended_sf: r26 \(s10\) at cfa\+108
+ DW_CFA_offset_extended_sf: r27 \(s11\) at cfa\+112
+ DW_CFA_offset_extended_sf: r28 \(t3\) at cfa\+116
+ DW_CFA_offset_extended_sf: r29 \(t4\) at cfa\+120
+ DW_CFA_offset_extended_sf: r30 \(t5\) at cfa\+124
+ DW_CFA_offset_extended_sf: r31 \(t6\) at cfa\+128
+ DW_CFA_offset_extended_sf: r8 \(s0\) at cfa\+36
+ DW_CFA_offset_extended_sf: r0 \(zero\) at cfa\+4
+ DW_CFA_offset_extended_sf: r1 \(ra\) at cfa\+8
+ DW_CFA_offset_extended_sf: r2 \(sp\) at cfa\+12
+ DW_CFA_offset_extended_sf: r3 \(gp\) at cfa\+16
+ DW_CFA_offset_extended_sf: r4 \(tp\) at cfa\+20
+ DW_CFA_offset_extended_sf: r5 \(t0\) at cfa\+24
+ DW_CFA_offset_extended_sf: r6 \(t1\) at cfa\+28
+ DW_CFA_offset_extended_sf: r7 \(t2\) at cfa\+32
+ DW_CFA_offset_extended_sf: r8 \(s0\) at cfa\+36
+ DW_CFA_offset_extended_sf: r9 \(s1\) at cfa\+40
+ DW_CFA_offset_extended_sf: r10 \(a0\) at cfa\+44
+ DW_CFA_offset_extended_sf: r11 \(a1\) at cfa\+48
+ DW_CFA_offset_extended_sf: r12 \(a2\) at cfa\+52
+ DW_CFA_offset_extended_sf: r13 \(a3\) at cfa\+56
+ DW_CFA_offset_extended_sf: r14 \(a4\) at cfa\+60
+ DW_CFA_offset_extended_sf: r15 \(a5\) at cfa\+64
+ DW_CFA_offset_extended_sf: r16 \(a6\) at cfa\+68
+ DW_CFA_offset_extended_sf: r17 \(a7\) at cfa\+72
+ DW_CFA_offset_extended_sf: r18 \(s2\) at cfa\+76
+ DW_CFA_offset_extended_sf: r19 \(s3\) at cfa\+80
+ DW_CFA_offset_extended_sf: r20 \(s4\) at cfa\+84
+ DW_CFA_offset_extended_sf: r21 \(s5\) at cfa\+88
+ DW_CFA_offset_extended_sf: r22 \(s6\) at cfa\+92
+ DW_CFA_offset_extended_sf: r23 \(s7\) at cfa\+96
+ DW_CFA_offset_extended_sf: r24 \(s8\) at cfa\+100
+ DW_CFA_offset_extended_sf: r25 \(s9\) at cfa\+104
+ DW_CFA_offset_extended_sf: r26 \(s10\) at cfa\+108
+ DW_CFA_offset_extended_sf: r27 \(s11\) at cfa\+112
+ DW_CFA_offset_extended_sf: r28 \(t3\) at cfa\+116
+ DW_CFA_offset_extended_sf: r29 \(t4\) at cfa\+120
+ DW_CFA_offset_extended_sf: r30 \(t5\) at cfa\+124
+ DW_CFA_offset_extended_sf: r31 \(t6\) at cfa\+128
+ DW_CFA_offset_extended_sf: r32 \(ft0\) at cfa\+132
+ DW_CFA_offset_extended_sf: r33 \(ft1\) at cfa\+136
+ DW_CFA_offset_extended_sf: r34 \(ft2\) at cfa\+140
+ DW_CFA_offset_extended_sf: r35 \(ft3\) at cfa\+144
+ DW_CFA_offset_extended_sf: r36 \(ft4\) at cfa\+148
+ DW_CFA_offset_extended_sf: r37 \(ft5\) at cfa\+152
+ DW_CFA_offset_extended_sf: r38 \(ft6\) at cfa\+156
+ DW_CFA_offset_extended_sf: r39 \(ft7\) at cfa\+160
+ DW_CFA_offset_extended_sf: r40 \(fs0\) at cfa\+164
+ DW_CFA_offset_extended_sf: r41 \(fs1\) at cfa\+168
+ DW_CFA_offset_extended_sf: r42 \(fa0\) at cfa\+172
+ DW_CFA_offset_extended_sf: r43 \(fa1\) at cfa\+176
+ DW_CFA_offset_extended_sf: r44 \(fa2\) at cfa\+180
+ DW_CFA_offset_extended_sf: r45 \(fa3\) at cfa\+184
+ DW_CFA_offset_extended_sf: r46 \(fa4\) at cfa\+188
+ DW_CFA_offset_extended_sf: r47 \(fa5\) at cfa\+192
+ DW_CFA_offset_extended_sf: r48 \(fa6\) at cfa\+196
+ DW_CFA_offset_extended_sf: r49 \(fa7\) at cfa\+200
+ DW_CFA_offset_extended_sf: r50 \(fs2\) at cfa\+204
+ DW_CFA_offset_extended_sf: r51 \(fs3\) at cfa\+208
+ DW_CFA_offset_extended_sf: r52 \(fs4\) at cfa\+212
+ DW_CFA_offset_extended_sf: r53 \(fs5\) at cfa\+216
+ DW_CFA_offset_extended_sf: r54 \(fs6\) at cfa\+220
+ DW_CFA_offset_extended_sf: r55 \(fs7\) at cfa\+224
+ DW_CFA_offset_extended_sf: r56 \(fs8\) at cfa\+228
+ DW_CFA_offset_extended_sf: r57 \(fs9\) at cfa\+232
+ DW_CFA_offset_extended_sf: r58 \(fs10\) at cfa\+236
+ DW_CFA_offset_extended_sf: r59 \(fs11\) at cfa\+240
+ DW_CFA_offset_extended_sf: r60 \(ft8\) at cfa\+244
+ DW_CFA_offset_extended_sf: r61 \(ft9\) at cfa\+248
+ DW_CFA_offset_extended_sf: r62 \(ft10\) at cfa\+252
+ DW_CFA_offset_extended_sf: r63 \(ft11\) at cfa\+256
+ DW_CFA_offset_extended_sf: r32 \(ft0\) at cfa\+132
+ DW_CFA_offset_extended_sf: r33 \(ft1\) at cfa\+136
+ DW_CFA_offset_extended_sf: r34 \(ft2\) at cfa\+140
+ DW_CFA_offset_extended_sf: r35 \(ft3\) at cfa\+144
+ DW_CFA_offset_extended_sf: r36 \(ft4\) at cfa\+148
+ DW_CFA_offset_extended_sf: r37 \(ft5\) at cfa\+152
+ DW_CFA_offset_extended_sf: r38 \(ft6\) at cfa\+156
+ DW_CFA_offset_extended_sf: r39 \(ft7\) at cfa\+160
+ DW_CFA_offset_extended_sf: r40 \(fs0\) at cfa\+164
+ DW_CFA_offset_extended_sf: r41 \(fs1\) at cfa\+168
+ DW_CFA_offset_extended_sf: r42 \(fa0\) at cfa\+172
+ DW_CFA_offset_extended_sf: r43 \(fa1\) at cfa\+176
+ DW_CFA_offset_extended_sf: r44 \(fa2\) at cfa\+180
+ DW_CFA_offset_extended_sf: r45 \(fa3\) at cfa\+184
+ DW_CFA_offset_extended_sf: r46 \(fa4\) at cfa\+188
+ DW_CFA_offset_extended_sf: r47 \(fa5\) at cfa\+192
+ DW_CFA_offset_extended_sf: r48 \(fa6\) at cfa\+196
+ DW_CFA_offset_extended_sf: r49 \(fa7\) at cfa\+200
+ DW_CFA_offset_extended_sf: r50 \(fs2\) at cfa\+204
+ DW_CFA_offset_extended_sf: r51 \(fs3\) at cfa\+208
+ DW_CFA_offset_extended_sf: r52 \(fs4\) at cfa\+212
+ DW_CFA_offset_extended_sf: r53 \(fs5\) at cfa\+216
+ DW_CFA_offset_extended_sf: r54 \(fs6\) at cfa\+220
+ DW_CFA_offset_extended_sf: r55 \(fs7\) at cfa\+224
+ DW_CFA_offset_extended_sf: r56 \(fs8\) at cfa\+228
+ DW_CFA_offset_extended_sf: r57 \(fs9\) at cfa\+232
+ DW_CFA_offset_extended_sf: r58 \(fs10\) at cfa\+236
+ DW_CFA_offset_extended_sf: r59 \(fs11\) at cfa\+240
+ DW_CFA_offset_extended_sf: r60 \(ft8\) at cfa\+244
+ DW_CFA_offset_extended_sf: r61 \(ft9\) at cfa\+248
+ DW_CFA_offset_extended_sf: r62 \(ft10\) at cfa\+252
+ DW_CFA_offset_extended_sf: r63 \(ft11\) at cfa\+256
+#...
diff --git a/gas/testsuite/gas/riscv/dw-regnums.s b/gas/testsuite/gas/riscv/dw-regnums.s
new file mode 100644
index 00000000000..207fadfe668
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dw-regnums.s
@@ -0,0 +1,151 @@
+# Check that CFI directives can accept all of the register names (including
+# aliases). The results for this test also ensures that the DWARF
+# register numbers for the GPRs/FPRs registers shouldn't change.
+
+ .text
+ .global _start
+_start:
+ .cfi_startproc
+ nop
+
+ # GPRs (ABI)
+ .cfi_offset zero, 4
+ .cfi_offset ra, 8
+ .cfi_offset sp, 12
+ .cfi_offset gp, 16
+ .cfi_offset tp, 20
+ .cfi_offset t0, 24
+ .cfi_offset t1, 28
+ .cfi_offset t2, 32
+ .cfi_offset s0, 36
+ .cfi_offset s1, 40
+ .cfi_offset a0, 44
+ .cfi_offset a1, 48
+ .cfi_offset a2, 52
+ .cfi_offset a3, 56
+ .cfi_offset a4, 60
+ .cfi_offset a5, 64
+ .cfi_offset a6, 68
+ .cfi_offset a7, 72
+ .cfi_offset s2, 76
+ .cfi_offset s3, 80
+ .cfi_offset s4, 84
+ .cfi_offset s5, 88
+ .cfi_offset s6, 92
+ .cfi_offset s7, 96
+ .cfi_offset s8, 100
+ .cfi_offset s9, 104
+ .cfi_offset s10, 108
+ .cfi_offset s11, 112
+ .cfi_offset t3, 116
+ .cfi_offset t4, 120
+ .cfi_offset t5, 124
+ .cfi_offset t6, 128
+
+ # GPR (ABI alias)
+ .cfi_offset fp, 36
+
+ # GPRs (Numeric)
+ .cfi_offset x0, 4
+ .cfi_offset x1, 8
+ .cfi_offset x2, 12
+ .cfi_offset x3, 16
+ .cfi_offset x4, 20
+ .cfi_offset x5, 24
+ .cfi_offset x6, 28
+ .cfi_offset x7, 32
+ .cfi_offset x8, 36
+ .cfi_offset x9, 40
+ .cfi_offset x10, 44
+ .cfi_offset x11, 48
+ .cfi_offset x12, 52
+ .cfi_offset x13, 56
+ .cfi_offset x14, 60
+ .cfi_offset x15, 64
+ .cfi_offset x16, 68
+ .cfi_offset x17, 72
+ .cfi_offset x18, 76
+ .cfi_offset x19, 80
+ .cfi_offset x20, 84
+ .cfi_offset x21, 88
+ .cfi_offset x22, 92
+ .cfi_offset x23, 96
+ .cfi_offset x24, 100
+ .cfi_offset x25, 104
+ .cfi_offset x26, 108
+ .cfi_offset x27, 112
+ .cfi_offset x28, 116
+ .cfi_offset x29, 120
+ .cfi_offset x30, 124
+ .cfi_offset x31, 128
+
+ # FPRs (ABI)
+ .cfi_offset ft0, 132
+ .cfi_offset ft1, 136
+ .cfi_offset ft2, 140
+ .cfi_offset ft3, 144
+ .cfi_offset ft4, 148
+ .cfi_offset ft5, 152
+ .cfi_offset ft6, 156
+ .cfi_offset ft7, 160
+ .cfi_offset fs0, 164
+ .cfi_offset fs1, 168
+ .cfi_offset fa0, 172
+ .cfi_offset fa1, 176
+ .cfi_offset fa2, 180
+ .cfi_offset fa3, 184
+ .cfi_offset fa4, 188
+ .cfi_offset fa5, 192
+ .cfi_offset fa6, 196
+ .cfi_offset fa7, 200
+ .cfi_offset fs2, 204
+ .cfi_offset fs3, 208
+ .cfi_offset fs4, 212
+ .cfi_offset fs5, 216
+ .cfi_offset fs6, 220
+ .cfi_offset fs7, 224
+ .cfi_offset fs8, 228
+ .cfi_offset fs9, 232
+ .cfi_offset fs10, 236
+ .cfi_offset fs11, 240
+ .cfi_offset ft8, 244
+ .cfi_offset ft9, 248
+ .cfi_offset ft10, 252
+ .cfi_offset ft11, 256
+
+ # FPRs (Numeric)
+ .cfi_offset f0, 132
+ .cfi_offset f1, 136
+ .cfi_offset f2, 140
+ .cfi_offset f3, 144
+ .cfi_offset f4, 148
+ .cfi_offset f5, 152
+ .cfi_offset f6, 156
+ .cfi_offset f7, 160
+ .cfi_offset f8, 164
+ .cfi_offset f9, 168
+ .cfi_offset f10, 172
+ .cfi_offset f11, 176
+ .cfi_offset f12, 180
+ .cfi_offset f13, 184
+ .cfi_offset f14, 188
+ .cfi_offset f15, 192
+ .cfi_offset f16, 196
+ .cfi_offset f17, 200
+ .cfi_offset f18, 204
+ .cfi_offset f19, 208
+ .cfi_offset f20, 212
+ .cfi_offset f21, 216
+ .cfi_offset f22, 220
+ .cfi_offset f23, 224
+ .cfi_offset f24, 228
+ .cfi_offset f25, 232
+ .cfi_offset f26, 236
+ .cfi_offset f27, 240
+ .cfi_offset f28, 244
+ .cfi_offset f29, 248
+ .cfi_offset f30, 252
+ .cfi_offset f31, 256
+
+ nop
+ .cfi_endproc
--
2.34.1
next prev parent reply other threads:[~2022-09-23 8:42 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-23 8:41 [PATCH 0/1] RISC-V psABI: " Tsukasa OI
2022-09-23 8:41 ` Tsukasa OI [this message]
2022-10-08 4:29 ` [PATCH v2 0/1] RISC-V psABI: Add testcase for DWARF register numbers (supplemental) Tsukasa OI
2022-10-08 4:29 ` [PATCH v2 1/1] RISC-V: Test DWARF register numbers for "fp" Tsukasa OI
2022-10-14 1:33 ` [PATCH v2 0/1] RISC-V psABI: Add testcase for DWARF register numbers (supplemental) Nelson Chu
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