From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 0EDE33857B93 for ; Sun, 4 Sep 2022 07:07:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0EDE33857B93 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 4353C300089; Sun, 4 Sep 2022 07:07:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1662275220; bh=wAelVuVT/S26Wm2aheZPnqA5jtMu3CSvXvx64x59Lmw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=QRSPq/43L6YVoU+yA0DXCXLFWSZl4fOjUBJQMgU64t6IvynxDrqYXcGWMTFIvqN81 sHEtioqssNnUElJxcsVXT1SlJ9XFQPyJta2aKMZbxc90VnKjRVx8bC0yMjgKgnm1hb w8eIQNnWT+7+kXWENVtTnZk0fiu/coaMw/wlukIw= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v5 3/3] RISC-V: Validate Zdinx/Zqinx register pairs Date: Sun, 4 Sep 2022 07:06:17 +0000 Message-Id: <47414d06a7f103b273f5bce516da69da9f810884.1662275167.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This commit adds floating point register number validation on 'Zdinx'/'Zqinx' extensions by separating handling on 'D'/'Q' and 'Zdinx' /'Zqinx' extensions (per-xlen on 'Zdinx'/'Zqinx'). bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Reflect new instruction classes. (riscv_multi_subset_supports_ext): Reflect new instruction classes. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Add handling for new instruction flag INSN_F_OR_X. * testsuite/gas/riscv/zdinx-32-regpair.s: Test RV32_Zdinx register pairs. * testsuite/gas/riscv/zdinx-32-regpair.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-dis.s: New test to make sure that invalid encoding is not disassembled. * testsuite/gas/riscv/zdinx-32-regpair-dis.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-fail.s: Test RV32_Zdinx register pairs (failure cases). * testsuite/gas/riscv/zdinx-32-regpair-fail.d: Likewise. * testsuite/gas/riscv/zdinx-32-regpair-fail.l: Likewise. * testsuite/gas/riscv/zqinx-64-regpair.s: Test RV64_Zqinx register pairs. * testsuite/gas/riscv/zqinx-64-regpair.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-dis.s: New test to make sure that invalid encodings are not disassembled. * testsuite/gas/riscv/zqinx-32-regpair-dis.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-dis.s: New test to make sure that invalid encoding is not disassembled. * testsuite/gas/riscv/zqinx-64-regpair-dis.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-fail.s: Test RV64_Zqinx register pairs (failure cases). * testsuite/gas/riscv/zqinx-64-regpair-fail.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-fail.l: Likewise. * testsuite/gas/riscv/zqinx-32-regpair.s: Test RV32_Zqinx register pairs and quad-register groups. * testsuite/gas/riscv/zqinx-32-regpair.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-fail.s: Test RV32_Zqinx register pairs and quad-register groups (failure cases). * testsuite/gas/riscv/zqinx-32-regpair-fail.d: Likewise. * testsuite/gas/riscv/zqinx-32-regpair-fail.l: Likewise. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZDINX and INSN_CLASS_ZQINX narrow instruction classes. (INSN_F_OR_X): New pinfo flag for better error handling. opcodes/ChangeLog: * riscv-opc.c (MASK_RS3): New mask macro for RS3 field. (match_opcode_zdinx_rtype_g2, match_opcode_zdinx_rtype_g4, match_rs1_eq_rs2_zdinx_rtype_g2, match_rs1_eq_rs2_zdinx_rtype_g4, match_opcode_zdinx_r4type_g2, match_opcode_zdinx_r4type_g4, match_opcode_zdinx_itype_g1_2, match_opcode_zdinx_itype_g1_4, match_opcode_zdinx_itype_g2_1, match_opcode_zdinx_itype_g2_2, match_opcode_zdinx_itype_g2_4, match_opcode_zdinx_itype_g4_1, match_opcode_zdinx_itype_g4_2, match_opcode_zdinx_itype_g4_4, match_opcode_zdinx_cmp_g2, match_opcode_zdinx_cmp_g4): New instruction matching functions with register pair / quad-register group validation. (riscv_opcodes): Use new instruction classes, matching functions and the pinfo flag. --- bfd/elfxx-riscv.c | 8 + gas/config/tc-riscv.c | 21 +- .../gas/riscv/zdinx-32-regpair-dis.d | 11 + .../gas/riscv/zdinx-32-regpair-dis.s | 5 + .../gas/riscv/zdinx-32-regpair-fail.d | 3 + .../gas/riscv/zdinx-32-regpair-fail.l | 111 ++++ .../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++ gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 +++ gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++ .../gas/riscv/zqinx-32-regpair-dis.d | 12 + .../gas/riscv/zqinx-32-regpair-dis.s | 7 + .../gas/riscv/zqinx-32-regpair-fail.d | 3 + .../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++ .../gas/riscv/zqinx-32-regpair-fail.s | 218 +++++++ gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 +++ gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++ .../gas/riscv/zqinx-64-regpair-dis.d | 11 + .../gas/riscv/zqinx-64-regpair-dis.s | 5 + .../gas/riscv/zqinx-64-regpair-fail.d | 3 + .../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++ .../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++ gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++ gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++ include/opcode/riscv.h | 10 +- opcodes/riscv-opc.c | 539 ++++++++++++++---- 25 files changed, 1886 insertions(+), 108 deletions(-) create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 8cb3c8d4930..b6c2eb9fe50 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -2334,6 +2334,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, && riscv_subset_supports (rps, "q")) || (riscv_subset_supports (rps, "zhinxmin") && riscv_subset_supports (rps, "zqinx"))); + case INSN_CLASS_ZDINX: + return riscv_subset_supports (rps, "zdinx"); + case INSN_CLASS_ZQINX: + return riscv_subset_supports (rps, "zqinx"); case INSN_CLASS_ZBA: return riscv_subset_supports (rps, "zba"); case INSN_CLASS_ZBB: @@ -2469,6 +2473,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "zhinxmin"; else return _("zfhmin' and `q', or `zhinxmin' and `zqinx"); + case INSN_CLASS_ZDINX: + return "zdinx"; + case INSN_CLASS_ZQINX: + return "zqinx"; case INSN_CLASS_ZBA: return "zba"; case INSN_CLASS_ZBB: diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 34ce68e8252..56b4242b101 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2306,6 +2306,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, int argnum; const struct percent_op_match *p; struct riscv_ip_error error; + enum riscv_insn_class insn_class; error.msg = "unrecognized opcode"; error.statement = str; error.missing_ext = NULL; @@ -2332,8 +2333,24 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, if (!riscv_multi_subset_supports (&riscv_rps_as, insn->insn_class)) { - error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as, - insn->insn_class); + insn_class = insn->insn_class; + if (insn->pinfo != INSN_MACRO && insn->pinfo & INSN_F_OR_X) + switch (insn_class) + { + case INSN_CLASS_D: + case INSN_CLASS_ZDINX: + insn_class = INSN_CLASS_D_OR_ZDINX; + break; + case INSN_CLASS_Q: + case INSN_CLASS_ZQINX: + insn_class = INSN_CLASS_Q_OR_ZQINX; + break; + default: + break; + } + if (!riscv_multi_subset_supports (&riscv_rps_as, insn_class)) + error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as, + insn_class); continue; } diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d new file mode 100644 index 00000000000..018a0e51f03 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d @@ -0,0 +1,11 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+02627153[ ]+fadd.d[ ]+x2,x4,x6 +[ ]+[0-9a-f]+:[ ]+0272f1d3[ ]+\.4byte[ ]+0x272f1d3 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s new file mode 100644 index 00000000000..5c28ca7cdc9 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s @@ -0,0 +1,5 @@ +target: + # fadd.d x2, x4, x6 + .insn r OP_FP, 0x7, 0x01, x2, x4, x6 + # fadd.d x3, x5, x7 (invalid) + .insn r OP_FP, 0x7, 0x01, x3, x5, x7 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d new file mode 100644 index 00000000000..f26096ca1c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair-fail.s +#error_output: zdinx-32-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l new file mode 100644 index 00000000000..ce4a8eaa42a --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l @@ -0,0 +1,111 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.d a1,a2,a4' +.*Error: illegal operands `fadd\.d a1,a2,a4,rne' +.*Error: illegal operands `fadd\.d a0,a1,a4' +.*Error: illegal operands `fadd\.d a0,a1,a4,rne' +.*Error: illegal operands `fadd\.d a0,a2,a1' +.*Error: illegal operands `fadd\.d a0,a2,a1,rne' +.*Error: illegal operands `fsub\.d a1,a2,a4' +.*Error: illegal operands `fsub\.d a1,a2,a4,rne' +.*Error: illegal operands `fsub\.d a0,a1,a4' +.*Error: illegal operands `fsub\.d a0,a1,a4,rne' +.*Error: illegal operands `fsub\.d a0,a2,a1' +.*Error: illegal operands `fsub\.d a0,a2,a1,rne' +.*Error: illegal operands `fmul\.d a1,a2,a4' +.*Error: illegal operands `fmul\.d a1,a2,a4,rne' +.*Error: illegal operands `fmul\.d a0,a1,a4' +.*Error: illegal operands `fmul\.d a0,a1,a4,rne' +.*Error: illegal operands `fmul\.d a0,a2,a1' +.*Error: illegal operands `fmul\.d a0,a2,a1,rne' +.*Error: illegal operands `fdiv\.d a1,a2,a4' +.*Error: illegal operands `fdiv\.d a1,a2,a4,rne' +.*Error: illegal operands `fdiv\.d a0,a1,a4' +.*Error: illegal operands `fdiv\.d a0,a1,a4,rne' +.*Error: illegal operands `fdiv\.d a0,a2,a1' +.*Error: illegal operands `fdiv\.d a0,a2,a1,rne' +.*Error: illegal operands `fsqrt\.d a1,a2' +.*Error: illegal operands `fsqrt\.d a1,a2,rne' +.*Error: illegal operands `fsqrt\.d a0,a1' +.*Error: illegal operands `fsqrt\.d a0,a1,rne' +.*Error: illegal operands `fmin\.d a1,a2,a4' +.*Error: illegal operands `fmin\.d a0,a1,a4' +.*Error: illegal operands `fmin\.d a0,a2,a1' +.*Error: illegal operands `fmax\.d a1,a2,a4' +.*Error: illegal operands `fmax\.d a0,a1,a4' +.*Error: illegal operands `fmax\.d a0,a2,a1' +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6' +.*Error: illegal operands `fmadd\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6' +.*Error: illegal operands `fmadd\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6' +.*Error: illegal operands `fmadd\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1' +.*Error: illegal operands `fmadd\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6' +.*Error: illegal operands `fnmadd\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6' +.*Error: illegal operands `fnmadd\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6' +.*Error: illegal operands `fnmadd\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1' +.*Error: illegal operands `fnmadd\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6' +.*Error: illegal operands `fmsub\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6' +.*Error: illegal operands `fmsub\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6' +.*Error: illegal operands `fmsub\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1' +.*Error: illegal operands `fmsub\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6' +.*Error: illegal operands `fnmsub\.d a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6' +.*Error: illegal operands `fnmsub\.d a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6' +.*Error: illegal operands `fnmsub\.d a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1' +.*Error: illegal operands `fnmsub\.d a0,a2,a4,a1,rne' +.*Error: illegal operands `fsgnj\.d a1,a2,a4' +.*Error: illegal operands `fsgnj\.d a0,a1,a4' +.*Error: illegal operands `fsgnj\.d a0,a2,a1' +.*Error: illegal operands `fsgnjn\.d a1,a2,a4' +.*Error: illegal operands `fsgnjn\.d a0,a1,a4' +.*Error: illegal operands `fsgnjn\.d a0,a2,a1' +.*Error: illegal operands `fsgnjx\.d a1,a2,a4' +.*Error: illegal operands `fsgnjx\.d a0,a1,a4' +.*Error: illegal operands `fsgnjx\.d a0,a2,a1' +.*Error: illegal operands `fmv\.d a1,a2' +.*Error: illegal operands `fmv\.d a0,a1' +.*Error: illegal operands `fneg\.d a1,a2' +.*Error: illegal operands `fneg\.d a0,a1' +.*Error: illegal operands `fabs\.d a1,a2' +.*Error: illegal operands `fabs\.d a0,a1' +.*Error: illegal operands `feq\.d a0,a1,a4' +.*Error: illegal operands `feq\.d a0,a2,a1' +.*Error: illegal operands `flt\.d a0,a1,a4' +.*Error: illegal operands `flt\.d a0,a2,a1' +.*Error: illegal operands `fle\.d a0,a1,a4' +.*Error: illegal operands `fle\.d a0,a2,a1' +.*Error: illegal operands `fgt\.d a0,a1,a4' +.*Error: illegal operands `fgt\.d a0,a2,a1' +.*Error: illegal operands `fge\.d a0,a1,a4' +.*Error: illegal operands `fge\.d a0,a2,a1' +.*Error: illegal operands `fclass\.d a0,a1' +.*Error: illegal operands `fcvt\.w\.d a0,a1' +.*Error: illegal operands `fcvt\.w\.d a0,a1,rne' +.*Error: illegal operands `fcvt\.w\.d a3,a1' +.*Error: illegal operands `fcvt\.w\.d a3,a1,rne' +.*Error: illegal operands `fcvt\.wu\.d a0,a1' +.*Error: illegal operands `fcvt\.wu\.d a0,a1,rne' +.*Error: illegal operands `fcvt\.wu\.d a3,a1' +.*Error: illegal operands `fcvt\.wu\.d a3,a1,rne' +.*Error: illegal operands `fcvt\.d\.w a1,a2' +.*Error: illegal operands `fcvt\.d\.w a1,a3' +.*Error: illegal operands `fcvt\.d\.wu a1,a2' +.*Error: illegal operands `fcvt\.d\.wu a1,a3' +.*Error: illegal operands `fcvt\.s\.d a0,a1' +.*Error: illegal operands `fcvt\.s\.d a0,a1,rne' +.*Error: illegal operands `fcvt\.s\.d a3,a1' +.*Error: illegal operands `fcvt\.s\.d a3,a1,rne' +.*Error: illegal operands `fcvt\.d\.s a1,a2' +.*Error: illegal operands `fcvt\.d\.s a1,a3' diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s new file mode 100644 index 00000000000..2243d89a6d3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s @@ -0,0 +1,116 @@ +target: + fadd.d a1, a2, a4 + fadd.d a1, a2, a4, rne + fadd.d a0, a1, a4 + fadd.d a0, a1, a4, rne + fadd.d a0, a2, a1 + fadd.d a0, a2, a1, rne + fsub.d a1, a2, a4 + fsub.d a1, a2, a4, rne + fsub.d a0, a1, a4 + fsub.d a0, a1, a4, rne + fsub.d a0, a2, a1 + fsub.d a0, a2, a1, rne + fmul.d a1, a2, a4 + fmul.d a1, a2, a4, rne + fmul.d a0, a1, a4 + fmul.d a0, a1, a4, rne + fmul.d a0, a2, a1 + fmul.d a0, a2, a1, rne + fdiv.d a1, a2, a4 + fdiv.d a1, a2, a4, rne + fdiv.d a0, a1, a4 + fdiv.d a0, a1, a4, rne + fdiv.d a0, a2, a1 + fdiv.d a0, a2, a1, rne + fsqrt.d a1, a2 + fsqrt.d a1, a2, rne + fsqrt.d a0, a1 + fsqrt.d a0, a1, rne + fmin.d a1, a2, a4 + fmin.d a0, a1, a4 + fmin.d a0, a2, a1 + fmax.d a1, a2, a4 + fmax.d a0, a1, a4 + fmax.d a0, a2, a1 + fmadd.d a1, a2, a4, a6 + fmadd.d a1, a2, a4, a6, rne + fmadd.d a0, a1, a4, a6 + fmadd.d a0, a1, a4, a6, rne + fmadd.d a0, a2, a1, a6 + fmadd.d a0, a2, a1, a6, rne + fmadd.d a0, a2, a4, a1 + fmadd.d a0, a2, a4, a1, rne + fnmadd.d a1, a2, a4, a6 + fnmadd.d a1, a2, a4, a6, rne + fnmadd.d a0, a1, a4, a6 + fnmadd.d a0, a1, a4, a6, rne + fnmadd.d a0, a2, a1, a6 + fnmadd.d a0, a2, a1, a6, rne + fnmadd.d a0, a2, a4, a1 + fnmadd.d a0, a2, a4, a1, rne + fmsub.d a1, a2, a4, a6 + fmsub.d a1, a2, a4, a6, rne + fmsub.d a0, a1, a4, a6 + fmsub.d a0, a1, a4, a6, rne + fmsub.d a0, a2, a1, a6 + fmsub.d a0, a2, a1, a6, rne + fmsub.d a0, a2, a4, a1 + fmsub.d a0, a2, a4, a1, rne + fnmsub.d a1, a2, a4, a6 + fnmsub.d a1, a2, a4, a6, rne + fnmsub.d a0, a1, a4, a6 + fnmsub.d a0, a1, a4, a6, rne + fnmsub.d a0, a2, a1, a6 + fnmsub.d a0, a2, a1, a6, rne + fnmsub.d a0, a2, a4, a1 + fnmsub.d a0, a2, a4, a1, rne + fsgnj.d a1, a2, a4 + fsgnj.d a0, a1, a4 + fsgnj.d a0, a2, a1 + fsgnjn.d a1, a2, a4 + fsgnjn.d a0, a1, a4 + fsgnjn.d a0, a2, a1 + fsgnjx.d a1, a2, a4 + fsgnjx.d a0, a1, a4 + fsgnjx.d a0, a2, a1 + fmv.d a1, a2 + fmv.d a0, a1 + fneg.d a1, a2 + fneg.d a0, a1 + fabs.d a1, a2 + fabs.d a0, a1 + # Compare instructions: destination is a GPR + feq.d a0, a1, a4 + feq.d a0, a2, a1 + flt.d a0, a1, a4 + flt.d a0, a2, a1 + fle.d a0, a1, a4 + fle.d a0, a2, a1 + fgt.d a0, a1, a4 + fgt.d a0, a2, a1 + fge.d a0, a1, a4 + fge.d a0, a2, a1 + # fclass instruction: destination is a GPR + fclass.d a0, a1 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.d a0, a1 + fcvt.w.d a0, a1, rne + fcvt.w.d a3, a1 + fcvt.w.d a3, a1, rne + fcvt.wu.d a0, a1 + fcvt.wu.d a0, a1, rne + fcvt.wu.d a3, a1 + fcvt.wu.d a3, a1, rne + fcvt.d.w a1, a2 + fcvt.d.w a1, a3 + fcvt.d.wu a1, a2 + fcvt.d.wu a1, a3 + # fcvt instructions (float-float; FP32 operand can be odd) + fcvt.s.d a0, a1 + fcvt.s.d a0, a1, rne + fcvt.s.d a3, a1 + fcvt.s.d a3, a1, rne + fcvt.d.s a1, a2 + fcvt.d.s a1, a3 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.d b/gas/testsuite/gas/riscv/zdinx-32-regpair.d new file mode 100644 index 00000000000..eb8aa24b8d0 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.d @@ -0,0 +1,65 @@ +#as: -march=rv32ima_zdinx +#source: zdinx-32-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+02e67553[ ]+fadd.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+02e60553[ ]+fadd.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ae67553[ ]+fsub.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ae60553[ ]+fsub.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+12e67553[ ]+fmul.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+12e60553[ ]+fmul.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ae67553[ ]+fdiv.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ae60553[ ]+fdiv.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5a067553[ ]+fsqrt.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5a060553[ ]+fsqrt.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ae60553[ ]+fmin.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ae61553[ ]+fmax.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+82e67543[ ]+fmadd.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e60543[ ]+fmadd.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e6754f[ ]+fnmadd.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6054f[ ]+fnmadd.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e67547[ ]+fmsub.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e60547[ ]+fmsub.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e6754b[ ]+fnmsub.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6054b[ ]+fnmsub.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+22e60553[ ]+fsgnj.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e61553[ ]+fsgnjn.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e62553[ ]+fsgnjx.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22c60553[ ]+fmv.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c61553[ ]+fneg.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c62553[ ]+fabs.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+a2e62553[ ]+feq.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e625d3[ ]+feq.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e61553[ ]+flt.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e615d3[ ]+flt.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e60553[ ]+fle.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e605d3[ ]+fle.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2c71553[ ]+flt.d[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c715d3[ ]+flt.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c70553[ ]+fle.d[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c705d3[ ]+fle.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+e2061553[ ]+fclass.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e20615d3[ ]+fclass.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c2067553[ ]+fcvt.w.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c2060553[ ]+fcvt.w.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c20675d3[ ]+fcvt.w.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c20605d3[ ]+fcvt.w.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c2167553[ ]+fcvt.wu.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c2160553[ ]+fcvt.wu.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c21675d3[ ]+fcvt.wu.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c21605d3[ ]+fcvt.wu.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+d2060553[ ]+fcvt.d.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2160553[ ]+fcvt.d.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+40167553[ ]+fcvt.s.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40160553[ ]+fcvt.s.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+401675d3[ ]+fcvt.s.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+401605d3[ ]+fcvt.s.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+42060553[ ]+fcvt.d.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx-32-regpair.s b/gas/testsuite/gas/riscv/zdinx-32-regpair.s new file mode 100644 index 00000000000..cef479a976e --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-32-regpair.s @@ -0,0 +1,62 @@ +target: + fadd.d a0, a2, a4 + fadd.d a0, a2, a4, rne + fsub.d a0, a2, a4 + fsub.d a0, a2, a4, rne + fmul.d a0, a2, a4 + fmul.d a0, a2, a4, rne + fdiv.d a0, a2, a4 + fdiv.d a0, a2, a4, rne + fsqrt.d a0, a2 + fsqrt.d a0, a2, rne + fmin.d a0, a2, a4 + fmax.d a0, a2, a4 + fmadd.d a0, a2, a4, a6 + fmadd.d a0, a2, a4, a6, rne + fnmadd.d a0, a2, a4, a6 + fnmadd.d a0, a2, a4, a6, rne + fmsub.d a0, a2, a4, a6 + fmsub.d a0, a2, a4, a6, rne + fnmsub.d a0, a2, a4, a6 + fnmsub.d a0, a2, a4, a6, rne + fsgnj.d a0, a2, a4 + fsgnjn.d a0, a2, a4 + fsgnjx.d a0, a2, a4 + fmv.d a0, a2 + fneg.d a0, a2 + fabs.d a0, a2 + # Compare instructions: destination is a GPR + feq.d a0, a2, a4 + feq.d a1, a2, a4 + flt.d a0, a2, a4 + flt.d a1, a2, a4 + fle.d a0, a2, a4 + fle.d a1, a2, a4 + fgt.d a0, a2, a4 + fgt.d a1, a2, a4 + fge.d a0, a2, a4 + fge.d a1, a2, a4 + # fclass instruction: destination is a GPR + fclass.d a0, a2 + fclass.d a1, a2 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.d a0, a2 + fcvt.w.d a0, a2, rne + fcvt.w.d a1, a2 + fcvt.w.d a1, a2, rne + fcvt.wu.d a0, a2 + fcvt.wu.d a0, a2, rne + fcvt.wu.d a1, a2 + fcvt.wu.d a1, a2, rne + fcvt.d.w a0, a2 + fcvt.d.w a0, a1 + fcvt.d.wu a0, a2 + fcvt.d.wu a0, a1 + # fcvt instructions (float-float; FP32 operand can be odd) + fcvt.s.d a0, a2 + fcvt.s.d a0, a2, rne + fcvt.s.d a1, a2 + fcvt.s.d a1, a2, rne + fcvt.d.s a0, a2 + fcvt.d.s a0, a1 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d new file mode 100644 index 00000000000..5af92477116 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d @@ -0,0 +1,12 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+x4,x8,x12 +[ ]+[0-9a-f]+:[ ]+06d4f2d3[ ]+\.4byte[ ]+0x6d4f2d3 +[ ]+[0-9a-f]+:[ ]+06e57353[ ]+\.4byte[ ]+0x6e57353 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s new file mode 100644 index 00000000000..c6ce9513175 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s @@ -0,0 +1,7 @@ +target: + # fadd.q x4, x8, x12 + .insn r OP_FP, 0x7, 0x03, x4, x8, x12 + # fadd.q x5, x9, x13 (invalid) + .insn r OP_FP, 0x7, 0x03, x5, x9, x13 + # fadd.q x6, x10, x14 (invalid) + .insn r OP_FP, 0x7, 0x03, x6, x10, x14 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d new file mode 100644 index 00000000000..957401f4683 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair-fail.s +#error_output: zqinx-32-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l new file mode 100644 index 00000000000..61afcc84d79 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l @@ -0,0 +1,212 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.q x5,x8,x12' +.*Error: illegal operands `fadd\.q x5,x8,x12,rne' +.*Error: illegal operands `fadd\.q x6,x8,x12' +.*Error: illegal operands `fadd\.q x6,x8,x12,rne' +.*Error: illegal operands `fadd\.q x4,x5,x12' +.*Error: illegal operands `fadd\.q x4,x5,x12,rne' +.*Error: illegal operands `fadd\.q x4,x6,x12' +.*Error: illegal operands `fadd\.q x4,x6,x12,rne' +.*Error: illegal operands `fadd\.q x4,x8,x5' +.*Error: illegal operands `fadd\.q x4,x8,x5,rne' +.*Error: illegal operands `fadd\.q x4,x8,x6' +.*Error: illegal operands `fadd\.q x4,x8,x6,rne' +.*Error: illegal operands `fsub\.q x5,x8,x12' +.*Error: illegal operands `fsub\.q x5,x8,x12,rne' +.*Error: illegal operands `fsub\.q x6,x8,x12' +.*Error: illegal operands `fsub\.q x6,x8,x12,rne' +.*Error: illegal operands `fsub\.q x4,x5,x12' +.*Error: illegal operands `fsub\.q x4,x5,x12,rne' +.*Error: illegal operands `fsub\.q x4,x6,x12' +.*Error: illegal operands `fsub\.q x4,x6,x12,rne' +.*Error: illegal operands `fsub\.q x4,x8,x5' +.*Error: illegal operands `fsub\.q x4,x8,x5,rne' +.*Error: illegal operands `fsub\.q x4,x8,x6' +.*Error: illegal operands `fsub\.q x4,x8,x6,rne' +.*Error: illegal operands `fmul\.q x5,x8,x12' +.*Error: illegal operands `fmul\.q x5,x8,x12,rne' +.*Error: illegal operands `fmul\.q x6,x8,x12' +.*Error: illegal operands `fmul\.q x6,x8,x12,rne' +.*Error: illegal operands `fmul\.q x4,x5,x12' +.*Error: illegal operands `fmul\.q x4,x5,x12,rne' +.*Error: illegal operands `fmul\.q x4,x6,x12' +.*Error: illegal operands `fmul\.q x4,x6,x12,rne' +.*Error: illegal operands `fmul\.q x4,x8,x5' +.*Error: illegal operands `fmul\.q x4,x8,x5,rne' +.*Error: illegal operands `fmul\.q x4,x8,x6' +.*Error: illegal operands `fmul\.q x4,x8,x6,rne' +.*Error: illegal operands `fdiv\.q x5,x8,x12' +.*Error: illegal operands `fdiv\.q x5,x8,x12,rne' +.*Error: illegal operands `fdiv\.q x6,x8,x12' +.*Error: illegal operands `fdiv\.q x6,x8,x12,rne' +.*Error: illegal operands `fdiv\.q x4,x5,x12' +.*Error: illegal operands `fdiv\.q x4,x5,x12,rne' +.*Error: illegal operands `fdiv\.q x4,x6,x12' +.*Error: illegal operands `fdiv\.q x4,x6,x12,rne' +.*Error: illegal operands `fdiv\.q x4,x8,x5' +.*Error: illegal operands `fdiv\.q x4,x8,x5,rne' +.*Error: illegal operands `fdiv\.q x4,x8,x6' +.*Error: illegal operands `fdiv\.q x4,x8,x6,rne' +.*Error: illegal operands `fsqrt\.q x5,x8' +.*Error: illegal operands `fsqrt\.q x5,x8,rne' +.*Error: illegal operands `fsqrt\.q x6,x8' +.*Error: illegal operands `fsqrt\.q x6,x8,rne' +.*Error: illegal operands `fsqrt\.q x4,x5' +.*Error: illegal operands `fsqrt\.q x4,x5,rne' +.*Error: illegal operands `fsqrt\.q x4,x6' +.*Error: illegal operands `fsqrt\.q x4,x6,rne' +.*Error: illegal operands `fmin\.q x5,x8,x12' +.*Error: illegal operands `fmin\.q x6,x8,x12' +.*Error: illegal operands `fmin\.q x4,x5,x12' +.*Error: illegal operands `fmin\.q x4,x6,x12' +.*Error: illegal operands `fmin\.q x4,x8,x5' +.*Error: illegal operands `fmin\.q x4,x8,x6' +.*Error: illegal operands `fmax\.q x5,x8,x12' +.*Error: illegal operands `fmax\.q x6,x8,x12' +.*Error: illegal operands `fmax\.q x4,x5,x12' +.*Error: illegal operands `fmax\.q x4,x6,x12' +.*Error: illegal operands `fmax\.q x4,x8,x5' +.*Error: illegal operands `fmax\.q x4,x8,x6' +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16' +.*Error: illegal operands `fmadd\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16' +.*Error: illegal operands `fmadd\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16' +.*Error: illegal operands `fmadd\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16' +.*Error: illegal operands `fmadd\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16' +.*Error: illegal operands `fmadd\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16' +.*Error: illegal operands `fmadd\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6' +.*Error: illegal operands `fmadd\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16' +.*Error: illegal operands `fnmadd\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16' +.*Error: illegal operands `fnmadd\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16' +.*Error: illegal operands `fnmadd\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16' +.*Error: illegal operands `fnmadd\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16' +.*Error: illegal operands `fnmadd\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16' +.*Error: illegal operands `fnmadd\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6' +.*Error: illegal operands `fnmadd\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16' +.*Error: illegal operands `fmsub\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16' +.*Error: illegal operands `fmsub\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16' +.*Error: illegal operands `fmsub\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16' +.*Error: illegal operands `fmsub\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16' +.*Error: illegal operands `fmsub\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16' +.*Error: illegal operands `fmsub\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6' +.*Error: illegal operands `fmsub\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16' +.*Error: illegal operands `fnmsub\.q x5,x8,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16' +.*Error: illegal operands `fnmsub\.q x6,x8,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16' +.*Error: illegal operands `fnmsub\.q x4,x5,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16' +.*Error: illegal operands `fnmsub\.q x4,x6,x12,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16' +.*Error: illegal operands `fnmsub\.q x4,x8,x5,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16' +.*Error: illegal operands `fnmsub\.q x4,x8,x6,x16,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x5,rne' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6' +.*Error: illegal operands `fnmsub\.q x4,x8,x12,x6,rne' +.*Error: illegal operands `fsgnj\.q x5,x8,x12' +.*Error: illegal operands `fsgnj\.q x6,x8,x12' +.*Error: illegal operands `fsgnj\.q x4,x5,x12' +.*Error: illegal operands `fsgnj\.q x4,x6,x12' +.*Error: illegal operands `fsgnj\.q x4,x8,x5' +.*Error: illegal operands `fsgnj\.q x4,x8,x6' +.*Error: illegal operands `fsgnjn\.q x5,x8,x12' +.*Error: illegal operands `fsgnjn\.q x6,x8,x12' +.*Error: illegal operands `fsgnjn\.q x4,x5,x12' +.*Error: illegal operands `fsgnjn\.q x4,x6,x12' +.*Error: illegal operands `fsgnjn\.q x4,x8,x5' +.*Error: illegal operands `fsgnjn\.q x4,x8,x6' +.*Error: illegal operands `fsgnjx\.q x5,x8,x12' +.*Error: illegal operands `fsgnjx\.q x6,x8,x12' +.*Error: illegal operands `fsgnjx\.q x4,x5,x12' +.*Error: illegal operands `fsgnjx\.q x4,x6,x12' +.*Error: illegal operands `fsgnjx\.q x4,x8,x5' +.*Error: illegal operands `fsgnjx\.q x4,x8,x6' +.*Error: illegal operands `fmv\.q x5,x8' +.*Error: illegal operands `fmv\.q x6,x8' +.*Error: illegal operands `fmv\.q x4,x5' +.*Error: illegal operands `fmv\.q x4,x6' +.*Error: illegal operands `fneg\.q x5,x8' +.*Error: illegal operands `fneg\.q x6,x8' +.*Error: illegal operands `fneg\.q x4,x5' +.*Error: illegal operands `fneg\.q x4,x6' +.*Error: illegal operands `fabs\.q x5,x8' +.*Error: illegal operands `fabs\.q x6,x8' +.*Error: illegal operands `fabs\.q x4,x5' +.*Error: illegal operands `fabs\.q x4,x6' +.*Error: illegal operands `feq\.q x4,x5,x12' +.*Error: illegal operands `feq\.q x4,x6,x12' +.*Error: illegal operands `feq\.q x4,x8,x5' +.*Error: illegal operands `feq\.q x4,x8,x6' +.*Error: illegal operands `flt\.q x4,x5,x12' +.*Error: illegal operands `flt\.q x4,x6,x12' +.*Error: illegal operands `flt\.q x4,x8,x5' +.*Error: illegal operands `flt\.q x4,x8,x6' +.*Error: illegal operands `fle\.q x4,x5,x12' +.*Error: illegal operands `fle\.q x4,x6,x12' +.*Error: illegal operands `fle\.q x4,x8,x5' +.*Error: illegal operands `fle\.q x4,x8,x6' +.*Error: illegal operands `fgt\.q x4,x5,x12' +.*Error: illegal operands `fgt\.q x4,x6,x12' +.*Error: illegal operands `fgt\.q x4,x8,x5' +.*Error: illegal operands `fgt\.q x4,x8,x6' +.*Error: illegal operands `fge\.q x4,x5,x12' +.*Error: illegal operands `fge\.q x4,x6,x12' +.*Error: illegal operands `fge\.q x4,x8,x5' +.*Error: illegal operands `fge\.q x4,x8,x6' +.*Error: illegal operands `fclass\.q x4,x5' +.*Error: illegal operands `fclass\.q x4,x6' +.*Error: illegal operands `fcvt\.w\.q x4,x5' +.*Error: illegal operands `fcvt\.w\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.w\.q x4,x6' +.*Error: illegal operands `fcvt\.w\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.wu\.q x4,x5' +.*Error: illegal operands `fcvt\.wu\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.wu\.q x4,x6' +.*Error: illegal operands `fcvt\.wu\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.q\.w x5,x4' +.*Error: illegal operands `fcvt\.q\.w x6,x4' +.*Error: illegal operands `fcvt\.q\.wu x5,x4' +.*Error: illegal operands `fcvt\.q\.wu x6,x4' +.*Error: illegal operands `fcvt\.s\.q x4,x5' +.*Error: illegal operands `fcvt\.s\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.s\.q x4,x6' +.*Error: illegal operands `fcvt\.s\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.d\.q x4,x5' +.*Error: illegal operands `fcvt\.d\.q x4,x5,rne' +.*Error: illegal operands `fcvt\.d\.q x4,x6' +.*Error: illegal operands `fcvt\.d\.q x4,x6,rne' +.*Error: illegal operands `fcvt\.d\.q x5,x8' +.*Error: illegal operands `fcvt\.d\.q x5,x8,rne' +.*Error: illegal operands `fcvt\.q\.s x5,x4' +.*Error: illegal operands `fcvt\.q\.s x6,x4' +.*Error: illegal operands `fcvt\.q\.d x5,x4' +.*Error: illegal operands `fcvt\.q\.d x6,x4' +.*Error: illegal operands `fcvt\.q\.d x8,x5' diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s new file mode 100644 index 00000000000..9a1981f3bb3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s @@ -0,0 +1,218 @@ +target: + fadd.q x5, x8, x12 + fadd.q x5, x8, x12, rne + fadd.q x6, x8, x12 + fadd.q x6, x8, x12, rne + fadd.q x4, x5, x12 + fadd.q x4, x5, x12, rne + fadd.q x4, x6, x12 + fadd.q x4, x6, x12, rne + fadd.q x4, x8, x5 + fadd.q x4, x8, x5, rne + fadd.q x4, x8, x6 + fadd.q x4, x8, x6, rne + fsub.q x5, x8, x12 + fsub.q x5, x8, x12, rne + fsub.q x6, x8, x12 + fsub.q x6, x8, x12, rne + fsub.q x4, x5, x12 + fsub.q x4, x5, x12, rne + fsub.q x4, x6, x12 + fsub.q x4, x6, x12, rne + fsub.q x4, x8, x5 + fsub.q x4, x8, x5, rne + fsub.q x4, x8, x6 + fsub.q x4, x8, x6, rne + fmul.q x5, x8, x12 + fmul.q x5, x8, x12, rne + fmul.q x6, x8, x12 + fmul.q x6, x8, x12, rne + fmul.q x4, x5, x12 + fmul.q x4, x5, x12, rne + fmul.q x4, x6, x12 + fmul.q x4, x6, x12, rne + fmul.q x4, x8, x5 + fmul.q x4, x8, x5, rne + fmul.q x4, x8, x6 + fmul.q x4, x8, x6, rne + fdiv.q x5, x8, x12 + fdiv.q x5, x8, x12, rne + fdiv.q x6, x8, x12 + fdiv.q x6, x8, x12, rne + fdiv.q x4, x5, x12 + fdiv.q x4, x5, x12, rne + fdiv.q x4, x6, x12 + fdiv.q x4, x6, x12, rne + fdiv.q x4, x8, x5 + fdiv.q x4, x8, x5, rne + fdiv.q x4, x8, x6 + fdiv.q x4, x8, x6, rne + fsqrt.q x5, x8 + fsqrt.q x5, x8, rne + fsqrt.q x6, x8 + fsqrt.q x6, x8, rne + fsqrt.q x4, x5 + fsqrt.q x4, x5, rne + fsqrt.q x4, x6 + fsqrt.q x4, x6, rne + fmin.q x5, x8, x12 + fmin.q x6, x8, x12 + fmin.q x4, x5, x12 + fmin.q x4, x6, x12 + fmin.q x4, x8, x5 + fmin.q x4, x8, x6 + fmax.q x5, x8, x12 + fmax.q x6, x8, x12 + fmax.q x4, x5, x12 + fmax.q x4, x6, x12 + fmax.q x4, x8, x5 + fmax.q x4, x8, x6 + fmadd.q x5, x8, x12, x16 + fmadd.q x5, x8, x12, x16, rne + fmadd.q x6, x8, x12, x16 + fmadd.q x6, x8, x12, x16, rne + fmadd.q x4, x5, x12, x16 + fmadd.q x4, x5, x12, x16, rne + fmadd.q x4, x6, x12, x16 + fmadd.q x4, x6, x12, x16, rne + fmadd.q x4, x8, x5, x16 + fmadd.q x4, x8, x5, x16, rne + fmadd.q x4, x8, x6, x16 + fmadd.q x4, x8, x6, x16, rne + fmadd.q x4, x8, x12, x5 + fmadd.q x4, x8, x12, x5, rne + fmadd.q x4, x8, x12, x6 + fmadd.q x4, x8, x12, x6, rne + fnmadd.q x5, x8, x12, x16 + fnmadd.q x5, x8, x12, x16, rne + fnmadd.q x6, x8, x12, x16 + fnmadd.q x6, x8, x12, x16, rne + fnmadd.q x4, x5, x12, x16 + fnmadd.q x4, x5, x12, x16, rne + fnmadd.q x4, x6, x12, x16 + fnmadd.q x4, x6, x12, x16, rne + fnmadd.q x4, x8, x5, x16 + fnmadd.q x4, x8, x5, x16, rne + fnmadd.q x4, x8, x6, x16 + fnmadd.q x4, x8, x6, x16, rne + fnmadd.q x4, x8, x12, x5 + fnmadd.q x4, x8, x12, x5, rne + fnmadd.q x4, x8, x12, x6 + fnmadd.q x4, x8, x12, x6, rne + fmsub.q x5, x8, x12, x16 + fmsub.q x5, x8, x12, x16, rne + fmsub.q x6, x8, x12, x16 + fmsub.q x6, x8, x12, x16, rne + fmsub.q x4, x5, x12, x16 + fmsub.q x4, x5, x12, x16, rne + fmsub.q x4, x6, x12, x16 + fmsub.q x4, x6, x12, x16, rne + fmsub.q x4, x8, x5, x16 + fmsub.q x4, x8, x5, x16, rne + fmsub.q x4, x8, x6, x16 + fmsub.q x4, x8, x6, x16, rne + fmsub.q x4, x8, x12, x5 + fmsub.q x4, x8, x12, x5, rne + fmsub.q x4, x8, x12, x6 + fmsub.q x4, x8, x12, x6, rne + fnmsub.q x5, x8, x12, x16 + fnmsub.q x5, x8, x12, x16, rne + fnmsub.q x6, x8, x12, x16 + fnmsub.q x6, x8, x12, x16, rne + fnmsub.q x4, x5, x12, x16 + fnmsub.q x4, x5, x12, x16, rne + fnmsub.q x4, x6, x12, x16 + fnmsub.q x4, x6, x12, x16, rne + fnmsub.q x4, x8, x5, x16 + fnmsub.q x4, x8, x5, x16, rne + fnmsub.q x4, x8, x6, x16 + fnmsub.q x4, x8, x6, x16, rne + fnmsub.q x4, x8, x12, x5 + fnmsub.q x4, x8, x12, x5, rne + fnmsub.q x4, x8, x12, x6 + fnmsub.q x4, x8, x12, x6, rne + fsgnj.q x5, x8, x12 + fsgnj.q x6, x8, x12 + fsgnj.q x4, x5, x12 + fsgnj.q x4, x6, x12 + fsgnj.q x4, x8, x5 + fsgnj.q x4, x8, x6 + fsgnjn.q x5, x8, x12 + fsgnjn.q x6, x8, x12 + fsgnjn.q x4, x5, x12 + fsgnjn.q x4, x6, x12 + fsgnjn.q x4, x8, x5 + fsgnjn.q x4, x8, x6 + fsgnjx.q x5, x8, x12 + fsgnjx.q x6, x8, x12 + fsgnjx.q x4, x5, x12 + fsgnjx.q x4, x6, x12 + fsgnjx.q x4, x8, x5 + fsgnjx.q x4, x8, x6 + fmv.q x5, x8 + fmv.q x6, x8 + fmv.q x4, x5 + fmv.q x4, x6 + fneg.q x5, x8 + fneg.q x6, x8 + fneg.q x4, x5 + fneg.q x4, x6 + fabs.q x5, x8 + fabs.q x6, x8 + fabs.q x4, x5 + fabs.q x4, x6 + # Compare instructions: destination is a GPR + feq.q x4, x5, x12 + feq.q x4, x6, x12 + feq.q x4, x8, x5 + feq.q x4, x8, x6 + flt.q x4, x5, x12 + flt.q x4, x6, x12 + flt.q x4, x8, x5 + flt.q x4, x8, x6 + fle.q x4, x5, x12 + fle.q x4, x6, x12 + fle.q x4, x8, x5 + fle.q x4, x8, x6 + fgt.q x4, x5, x12 + fgt.q x4, x6, x12 + fgt.q x4, x8, x5 + fgt.q x4, x8, x6 + fge.q x4, x5, x12 + fge.q x4, x6, x12 + fge.q x4, x8, x5 + fge.q x4, x8, x6 + # fclass instruction: destination is a GPR + fclass.q x4, x5 + fclass.q x4, x6 + # fcvt instructions (float-int or int-float; + # integer operand register can be any) + fcvt.w.q x4, x5 + fcvt.w.q x4, x5, rne + fcvt.w.q x4, x6 + fcvt.w.q x4, x6, rne + fcvt.wu.q x4, x5 + fcvt.wu.q x4, x5, rne + fcvt.wu.q x4, x6 + fcvt.wu.q x4, x6, rne + fcvt.q.w x5, x4 + fcvt.q.w x6, x4 + fcvt.q.wu x5, x4 + fcvt.q.wu x6, x4 + # fcvt instructions (float-float; FP32 operand can be any, + # FP64 operand can be (x%4)==2) + fcvt.s.q x4, x5 + fcvt.s.q x4, x5, rne + fcvt.s.q x4, x6 + fcvt.s.q x4, x6, rne + fcvt.d.q x4, x5 + fcvt.d.q x4, x5, rne + fcvt.d.q x4, x6 + fcvt.d.q x4, x6, rne + fcvt.d.q x5, x8 + fcvt.d.q x5, x8, rne + fcvt.q.s x5, x4 + fcvt.q.s x6, x4 + fcvt.q.d x5, x4 + fcvt.q.d x6, x4 + fcvt.q.d x8, x5 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.d b/gas/testsuite/gas/riscv/zqinx-32-regpair.d new file mode 100644 index 00000000000..fcfdab597b1 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.d @@ -0,0 +1,66 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+0ec47253[ ]+fsub.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+16c47253[ ]+fmul.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+1ec47253[ ]+fdiv.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+5e047253[ ]+fsqrt.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+2ec40253[ ]+fmin.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+2ec41253[ ]+fmax.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+86c47243[ ]+fmadd.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c4724f[ ]+fnmadd.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c47247[ ]+fmsub.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+86c4724b[ ]+fnmsub.q[ ]+tp,s0,a2,a6 +[ ]+[0-9a-f]+:[ ]+26c40253[ ]+fsgnj.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26c41253[ ]+fsgnjn.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26c42253[ ]+fsgnjx.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+26840253[ ]+fmv.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+26841253[ ]+fneg.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+26842253[ ]+fabs.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+a6c42253[ ]+feq.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c422d3[ ]+feq.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c42353[ ]+feq.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c41253[ ]+flt.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c412d3[ ]+flt.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c41353[ ]+flt.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c40253[ ]+fle.q[ ]+tp,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c402d3[ ]+fle.q[ ]+t0,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6c40353[ ]+fle.q[ ]+t1,s0,a2 +[ ]+[0-9a-f]+:[ ]+a6861253[ ]+flt.q[ ]+tp,a2,s0 +[ ]+[0-9a-f]+:[ ]+a68612d3[ ]+flt.q[ ]+t0,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6861353[ ]+flt.q[ ]+t1,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6860253[ ]+fle.q[ ]+tp,a2,s0 +[ ]+[0-9a-f]+:[ ]+a68602d3[ ]+fle.q[ ]+t0,a2,s0 +[ ]+[0-9a-f]+:[ ]+a6860353[ ]+fle.q[ ]+t1,a2,s0 +[ ]+[0-9a-f]+:[ ]+e6041253[ ]+fclass.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+e60412d3[ ]+fclass.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+e6041353[ ]+fclass.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+c6047253[ ]+fcvt.w.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+c60472d3[ ]+fcvt.w.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+c6047353[ ]+fcvt.w.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+c6147253[ ]+fcvt.wu.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+c61472d3[ ]+fcvt.wu.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+c6147353[ ]+fcvt.wu.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+d6020453[ ]+fcvt.q.w[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+d6028453[ ]+fcvt.q.w[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+d6030453[ ]+fcvt.q.w[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+d6120453[ ]+fcvt.q.wu[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+d6128453[ ]+fcvt.q.wu[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+d6130453[ ]+fcvt.q.wu[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+40347253[ ]+fcvt.s.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+403472d3[ ]+fcvt.s.q[ ]+t0,s0 +[ ]+[0-9a-f]+:[ ]+40347353[ ]+fcvt.s.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+42347253[ ]+fcvt.d.q[ ]+tp,s0 +[ ]+[0-9a-f]+:[ ]+42347353[ ]+fcvt.d.q[ ]+t1,s0 +[ ]+[0-9a-f]+:[ ]+46020453[ ]+fcvt.q.s[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+46028453[ ]+fcvt.q.s[ ]+s0,t0 +[ ]+[0-9a-f]+:[ ]+46030453[ ]+fcvt.q.s[ ]+s0,t1 +[ ]+[0-9a-f]+:[ ]+46120453[ ]+fcvt.q.d[ ]+s0,tp +[ ]+[0-9a-f]+:[ ]+46130453[ ]+fcvt.q.d[ ]+s0,t1 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair.s b/gas/testsuite/gas/riscv/zqinx-32-regpair.s new file mode 100644 index 00000000000..2f340767376 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair.s @@ -0,0 +1,64 @@ +target: + fadd.q x4, x8, x12 + fsub.q x4, x8, x12 + fmul.q x4, x8, x12 + fdiv.q x4, x8, x12 + fsqrt.q x4, x8 + fmin.q x4, x8, x12 + fmax.q x4, x8, x12 + fmadd.q x4, x8, x12, x16 + fnmadd.q x4, x8, x12, x16 + fmsub.q x4, x8, x12, x16 + fnmsub.q x4, x8, x12, x16 + fsgnj.q x4, x8, x12 + fsgnjn.q x4, x8, x12 + fsgnjx.q x4, x8, x12 + fmv.q x4, x8 + fneg.q x4, x8 + fabs.q x4, x8 + # Compare instructions: destination is a GPR + feq.q x4, x8, x12 + feq.q x5, x8, x12 + feq.q x6, x8, x12 + flt.q x4, x8, x12 + flt.q x5, x8, x12 + flt.q x6, x8, x12 + fle.q x4, x8, x12 + fle.q x5, x8, x12 + fle.q x6, x8, x12 + fgt.q x4, x8, x12 + fgt.q x5, x8, x12 + fgt.q x6, x8, x12 + fge.q x4, x8, x12 + fge.q x5, x8, x12 + fge.q x6, x8, x12 + # fclass instruction: destination is a GPR + fclass.q x4, x8 + fclass.q x5, x8 + fclass.q x6, x8 + # fcvt instructions (float-int or int-float; + # integer operand register can be any) + fcvt.w.q x4, x8 + fcvt.w.q x5, x8 + fcvt.w.q x6, x8 + fcvt.wu.q x4, x8 + fcvt.wu.q x5, x8 + fcvt.wu.q x6, x8 + fcvt.q.w x8, x4 + fcvt.q.w x8, x5 + fcvt.q.w x8, x6 + fcvt.q.wu x8, x4 + fcvt.q.wu x8, x5 + fcvt.q.wu x8, x6 + # fcvt instructions (float-float; FP32 operand can be any, + # FP64 operand can be (x%4)==2) + fcvt.s.q x4, x8 + fcvt.s.q x5, x8 + fcvt.s.q x6, x8 + fcvt.d.q x4, x8 + fcvt.d.q x6, x8 + fcvt.q.s x8, x4 + fcvt.q.s x8, x5 + fcvt.q.s x8, x6 + fcvt.q.d x8, x4 + fcvt.q.d x8, x6 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d new file mode 100644 index 00000000000..894ed34948e --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d @@ -0,0 +1,11 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+06627153[ ]+fadd.q[ ]+x2,x4,x6 +[ ]+[0-9a-f]+:[ ]+0672f1d3[ ]+\.4byte[ ]+0x672f1d3 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s new file mode 100644 index 00000000000..619d0fa4fdb --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s @@ -0,0 +1,5 @@ +target: + # fadd.q x2, x4, x6 + .insn r OP_FP, 0x7, 0x03, x2, x4, x6 + # fadd.q x3, x5, x7 (invalid) + .insn r OP_FP, 0x7, 0x03, x3, x5, x7 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d new file mode 100644 index 00000000000..bac4e356675 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair-fail.s +#error_output: zqinx-64-regpair-fail.l diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l new file mode 100644 index 00000000000..5a48b7bd22f --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l @@ -0,0 +1,133 @@ +.*Assembler messages: +.*Error: illegal operands `fadd\.q a1,a2,a4' +.*Error: illegal operands `fadd\.q a1,a2,a4,rne' +.*Error: illegal operands `fadd\.q a0,a1,a4' +.*Error: illegal operands `fadd\.q a0,a1,a4,rne' +.*Error: illegal operands `fadd\.q a0,a2,a1' +.*Error: illegal operands `fadd\.q a0,a2,a1,rne' +.*Error: illegal operands `fsub\.q a1,a2,a4' +.*Error: illegal operands `fsub\.q a1,a2,a4,rne' +.*Error: illegal operands `fsub\.q a0,a1,a4' +.*Error: illegal operands `fsub\.q a0,a1,a4,rne' +.*Error: illegal operands `fsub\.q a0,a2,a1' +.*Error: illegal operands `fsub\.q a0,a2,a1,rne' +.*Error: illegal operands `fmul\.q a1,a2,a4' +.*Error: illegal operands `fmul\.q a1,a2,a4,rne' +.*Error: illegal operands `fmul\.q a0,a1,a4' +.*Error: illegal operands `fmul\.q a0,a1,a4,rne' +.*Error: illegal operands `fmul\.q a0,a2,a1' +.*Error: illegal operands `fmul\.q a0,a2,a1,rne' +.*Error: illegal operands `fdiv\.q a1,a2,a4' +.*Error: illegal operands `fdiv\.q a1,a2,a4,rne' +.*Error: illegal operands `fdiv\.q a0,a1,a4' +.*Error: illegal operands `fdiv\.q a0,a1,a4,rne' +.*Error: illegal operands `fdiv\.q a0,a2,a1' +.*Error: illegal operands `fdiv\.q a0,a2,a1,rne' +.*Error: illegal operands `fsqrt\.q a1,a2' +.*Error: illegal operands `fsqrt\.q a1,a2,rne' +.*Error: illegal operands `fsqrt\.q a0,a1' +.*Error: illegal operands `fsqrt\.q a0,a1,rne' +.*Error: illegal operands `fmin\.q a1,a2,a4' +.*Error: illegal operands `fmin\.q a0,a1,a4' +.*Error: illegal operands `fmin\.q a0,a2,a1' +.*Error: illegal operands `fmax\.q a1,a2,a4' +.*Error: illegal operands `fmax\.q a0,a1,a4' +.*Error: illegal operands `fmax\.q a0,a2,a1' +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6' +.*Error: illegal operands `fmadd\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6' +.*Error: illegal operands `fmadd\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6' +.*Error: illegal operands `fmadd\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1' +.*Error: illegal operands `fmadd\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6' +.*Error: illegal operands `fnmadd\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6' +.*Error: illegal operands `fnmadd\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6' +.*Error: illegal operands `fnmadd\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1' +.*Error: illegal operands `fnmadd\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6' +.*Error: illegal operands `fmsub\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6' +.*Error: illegal operands `fmsub\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6' +.*Error: illegal operands `fmsub\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1' +.*Error: illegal operands `fmsub\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6' +.*Error: illegal operands `fnmsub\.q a1,a2,a4,a6,rne' +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6' +.*Error: illegal operands `fnmsub\.q a0,a1,a4,a6,rne' +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6' +.*Error: illegal operands `fnmsub\.q a0,a2,a1,a6,rne' +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1' +.*Error: illegal operands `fnmsub\.q a0,a2,a4,a1,rne' +.*Error: illegal operands `fsgnj\.q a1,a2,a4' +.*Error: illegal operands `fsgnj\.q a0,a1,a4' +.*Error: illegal operands `fsgnj\.q a0,a2,a1' +.*Error: illegal operands `fsgnjn\.q a1,a2,a4' +.*Error: illegal operands `fsgnjn\.q a0,a1,a4' +.*Error: illegal operands `fsgnjn\.q a0,a2,a1' +.*Error: illegal operands `fsgnjx\.q a1,a2,a4' +.*Error: illegal operands `fsgnjx\.q a0,a1,a4' +.*Error: illegal operands `fsgnjx\.q a0,a2,a1' +.*Error: illegal operands `fmv\.q a1,a2' +.*Error: illegal operands `fmv\.q a0,a1' +.*Error: illegal operands `fneg\.q a1,a2' +.*Error: illegal operands `fneg\.q a0,a1' +.*Error: illegal operands `fabs\.q a1,a2' +.*Error: illegal operands `fabs\.q a0,a1' +.*Error: illegal operands `feq\.q a0,a1,a4' +.*Error: illegal operands `feq\.q a0,a2,a1' +.*Error: illegal operands `flt\.q a0,a1,a4' +.*Error: illegal operands `flt\.q a0,a2,a1' +.*Error: illegal operands `fle\.q a0,a1,a4' +.*Error: illegal operands `fle\.q a0,a2,a1' +.*Error: illegal operands `fgt\.q a0,a1,a4' +.*Error: illegal operands `fgt\.q a0,a2,a1' +.*Error: illegal operands `fge\.q a0,a1,a4' +.*Error: illegal operands `fge\.q a0,a2,a1' +.*Error: illegal operands `fclass\.q a0,a1' +.*Error: illegal operands `fcvt\.w\.q a0,a1' +.*Error: illegal operands `fcvt\.w\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.w\.q a3,a1' +.*Error: illegal operands `fcvt\.w\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.wu\.q a0,a1' +.*Error: illegal operands `fcvt\.wu\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.wu\.q a3,a1' +.*Error: illegal operands `fcvt\.wu\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.l\.q a0,a1' +.*Error: illegal operands `fcvt\.l\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.l\.q a3,a1' +.*Error: illegal operands `fcvt\.l\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.lu\.q a0,a1' +.*Error: illegal operands `fcvt\.lu\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.lu\.q a3,a1' +.*Error: illegal operands `fcvt\.lu\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.q\.w a1,a2' +.*Error: illegal operands `fcvt\.q\.w a1,a3' +.*Error: illegal operands `fcvt\.q\.wu a1,a2' +.*Error: illegal operands `fcvt\.q\.wu a1,a3' +.*Error: illegal operands `fcvt\.q\.l a1,a2' +.*Error: illegal operands `fcvt\.q\.l a1,a2,rne' +.*Error: illegal operands `fcvt\.q\.l a1,a3' +.*Error: illegal operands `fcvt\.q\.l a1,a3,rne' +.*Error: illegal operands `fcvt\.q\.lu a1,a2' +.*Error: illegal operands `fcvt\.q\.lu a1,a2,rne' +.*Error: illegal operands `fcvt\.q\.lu a1,a3' +.*Error: illegal operands `fcvt\.q\.lu a1,a3,rne' +.*Error: illegal operands `fcvt\.s\.q a0,a1' +.*Error: illegal operands `fcvt\.s\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.s\.q a3,a1' +.*Error: illegal operands `fcvt\.s\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.d\.q a0,a1' +.*Error: illegal operands `fcvt\.d\.q a0,a1,rne' +.*Error: illegal operands `fcvt\.d\.q a3,a1' +.*Error: illegal operands `fcvt\.d\.q a3,a1,rne' +.*Error: illegal operands `fcvt\.q\.s a1,a2' +.*Error: illegal operands `fcvt\.q\.s a1,a3' +.*Error: illegal operands `fcvt\.q\.d a1,a2' +.*Error: illegal operands `fcvt\.q\.d a1,a3' diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s new file mode 100644 index 00000000000..36680e0c47a --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s @@ -0,0 +1,138 @@ +target: + fadd.q a1, a2, a4 + fadd.q a1, a2, a4, rne + fadd.q a0, a1, a4 + fadd.q a0, a1, a4, rne + fadd.q a0, a2, a1 + fadd.q a0, a2, a1, rne + fsub.q a1, a2, a4 + fsub.q a1, a2, a4, rne + fsub.q a0, a1, a4 + fsub.q a0, a1, a4, rne + fsub.q a0, a2, a1 + fsub.q a0, a2, a1, rne + fmul.q a1, a2, a4 + fmul.q a1, a2, a4, rne + fmul.q a0, a1, a4 + fmul.q a0, a1, a4, rne + fmul.q a0, a2, a1 + fmul.q a0, a2, a1, rne + fdiv.q a1, a2, a4 + fdiv.q a1, a2, a4, rne + fdiv.q a0, a1, a4 + fdiv.q a0, a1, a4, rne + fdiv.q a0, a2, a1 + fdiv.q a0, a2, a1, rne + fsqrt.q a1, a2 + fsqrt.q a1, a2, rne + fsqrt.q a0, a1 + fsqrt.q a0, a1, rne + fmin.q a1, a2, a4 + fmin.q a0, a1, a4 + fmin.q a0, a2, a1 + fmax.q a1, a2, a4 + fmax.q a0, a1, a4 + fmax.q a0, a2, a1 + fmadd.q a1, a2, a4, a6 + fmadd.q a1, a2, a4, a6, rne + fmadd.q a0, a1, a4, a6 + fmadd.q a0, a1, a4, a6, rne + fmadd.q a0, a2, a1, a6 + fmadd.q a0, a2, a1, a6, rne + fmadd.q a0, a2, a4, a1 + fmadd.q a0, a2, a4, a1, rne + fnmadd.q a1, a2, a4, a6 + fnmadd.q a1, a2, a4, a6, rne + fnmadd.q a0, a1, a4, a6 + fnmadd.q a0, a1, a4, a6, rne + fnmadd.q a0, a2, a1, a6 + fnmadd.q a0, a2, a1, a6, rne + fnmadd.q a0, a2, a4, a1 + fnmadd.q a0, a2, a4, a1, rne + fmsub.q a1, a2, a4, a6 + fmsub.q a1, a2, a4, a6, rne + fmsub.q a0, a1, a4, a6 + fmsub.q a0, a1, a4, a6, rne + fmsub.q a0, a2, a1, a6 + fmsub.q a0, a2, a1, a6, rne + fmsub.q a0, a2, a4, a1 + fmsub.q a0, a2, a4, a1, rne + fnmsub.q a1, a2, a4, a6 + fnmsub.q a1, a2, a4, a6, rne + fnmsub.q a0, a1, a4, a6 + fnmsub.q a0, a1, a4, a6, rne + fnmsub.q a0, a2, a1, a6 + fnmsub.q a0, a2, a1, a6, rne + fnmsub.q a0, a2, a4, a1 + fnmsub.q a0, a2, a4, a1, rne + fsgnj.q a1, a2, a4 + fsgnj.q a0, a1, a4 + fsgnj.q a0, a2, a1 + fsgnjn.q a1, a2, a4 + fsgnjn.q a0, a1, a4 + fsgnjn.q a0, a2, a1 + fsgnjx.q a1, a2, a4 + fsgnjx.q a0, a1, a4 + fsgnjx.q a0, a2, a1 + fmv.q a1, a2 + fmv.q a0, a1 + fneg.q a1, a2 + fneg.q a0, a1 + fabs.q a1, a2 + fabs.q a0, a1 + # Compare instructions: destination is a GPR + feq.q a0, a1, a4 + feq.q a0, a2, a1 + flt.q a0, a1, a4 + flt.q a0, a2, a1 + fle.q a0, a1, a4 + fle.q a0, a2, a1 + fgt.q a0, a1, a4 + fgt.q a0, a2, a1 + fge.q a0, a1, a4 + fge.q a0, a2, a1 + # fclass instruction: destination is a GPR + fclass.q a0, a1 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.q a0, a1 + fcvt.w.q a0, a1, rne + fcvt.w.q a3, a1 + fcvt.w.q a3, a1, rne + fcvt.wu.q a0, a1 + fcvt.wu.q a0, a1, rne + fcvt.wu.q a3, a1 + fcvt.wu.q a3, a1, rne + fcvt.l.q a0, a1 + fcvt.l.q a0, a1, rne + fcvt.l.q a3, a1 + fcvt.l.q a3, a1, rne + fcvt.lu.q a0, a1 + fcvt.lu.q a0, a1, rne + fcvt.lu.q a3, a1 + fcvt.lu.q a3, a1, rne + fcvt.q.w a1, a2 + fcvt.q.w a1, a3 + fcvt.q.wu a1, a2 + fcvt.q.wu a1, a3 + fcvt.q.l a1, a2 + fcvt.q.l a1, a2, rne + fcvt.q.l a1, a3 + fcvt.q.l a1, a3, rne + fcvt.q.lu a1, a2 + fcvt.q.lu a1, a2, rne + fcvt.q.lu a1, a3 + fcvt.q.lu a1, a3, rne + # fcvt instructions (float-float; FP32/FP64 operand can be odd) + fcvt.s.q a0, a1 + fcvt.s.q a0, a1, rne + fcvt.s.q a3, a1 + fcvt.s.q a3, a1, rne + fcvt.d.q a0, a1 + fcvt.d.q a0, a1, rne + fcvt.d.q a3, a1 + fcvt.d.q a3, a1, rne + fcvt.q.s a1, a2 + fcvt.q.s a1, a3 + fcvt.q.d a1, a2 + fcvt.q.d a1, a3 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.d b/gas/testsuite/gas/riscv/zqinx-64-regpair.d new file mode 100644 index 00000000000..d62c17ffe46 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.d @@ -0,0 +1,87 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+06e67553[ ]+fadd.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+06e60553[ ]+fadd.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ee67553[ ]+fsub.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ee60553[ ]+fsub.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+16e67553[ ]+fmul.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+16e60553[ ]+fmul.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ee67553[ ]+fdiv.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ee60553[ ]+fdiv.q[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5e067553[ ]+fsqrt.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5e060553[ ]+fsqrt.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ee60553[ ]+fmin.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ee61553[ ]+fmax.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+86e67543[ ]+fmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60543[ ]+fmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754f[ ]+fnmadd.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054f[ ]+fnmadd.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e67547[ ]+fmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e60547[ ]+fmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+86e6754b[ ]+fnmsub.q[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+86e6054b[ ]+fnmsub.q[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+26e60553[ ]+fsgnj.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e61553[ ]+fsgnjn.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26e62553[ ]+fsgnjx.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+a6e62553[ ]+feq.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e625d3[ ]+feq.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e61553[ ]+flt.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e615d3[ ]+flt.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6e605d3[ ]+fle.q[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c715d3[ ]+flt.q[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2 +[ ]+[0-9a-f]+:[ ]+a6c705d3[ ]+fle.q[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e60615d3[ ]+fclass.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c6067553[ ]+fcvt.w.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6060553[ ]+fcvt.w.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c60675d3[ ]+fcvt.w.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c60605d3[ ]+fcvt.w.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c6167553[ ]+fcvt.wu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6160553[ ]+fcvt.wu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c61675d3[ ]+fcvt.wu.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c61605d3[ ]+fcvt.wu.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c6267553[ ]+fcvt.l.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6260553[ ]+fcvt.l.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c62675d3[ ]+fcvt.l.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c62605d3[ ]+fcvt.l.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+c6360553[ ]+fcvt.lu.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+c63675d3[ ]+fcvt.lu.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c63605d3[ ]+fcvt.lu.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d6260553[ ]+fcvt.q.l[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6267553[ ]+fcvt.q.l[ ]+a0,a2,dyn +[ ]+[0-9a-f]+:[ ]+d6258553[ ]+fcvt.q.l[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d625f553[ ]+fcvt.q.l[ ]+a0,a1,dyn +[ ]+[0-9a-f]+:[ ]+d6360553[ ]+fcvt.q.lu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6367553[ ]+fcvt.q.lu[ ]+a0,a2,dyn +[ ]+[0-9a-f]+:[ ]+d6358553[ ]+fcvt.q.lu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d635f553[ ]+fcvt.q.lu[ ]+a0,a1,dyn +[ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+40360553[ ]+fcvt.s.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+403675d3[ ]+fcvt.s.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+403605d3[ ]+fcvt.s.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+42360553[ ]+fcvt.d.q[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+423675d3[ ]+fcvt.d.q[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+423605d3[ ]+fcvt.d.q[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair.s b/gas/testsuite/gas/riscv/zqinx-64-regpair.s new file mode 100644 index 00000000000..abb6dbd9258 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair.s @@ -0,0 +1,84 @@ +target: + fadd.q a0, a2, a4 + fadd.q a0, a2, a4, rne + fsub.q a0, a2, a4 + fsub.q a0, a2, a4, rne + fmul.q a0, a2, a4 + fmul.q a0, a2, a4, rne + fdiv.q a0, a2, a4 + fdiv.q a0, a2, a4, rne + fsqrt.q a0, a2 + fsqrt.q a0, a2, rne + fmin.q a0, a2, a4 + fmax.q a0, a2, a4 + fmadd.q a0, a2, a4, a6 + fmadd.q a0, a2, a4, a6, rne + fnmadd.q a0, a2, a4, a6 + fnmadd.q a0, a2, a4, a6, rne + fmsub.q a0, a2, a4, a6 + fmsub.q a0, a2, a4, a6, rne + fnmsub.q a0, a2, a4, a6 + fnmsub.q a0, a2, a4, a6, rne + fsgnj.q a0, a2, a4 + fsgnjn.q a0, a2, a4 + fsgnjx.q a0, a2, a4 + fmv.q a0, a2 + fneg.q a0, a2 + fabs.q a0, a2 + # Compare instructions: destination is a GPR + feq.q a0, a2, a4 + feq.q a1, a2, a4 + flt.q a0, a2, a4 + flt.q a1, a2, a4 + fle.q a0, a2, a4 + fle.q a1, a2, a4 + fgt.q a0, a2, a4 + fgt.q a1, a2, a4 + fge.q a0, a2, a4 + fge.q a1, a2, a4 + # fclass instruction: destination is a GPR + fclass.q a0, a2 + fclass.q a1, a2 + # fcvt instructions (float-int or int-float; + # integer operand register can be odd) + fcvt.w.q a0, a2 + fcvt.w.q a0, a2, rne + fcvt.w.q a1, a2 + fcvt.w.q a1, a2, rne + fcvt.wu.q a0, a2 + fcvt.wu.q a0, a2, rne + fcvt.wu.q a1, a2 + fcvt.wu.q a1, a2, rne + fcvt.l.q a0, a2 + fcvt.l.q a0, a2, rne + fcvt.l.q a1, a2 + fcvt.l.q a1, a2, rne + fcvt.lu.q a0, a2 + fcvt.lu.q a0, a2, rne + fcvt.lu.q a1, a2 + fcvt.lu.q a1, a2, rne + fcvt.q.w a0, a2 + fcvt.q.w a0, a1 + fcvt.q.wu a0, a2 + fcvt.q.wu a0, a1 + fcvt.q.l a0, a2 + fcvt.q.l a0, a2, dyn + fcvt.q.l a0, a1 + fcvt.q.l a0, a1, dyn + fcvt.q.lu a0, a2 + fcvt.q.lu a0, a2, dyn + fcvt.q.lu a0, a1 + fcvt.q.lu a0, a1, dyn + # fcvt instructions (float-float; FP32/FP64 operand can be odd) + fcvt.s.q a0, a2 + fcvt.s.q a0, a2, rne + fcvt.s.q a1, a2 + fcvt.s.q a1, a2, rne + fcvt.d.q a0, a2 + fcvt.d.q a0, a2, rne + fcvt.d.q a1, a2 + fcvt.d.q a1, a2, rne + fcvt.q.s a0, a2 + fcvt.q.s a0, a1 + fcvt.q.d a0, a2 + fcvt.q.d a0, a1 diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f1dabeaab8e..db881831ff9 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -369,8 +369,10 @@ enum riscv_insn_class INSN_CLASS_ZIHINTPAUSE, INSN_CLASS_ZMMUL, INSN_CLASS_F_OR_ZFINX, - INSN_CLASS_D_OR_ZDINX, - INSN_CLASS_Q_OR_ZQINX, + INSN_CLASS_D_OR_ZDINX, /* Diagnostics only. */ + INSN_CLASS_Q_OR_ZQINX, /* Diagnostics only. */ + INSN_CLASS_ZDINX, + INSN_CLASS_ZQINX, INSN_CLASS_ZFH_OR_ZHINX, INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, @@ -468,6 +470,10 @@ struct riscv_opcode #define INSN_8_BYTE 0x00000040 #define INSN_16_BYTE 0x00000050 +/* Instruction has different entry that shares the name but differs + in register operands (FPR or GPR) used. */ +#define INSN_F_OR_X 0x00000080 + /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ #define INSN_MACRO 0xffffffff diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index fda2fb8d68a..f2d8dacbf89 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -109,6 +109,7 @@ const char * const riscv_vma[2] = #define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1) #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2) +#define MASK_RS3 (OP_MASK_RS3 << OP_SH_RS3) #define MASK_RD (OP_MASK_RD << OP_SH_RD) #define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2) #define MASK_IMM ENCODE_ITYPE_IMM (-1U) @@ -266,6 +267,146 @@ match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op, return match_opcode (op, insn) && vd == vs1 && vs1 == vs2; } +/* Functions below are used for Zdinx/Zqinx instructions. */ + +static int +match_opcode_zdinx_rtype_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rd % 2 == 0) + && (rs1 % 2 == 0) && (rs2 % 2 == 0); +} + +static int +match_opcode_zdinx_rtype_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rd % 4 == 0) + && (rs1 % 4 == 0) && (rs2 % 4 == 0); +} + +static int +match_rs1_eq_rs2_zdinx_rtype_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_rs1_eq_rs2 (op, insn) && (rd % 2 == 0) && (rs1 % 2 == 0); +} + +static int +match_rs1_eq_rs2_zdinx_rtype_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_rs1_eq_rs2 (op, insn) && (rd % 4 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_r4type_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + int rs3 = (insn & MASK_RS3) >> OP_SH_RS3; + return match_opcode (op, insn) && (rd % 2 == 0) + && (rs1 % 2 == 0) && (rs2 % 2 == 0) && (rs3 % 2 == 0); +} + +static int +match_opcode_zdinx_r4type_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + int rs3 = (insn & MASK_RS3) >> OP_SH_RS3; + return match_opcode (op, insn) && (rd % 4 == 0) + & (rs1 % 4 == 0) && (rs2 % 4 == 0) && (rs3 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g1_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 1 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g1_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 1 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g2_1 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 1 == 0); +} + +static int +match_opcode_zdinx_itype_g2_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g2_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 2 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_itype_g4_1 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 1 == 0); +} + +static int +match_opcode_zdinx_itype_g4_2 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 2 == 0); +} + +static int +match_opcode_zdinx_itype_g4_4 (const struct riscv_opcode *op, insn_t insn) +{ + int rd = (insn & MASK_RD) >> OP_SH_RD; + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + return match_opcode (op, insn) && (rd % 4 == 0) && (rs1 % 4 == 0); +} + +static int +match_opcode_zdinx_cmp_g2 (const struct riscv_opcode *op, insn_t insn) +{ + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rs1 % 2 == 0) && (rs2 % 2 == 0); +} + +static int +match_opcode_zdinx_cmp_g4 (const struct riscv_opcode *op, insn_t insn) +{ + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && (rs1 % 4 == 0) && (rs2 % 4 == 0); +} + const struct riscv_opcode riscv_opcodes[] = { /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ @@ -715,7 +856,9 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 }, {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, -/* Double-precision floating-point instruction subset. */ +/* Double-precision floating-point instruction subset. + Zdinx instructions must be defined per xlen. D/Zdinx instructions that + share the name must have INSN_F_OR_X flag. */ {"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, @@ -724,115 +867,303 @@ const struct riscv_opcode riscv_opcodes[] = {"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, -{"fsgnjn.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, -{"fsgnjx.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, -{"fmin.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, -{"fmax.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, -{"fcvt.d.w", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, -{"fcvt.d.wu", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.s", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, -{"fclass.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, -{"feq.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, -{"flt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fle.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, -{"fgt.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fge.d", 0, INSN_CLASS_D_OR_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 32, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.d", 64, INSN_CLASS_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fsgnj.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_F_OR_X }, +{"fsgnj.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnj.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_F_OR_X }, +{"fsgnjn.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_F_OR_X }, +{"fsgnjn.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjn.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_F_OR_X }, +{"fsgnjx.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_F_OR_X }, +{"fsgnjx.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjx.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_F_OR_X }, +{"fadd.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_F_OR_X }, +{"fadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_F_OR_X }, +{"fsub.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_F_OR_X }, +{"fsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_F_OR_X }, +{"fmul.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_F_OR_X }, +{"fmul.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_F_OR_X }, +{"fdiv.d", 32, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.d", 64, INSN_CLASS_ZDINX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 0, INSN_CLASS_D, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.d", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_F_OR_X }, +{"fsqrt.d", 32, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.d", 64, INSN_CLASS_ZDINX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_F_OR_X }, +{"fmin.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_F_OR_X }, +{"fmin.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmin.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_F_OR_X }, +{"fmax.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_F_OR_X }, +{"fmax.d", 32, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmax.d", 64, INSN_CLASS_ZDINX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_F_OR_X }, +{"fmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_F_OR_X }, +{"fnmadd.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_F_OR_X }, +{"fmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_F_OR_X }, +{"fnmsub.d", 32, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.d", 64, INSN_CLASS_ZDINX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_F_OR_X }, +{"fcvt.w.d", 32, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.d", 32, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.d.w", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.w", 32, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.w", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.wu", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.wu", 32, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.wu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.s", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.s", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.d.s", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 32, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.d", 64, INSN_CLASS_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_F_OR_X }, +{"fcvt.s.d", 32, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.d", 64, INSN_CLASS_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_F_OR_X }, +{"fclass.d", 0, INSN_CLASS_D, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_F_OR_X }, +{"fclass.d", 32, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fclass.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_F_OR_X }, +{"feq.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_F_OR_X }, +{"feq.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"feq.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_F_OR_X }, +{"flt.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"flt.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"flt.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fle.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fle.d", 32, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fle.d", 64, INSN_CLASS_ZDINX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fgt.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fgt.d", 32, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fgt.d", 64, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_F_OR_X }, +{"fge.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, +{"fge.d", 32, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fge.d", 64, INSN_CLASS_ZDINX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_F_OR_X }, {"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, {"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, - -/* Quad-precision floating-point instruction subset. */ +{"fcvt.l.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, INSN_F_OR_X }, +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, INSN_F_OR_X }, +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, INSN_F_OR_X }, +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, INSN_F_OR_X }, + +/* Quad-precision floating-point instruction subset. + Zqinx instructions must be defined per xlen. Q/Zqinx instructions that + share the name must have INSN_F_OR_X flag. */ {"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -{"fsgnjn.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, -{"fsgnjx.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, -{"fmin.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, -{"fmax.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, -{"fcvt.q.w", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, -{"fcvt.q.wu", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.s", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, -{"fcvt.q.d", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, -{"fclass.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, -{"feq.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, -{"flt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fle.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fgt.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fge.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, +{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fmv.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fneg.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 32, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2_zdinx_rtype_g4, INSN_ALIAS|INSN_F_OR_X }, +{"fabs.q", 64, INSN_CLASS_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2_zdinx_rtype_g2, INSN_ALIAS|INSN_F_OR_X }, +{"fsgnj.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, INSN_F_OR_X }, +{"fsgnj.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnj.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjn.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, INSN_F_OR_X }, +{"fsgnjn.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnjn.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsgnjx.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, INSN_F_OR_X }, +{"fsgnjx.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsgnjx.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fadd.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fadd.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fadd.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, INSN_F_OR_X }, +{"fadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsub.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsub.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsub.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, INSN_F_OR_X }, +{"fsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmul.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmul.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmul.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, INSN_F_OR_X }, +{"fmul.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmul.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fdiv.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fdiv.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fdiv.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, INSN_F_OR_X }, +{"fdiv.q", 32, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fdiv.q", 64, INSN_CLASS_ZQINX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fsqrt.q", 0, INSN_CLASS_Q, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fsqrt.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode_zdinx_itype_g4_4, INSN_F_OR_X }, +{"fsqrt.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fsqrt.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, INSN_F_OR_X }, +{"fsqrt.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode_zdinx_itype_g4_4, INSN_F_OR_X }, +{"fsqrt.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode_zdinx_itype_g2_2, INSN_F_OR_X }, +{"fmin.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, INSN_F_OR_X }, +{"fmin.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmin.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmax.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, INSN_F_OR_X }, +{"fmax.q", 32, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode_zdinx_rtype_g4, INSN_F_OR_X }, +{"fmax.q", 64, INSN_CLASS_ZQINX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode_zdinx_rtype_g2, INSN_F_OR_X }, +{"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, INSN_F_OR_X }, +{"fmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, INSN_F_OR_X }, +{"fnmadd.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmadd.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, INSN_F_OR_X }, +{"fmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fnmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, INSN_F_OR_X }, +{"fnmsub.q", 32, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode_zdinx_r4type_g4, INSN_F_OR_X }, +{"fnmsub.q", 64, INSN_CLASS_ZQINX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode_zdinx_r4type_g2, INSN_F_OR_X }, +{"fcvt.w.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.w.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.w.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.w.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.w.q", 32, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.w.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.wu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.wu.q", 32, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.wu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.q.w", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.w", 32, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.w", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.wu", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.wu", 32, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.wu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.s", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.s", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode_zdinx_itype_g4_1, INSN_F_OR_X }, +{"fcvt.q.s", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.d", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.d", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode_zdinx_itype_g4_2, INSN_F_OR_X }, +{"fcvt.q.d", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.s.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.s.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.s.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.s.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.s.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fcvt.s.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.d.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.d.q", 32, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode_zdinx_itype_g2_4, INSN_F_OR_X }, +{"fcvt.d.q", 64, INSN_CLASS_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.d.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.d.q", 32, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode_zdinx_itype_g2_4, INSN_F_OR_X }, +{"fcvt.d.q", 64, INSN_CLASS_ZQINX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fclass.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, INSN_F_OR_X }, +{"fclass.q", 32, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode_zdinx_itype_g1_4, INSN_F_OR_X }, +{"fclass.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"feq.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, INSN_F_OR_X }, +{"feq.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"feq.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"flt.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_F_OR_X }, +{"flt.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"flt.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fle.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_F_OR_X }, +{"fle.q", 32, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fle.q", 64, INSN_CLASS_ZQINX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fgt.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_F_OR_X }, +{"fgt.q", 32, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fgt.q", 64, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fge.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_F_OR_X }, +{"fge.q", 32, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g4, INSN_F_OR_X }, +{"fge.q", 64, INSN_CLASS_ZQINX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode_zdinx_cmp_g2, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, INSN_F_OR_X }, +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode_zdinx_itype_g1_2, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, INSN_F_OR_X }, +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, INSN_F_OR_X }, +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode_zdinx_itype_g2_1, INSN_F_OR_X }, /* Compressed instructions. */ {"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, 0 }, -- 2.34.1