From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 498FC3858D33 for ; Thu, 23 May 2024 15:15:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 498FC3858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 498FC3858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716477337; cv=none; b=JFPbgJCU9/I5GFi4VvQa/gNZWj4sRIX8DorMZCjV7QJnhMy0ovU3ENu9L1lXLvL4I/iPzEf2upJDxijJYMLW2CoLx45wW2ARtJIHyRkNhwFz6du2pWKlNpqey13MFXTqrGvhUTZxyaRSuDAA1sgHbWA/M+IGPqzLU77rZYoLMvg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716477337; c=relaxed/simple; bh=WhR6u9r+GCePqZW0GmKBq/oWD4U8zIlL3ETdV34KG5k=; h=Message-ID:Date:MIME-Version:Subject:To:From; b=sArXCVKjoUaOeQsQwU5UifXSHIYYRDYCjVJopm19+bmi2SieOidoE24j9xWL6+xS0PYc3V5cyQw7DH/+5F4oEkjbhYz7rqThyXoitNBXURR7xz1p6JGHYosWsb8qqHFPCCZdVafvbTpLZ2tuYx+q2PdvoC3kk+Kkd1lRp8XCa2M= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EFB5B339; Thu, 23 May 2024 08:15:58 -0700 (PDT) Received: from [10.2.78.57] (e120077-lin.cambridge.arm.com [10.2.78.57]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6C1EA3F766; Thu, 23 May 2024 08:15:34 -0700 (PDT) Message-ID: <47761b43-d0a7-4dcf-92a4-9f764d055f3c@arm.com> Date: Thu, 23 May 2024 16:15:33 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 1/4] gas, aarch64: Add AdvSIMD lut extension To: Saurabh Jha , binutils@sourceware.org References: <20240523135020.2492458-1-saujha01@e130340.arm.com> From: "Richard Earnshaw (lists)" Content-Language: en-GB In-Reply-To: <20240523135020.2492458-1-saujha01@e130340.arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3491.3 required=5.0 tests=BAYES_00,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 23/05/2024 14:50, Saurabh Jha wrote: > > Introduces instructions for the Advanced SIMD lut extension for AArch64. They are documented in the following links: > * luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en > * luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en > > These instructions needed definition of some new operands. We will first > discuss operands for the third operand of the instructions and then > discuss a vector register list operand needed for the second operand. > > The third operands are vectors with bit indices and without type > qualifiers. They are called Em_INDEX1_14, Em_INDEX2_13, and Em_INDEX3_12 > and they have 1 bit, 2 bit, and 3 bit indices respectively. For these > new operands, we defined new parsing case branch and a new instruction > class. The lsb and width of these operands are the same as many existing > but the convention is to give different names to fields that serve > different purpose so we introduced new fields in aarch64-opc.c and > aarch64-opc.h for these new operands. > > For the second operand of these instructions, we introduced a new > operand called LVn_LUT. This represents a vector register list with > stride 1. We defined new inserter and extractor for this new operand and > it is encoded in FLD_Rn. We are enforcing the number of registers in the > reglist using opcode flag rather than operand flag as this is what other > SIMD vector register list operands are doing. The disassembly also uses > opcode flag to print the correct number of registers. > --- > Hi, > > Regression tested for aarch64-none-elf and found no regressions. > > Ok for binutils-master? I don't have commit access so can someone please commit on my behalf? I was about to apply this when I realized that you haven't added anything to the manual or the NEWS file as we could customarily do for a new feature. Could you update the patch for that please? R. > > Regards, > Saurabh > --- > gas/config/tc-aarch64.c | 67 ++++++ > gas/testsuite/gas/aarch64/advsimd-lut-bad.d | 3 + > gas/testsuite/gas/aarch64/advsimd-lut-bad.l | 25 +++ > .../gas/aarch64/advsimd-lut-illegal.d | 3 + > .../gas/aarch64/advsimd-lut-illegal.l | 208 ++++++++++++++++++ > .../gas/aarch64/advsimd-lut-illegal.s | 128 +++++++++++ > gas/testsuite/gas/aarch64/advsimd-lut.d | 32 +++ > gas/testsuite/gas/aarch64/advsimd-lut.s | 29 +++ > include/opcode/aarch64.h | 9 +- > opcodes/aarch64-asm.c | 32 +++ > opcodes/aarch64-asm.h | 1 + > opcodes/aarch64-dis.c | 15 ++ > opcodes/aarch64-dis.h | 1 + > opcodes/aarch64-opc.c | 23 ++ > opcodes/aarch64-opc.h | 2 + > opcodes/aarch64-tbl.h | 38 +++- > 16 files changed, 614 insertions(+), 2 deletions(-) > create mode 100644 gas/testsuite/gas/aarch64/advsimd-lut-bad.d > create mode 100644 gas/testsuite/gas/aarch64/advsimd-lut-bad.l > create mode 100644 gas/testsuite/gas/aarch64/advsimd-lut-illegal.d > create mode 100644 gas/testsuite/gas/aarch64/advsimd-lut-illegal.l > create mode 100644 gas/testsuite/gas/aarch64/advsimd-lut-illegal.s > create mode 100644 gas/testsuite/gas/aarch64/advsimd-lut.d > create mode 100644 gas/testsuite/gas/aarch64/advsimd-lut.s >