From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 2A0A4384230A for ; Fri, 18 Nov 2022 07:44:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2A0A4384230A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id D6E0F300089; Fri, 18 Nov 2022 07:44:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1668757467; bh=UohoRCYj4eI7mGi3wz1O2147VlasBDIrIlOuNxmK6GQ=; h=Message-ID:Date:Mime-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type:Content-Transfer-Encoding; b=JL+FW51i25uVQ4y0FR4yHQHWHi0AO/gm+YZ1nawYZriOWpElAmPKpFajYm6c/uFVd fN56gwlIPbafo6wOIpKTDJSTh8AQ8/hoOS0myU2aYyuwrHfrqvRUOFylnktlRZe2Ex 4PnuCPJCSowwv48a5eiPPYJE2Vaek9tYFXHB/QMs= Message-ID: <486f80ee-d1c8-1104-ca8b-4f2c06c59961@irq.a4lg.com> Date: Fri, 18 Nov 2022 16:44:23 +0900 Mime-Version: 1.0 Subject: Re: [PATCH] RISC-V: Add INSN_DREF to memory read/write instructions Content-Language: en-US To: =?UTF-8?Q?Christoph_M=c3=bcllner?= , Nelson Chu Cc: Lifang Xia , Kito Cheng , Palmer Dabbelt , Binutils References: <4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com> From: Tsukasa OI In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP,UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 2022/11/18 16:25, Christoph Müllner wrote: > > > On Fri, Nov 18, 2022 at 3:18 AM Nelson Chu > wrote: > > LGTM, but I think we must get the approvals from Lifang and Christoph. > > > Ack. > I've also reviewed the size flags. > > However, I am not sure I understand the purpose of these flags. > I can't find any use of them in the repo. > Also, there are no tests for these flags. > Can you shed some light on this? > > Thanks, > Christoph It seems this is for generic libopcodes interface and no one in Binutils/GDB uses this (on data reference instructions). This is purely for custom libopcodes users (outside Binutils/GDB). Making new tests for this will get... to say the least, difficult (because I could not find any similar tests). This patch is better for consistency but TBH, I cannot find a good use of this either. Hmm... how can I do with this? Thanks, Tsukasa >   > > > Thanks > Nelson > > On Fri, Nov 18, 2022 at 10:02 AM Tsukasa OI > > > wrote: > > > > From: Tsukasa OI > > > > > From: Tsukasa OI > > > > > This commit adds INSN_DREF flag (and size-related flags) to > instruction > > which reads/writes the memory directly.  It however excludes > cache-related > > instructions that does synchronization with other cores but otherwise > > does not touch the contents of the memory. > > > > INSN_DREF and size flags are added to following instructions: > > > > -   "cbo.zero" > > -   All instructions from following custom extensions: > >     -   XTheadFMemIdx > >     -   XTheadInt > >     -   XTheadMemIdx > >     -   XTheadMemPair > > > > opcodes/ChangeLog: > > > >         * riscv-opc.c (riscv_opcodes): Add INSN_DREF and size > flags on the > >         instructions directly reads/writes memory. > > --- > >  opcodes/riscv-opc.c | 124 > ++++++++++++++++++++++---------------------- > >  1 file changed, 62 insertions(+), 62 deletions(-) > > > > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > > index 0e691544f9bc..5a6f98421512 100644 > > --- a/opcodes/riscv-opc.c > > +++ b/opcodes/riscv-opc.c > > @@ -933,7 +933,7 @@ const struct riscv_opcode riscv_opcodes[] = > >  {"cbo.clean",  0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_CLEAN, > MASK_CBO_CLEAN, match_opcode, 0 }, > >  {"cbo.flush",  0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_FLUSH, > MASK_CBO_FLUSH, match_opcode, 0 }, > >  {"cbo.inval",  0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, > MASK_CBO_INVAL, match_opcode, 0 }, > > -{"cbo.zero",   0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, > MASK_CBO_ZERO, match_opcode, 0 }, > > +{"cbo.zero",   0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, > MASK_CBO_ZERO, match_opcode, INSN_DREF }, > > > >  /* Zawrs instructions.  */ > >  {"wrs.nto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, > MASK_WRS_NTO, match_opcode, 0 }, > > @@ -1922,77 +1922,77 @@ const struct riscv_opcode riscv_opcodes[] = > >  {"th.mvnez",         0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", > MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0}, > > > >  /* Vendor-specific (T-Head) XTheadFMemIdx instructions.  */ > > -{"th.flrd",    0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FLRD,  MASK_TH_FLRD,  match_opcode, 0}, > > -{"th.flrw",    0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FLRW,  MASK_TH_FLRW,  match_opcode, 0}, > > -{"th.flurd",   0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, 0}, > > -{"th.flurw",   0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, 0}, > > -{"th.fsrd",    0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FSRD,  MASK_TH_FSRD,  match_opcode, 0}, > > -{"th.fsrw",    0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FSRW,  MASK_TH_FSRW,  match_opcode, 0}, > > -{"th.fsurd",   0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0}, > > -{"th.fsurw",   0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0}, > > +{"th.flrd",    0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FLRD,  MASK_TH_FLRD,  match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.flrw",    0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FLRW,  MASK_TH_FLRW,  match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.flurd",   0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.flurw",   0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.fsrd",    0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FSRD,  MASK_TH_FSRD,  match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.fsrw",    0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FSRW,  MASK_TH_FSRW,  match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.fsurd",   0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.fsurw",   0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, INSN_DREF|INSN_4_BYTE }, > > > >  /* Vendor-specific (T-Head) XTheadFmv instructions.  */ > >  {"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", > MATCH_TH_FMV_HW_X,  MASK_TH_FMV_HW_X,  match_opcode, 0}, > >  {"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", > MATCH_TH_FMV_X_HW,  MASK_TH_FMV_X_HW,  match_opcode, 0}, > > > >  /* Vendor-specific (T-Head) XTheadInt instructions.  */ > > -{"th.ipop",  0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPOP,  > MASK_TH_IPOP,  match_opcode, 0}, > > -{"th.ipush", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPUSH, > MASK_TH_IPUSH, match_opcode, 0}, > > +{"th.ipop",  0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPOP,  > MASK_TH_IPOP,  match_opcode, INSN_DREF }, > > +{"th.ipush", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPUSH, > MASK_TH_IPUSH, match_opcode, INSN_DREF }, > > > >  /* Vendor-specific (T-Head) XTheadMemIdx instructions.  */ > > -{"th.ldia",  64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LDIA,  MASK_TH_LDIA,  match_th_load_inc, 0}, > > -{"th.ldib",  64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LDIB,  MASK_TH_LDIB,  match_th_load_inc, 0}, > > -{"th.lwia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LWIA,  MASK_TH_LWIA,  match_th_load_inc, 0}, > > -{"th.lwib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LWIB,  MASK_TH_LWIB,  match_th_load_inc, 0}, > > -{"th.lwuia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LWUIA, MASK_TH_LWUIA, match_th_load_inc, 0}, > > -{"th.lwuib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LWUIB, MASK_TH_LWUIB, match_th_load_inc, 0}, > > -{"th.lhia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LHIA,  MASK_TH_LHIA,  match_th_load_inc, 0}, > > -{"th.lhib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LHIB,  MASK_TH_LHIB,  match_th_load_inc, 0}, > > -{"th.lhuia",  0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LHUIA, MASK_TH_LHUIA, match_th_load_inc, 0}, > > -{"th.lhuib",  0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LHUIB, MASK_TH_LHUIB, match_th_load_inc, 0}, > > -{"th.lbia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LBIA,  MASK_TH_LBIA,  match_th_load_inc, 0}, > > -{"th.lbib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LBIB,  MASK_TH_LBIB,  match_th_load_inc, 0}, > > -{"th.lbuia",  0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LBUIA, MASK_TH_LBUIA, match_th_load_inc, 0}, > > -{"th.lbuib",  0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LBUIB, MASK_TH_LBUIB, match_th_load_inc, 0}, > > -{"th.sdia",  64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SDIA, MASK_TH_SDIA, match_opcode, 0}, > > -{"th.sdib",  64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SDIB, MASK_TH_SDIB, match_opcode, 0}, > > -{"th.swia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SWIA, MASK_TH_SWIA, match_opcode, 0}, > > -{"th.swib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SWIB, MASK_TH_SWIB, match_opcode, 0}, > > -{"th.shia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SHIA, MASK_TH_SHIA, match_opcode, 0}, > > -{"th.shib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SHIB, MASK_TH_SHIB, match_opcode, 0}, > > -{"th.sbia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SBIA, MASK_TH_SBIA, match_opcode, 0}, > > -{"th.sbib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SBIB, MASK_TH_SBIB, match_opcode, 0}, > > - > > -{"th.lrd",  64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRD,  MASK_TH_LRD,  match_opcode, 0}, > > -{"th.lrw",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRW,  MASK_TH_LRW,  match_opcode, 0}, > > -{"th.lrwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRWU, MASK_TH_LRWU, match_opcode, 0}, > > -{"th.lrh",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRH,  MASK_TH_LRH,  match_opcode, 0}, > > -{"th.lrhu",  0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRHU, MASK_TH_LRHU, match_opcode, 0}, > > -{"th.lrb",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRB,  MASK_TH_LRB,  match_opcode, 0}, > > -{"th.lrbu",  0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRBU, MASK_TH_LRBU, match_opcode, 0}, > > -{"th.srd",  64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SRD,  MASK_TH_SRD, match_opcode, 0}, > > -{"th.srw",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SRW,  MASK_TH_SRW, match_opcode, 0}, > > -{"th.srh",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SRH,  MASK_TH_SRH, match_opcode, 0}, > > -{"th.srb",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SRB,  MASK_TH_SRB, match_opcode, 0}, > > - > > -{"th.lurd",  64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURD,  MASK_TH_LURD,  match_opcode, 0}, > > -{"th.lurw",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURW,  MASK_TH_LURW,  match_opcode, 0}, > > -{"th.lurwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURWU, MASK_TH_LURWU, match_opcode, 0}, > > -{"th.lurh",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURH,  MASK_TH_LURH,  match_opcode, 0}, > > -{"th.lurhu",  0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURHU, MASK_TH_LURHU, match_opcode, 0}, > > -{"th.lurb",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURB,  MASK_TH_LURB,  match_opcode, 0}, > > -{"th.lurbu",  0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURBU, MASK_TH_LURBU, match_opcode, 0}, > > -{"th.surd",  64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SURD,  MASK_TH_SURD, match_opcode, 0}, > > -{"th.surw",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SURW,  MASK_TH_SURW, match_opcode, 0}, > > -{"th.surh",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SURH,  MASK_TH_SURH, match_opcode, 0}, > > -{"th.surb",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SURB,  MASK_TH_SURB, match_opcode, 0}, > > +{"th.ldia",  64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LDIA,  MASK_TH_LDIA,  match_th_load_inc, > INSN_DREF|INSN_8_BYTE }, > > +{"th.ldib",  64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LDIB,  MASK_TH_LDIB,  match_th_load_inc, > INSN_DREF|INSN_8_BYTE }, > > +{"th.lwia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LWIA,  MASK_TH_LWIA,  match_th_load_inc, > INSN_DREF|INSN_4_BYTE }, > > +{"th.lwib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LWIB,  MASK_TH_LWIB,  match_th_load_inc, > INSN_DREF|INSN_4_BYTE }, > > +{"th.lwuia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LWUIA, MASK_TH_LWUIA, match_th_load_inc, > INSN_DREF|INSN_4_BYTE }, > > +{"th.lwuib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LWUIB, MASK_TH_LWUIB, match_th_load_inc, > INSN_DREF|INSN_4_BYTE }, > > +{"th.lhia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LHIA,  MASK_TH_LHIA,  match_th_load_inc, > INSN_DREF|INSN_2_BYTE }, > > +{"th.lhib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LHIB,  MASK_TH_LHIB,  match_th_load_inc, > INSN_DREF|INSN_2_BYTE }, > > +{"th.lhuia",  0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LHUIA, MASK_TH_LHUIA, match_th_load_inc, > INSN_DREF|INSN_2_BYTE }, > > +{"th.lhuib",  0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LHUIB, MASK_TH_LHUIB, match_th_load_inc, > INSN_DREF|INSN_2_BYTE }, > > +{"th.lbia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LBIA,  MASK_TH_LBIA,  match_th_load_inc, > INSN_DREF|INSN_1_BYTE }, > > +{"th.lbib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LBIB,  MASK_TH_LBIB,  match_th_load_inc, > INSN_DREF|INSN_1_BYTE }, > > +{"th.lbuia",  0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LBUIA, MASK_TH_LBUIA, match_th_load_inc, > INSN_DREF|INSN_1_BYTE }, > > +{"th.lbuib",  0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LBUIB, MASK_TH_LBUIB, match_th_load_inc, > INSN_DREF|INSN_1_BYTE }, > > +{"th.sdia",  64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SDIA, MASK_TH_SDIA, match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.sdib",  64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SDIB, MASK_TH_SDIB, match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.swia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SWIA, MASK_TH_SWIA, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.swib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SWIB, MASK_TH_SWIB, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.shia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SHIA, MASK_TH_SHIA, match_opcode, INSN_DREF|INSN_2_BYTE }, > > +{"th.shib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SHIB, MASK_TH_SHIB, match_opcode, INSN_DREF|INSN_2_BYTE }, > > +{"th.sbia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SBIA, MASK_TH_SBIA, match_opcode, INSN_DREF|INSN_1_BYTE }, > > +{"th.sbib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SBIB, MASK_TH_SBIB, match_opcode, INSN_DREF|INSN_1_BYTE }, > > + > > +{"th.lrd",  64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRD,  MASK_TH_LRD,  match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.lrw",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRW,  MASK_TH_LRW,  match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.lrwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRWU, MASK_TH_LRWU, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.lrh",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRH,  MASK_TH_LRH,  match_opcode, INSN_DREF|INSN_2_BYTE }, > > +{"th.lrhu",  0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRHU, MASK_TH_LRHU, match_opcode, INSN_DREF|INSN_2_BYTE }, > > +{"th.lrb",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRB,  MASK_TH_LRB,  match_opcode, INSN_DREF|INSN_1_BYTE }, > > +{"th.lrbu",  0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRBU, MASK_TH_LRBU, match_opcode, INSN_DREF|INSN_1_BYTE }, > > +{"th.srd",  64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SRD,  MASK_TH_SRD, match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.srw",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SRW,  MASK_TH_SRW, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.srh",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SRH,  MASK_TH_SRH, match_opcode, INSN_DREF|INSN_2_BYTE }, > > +{"th.srb",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SRB,  MASK_TH_SRB, match_opcode, INSN_DREF|INSN_1_BYTE }, > > + > > +{"th.lurd",  64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURD,  MASK_TH_LURD,  match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.lurw",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURW,  MASK_TH_LURW,  match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.lurwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURWU, MASK_TH_LURWU, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.lurh",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURH,  MASK_TH_LURH,  match_opcode, INSN_DREF|INSN_2_BYTE }, > > +{"th.lurhu",  0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURHU, MASK_TH_LURHU, match_opcode, INSN_DREF|INSN_2_BYTE }, > > +{"th.lurb",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURB,  MASK_TH_LURB,  match_opcode, INSN_DREF|INSN_1_BYTE }, > > +{"th.lurbu",  0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURBU, MASK_TH_LURBU, match_opcode, INSN_DREF|INSN_1_BYTE }, > > +{"th.surd",  64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SURD,  MASK_TH_SURD, match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.surw",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SURW,  MASK_TH_SURW, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.surh",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SURH,  MASK_TH_SURH, match_opcode, INSN_DREF|INSN_2_BYTE }, > > +{"th.surb",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SURB,  MASK_TH_SURB, match_opcode, INSN_DREF|INSN_1_BYTE }, > > > >  /* Vendor-specific (T-Head) XTheadMemPair instructions.  */ > > -{"th.ldd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl4", > MATCH_TH_LDD,  MASK_TH_LDD,  match_th_load_pair, 0}, > > -{"th.lwd",  0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", > MATCH_TH_LWD,  MASK_TH_LWD,  match_th_load_pair, 0}, > > -{"th.lwud", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", > MATCH_TH_LWUD, MASK_TH_LWUD, match_th_load_pair, 0}, > > -{"th.sdd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl4", > MATCH_TH_SDD,  MASK_TH_SDD,  match_opcode, 0}, > > -{"th.swd",  0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", > MATCH_TH_SWD,  MASK_TH_SWD,  match_opcode, 0}, > > +{"th.ldd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl4", > MATCH_TH_LDD,  MASK_TH_LDD,  match_th_load_pair, > INSN_DREF|INSN_16_BYTE }, > > +{"th.lwd",  0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", > MATCH_TH_LWD,  MASK_TH_LWD,  match_th_load_pair, > INSN_DREF|INSN_8_BYTE }, > > +{"th.lwud", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", > MATCH_TH_LWUD, MASK_TH_LWUD, match_th_load_pair, > INSN_DREF|INSN_8_BYTE }, > > +{"th.sdd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl4", > MATCH_TH_SDD,  MASK_TH_SDD,  match_opcode, INSN_DREF|INSN_16_BYTE }, > > +{"th.swd",  0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", > MATCH_TH_SWD,  MASK_TH_SWD,  match_opcode, INSN_DREF|INSN_8_BYTE }, > > > >  /* Vendor-specific (T-Head) XTheadMac instructions.  */ > >  {"th.mula",          0, INSN_CLASS_XTHEADMAC, "d,s,t", > MATCH_TH_MULA,  MASK_TH_MULA,  match_opcode, 0}, > > > > base-commit: 9c93bc90d577ac191ec94503e04cdcf87a3d2a1a > > -- > > 2.38.1 > > >