[PATCH] Fix reduce/reduce conflicts in Blackfin gas

[PATCH] Fix reduce/reduce conflicts in Blackfin gas

[Jie Zhang]

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I committed this patch to fix the following two reduce/reduce conflicts:

    92 asm_1: HALF_REG ASSIGN HALF_REG LESS_LESS expr .
    93      | HALF_REG ASSIGN HALF_REG LESS_LESS expr . smod

     DOUBLE_BAR  reduce using rule 92 (asm_1)
     DOUBLE_BAR  [reduce using rule 260 (smod)]
     SEMICOLON   reduce using rule 92 (asm_1)
     SEMICOLON   [reduce using rule 260 (smod)]


Jie

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	* config/bfin-parse.y (asm_1): Fix reduce/reduce conflicts.

Index: config/bfin-parse.y
===================================================================
--- config/bfin-parse.y	(revision 2892)
+++ config/bfin-parse.y	(working copy)
@@ -1939,22 +1939,20 @@ asm_1:   
 	  else
 	    return yyerror ("Bad shift value or register");
 	}
-	| HALF_REG ASSIGN HALF_REG LESS_LESS expr
-	{
-	  if (IS_UIMM ($5, 4))
-	    {
-	      notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
-	      $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
-	    }
-	  else
-	    return yyerror ("Bad shift value");
-	}
 	| HALF_REG ASSIGN HALF_REG LESS_LESS expr smod 
 	{
 	  if (IS_UIMM ($5, 4))
 	    {
-	      notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
-	      $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
+	      if ($6.s0)
+		{
+		  notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n");
+		  $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
+		}
+	      else
+		{
+		  notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
+		  $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
+		}
 	    }
 	  else
 	    return yyerror ("Bad shift value");