From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <research_trasio@irq.a4lg.com>
Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154])
 by sourceware.org (Postfix) with ESMTPS id CE2FC3858C2C
 for <binutils@sourceware.org>; Wed,  5 Jan 2022 03:17:33 +0000 (GMT)
DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CE2FC3858C2C
Received: by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 4C3A0300089;
 Wed,  5 Jan 2022 03:17:31 +0000 (UTC)
Message-ID: <4a09329f-4db8-ae0f-b93a-93d452d6170e@irq.a4lg.com>
Date: Wed, 5 Jan 2022 12:17:29 +0900
Mime-Version: 1.0
Subject: Re: [PATCH 2/5] RISC-V: Cache management instructions
Content-Language: en-US
To: Jan Beulich <jbeulich@suse.com>
Cc: binutils@sourceware.org
References: <cover.1639652695.git.research_trasio@irq.a4lg.com>
 <a8d7e5bf6f21f2ca84fdff42237629b085d21929.1639652695.git.research_trasio@irq.a4lg.com>
 <dc08970d-3cb2-3c70-4130-ae3b091bb04f@suse.com>
From: Tsukasa OI <research_trasio@irq.a4lg.com>
In-Reply-To: <dc08970d-3cb2-3c70-4130-ae3b091bb04f@suse.com>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 7bit
X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00, DKIM_SIGNED,
 DKIM_VALID, DKIM_VALID_AU, SPF_HELO_NONE, SPF_PASS,
 TXREP autolearn=ham autolearn_force=no version=3.4.4
X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on
 server2.sourceware.org
X-BeenThere: binutils@sourceware.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: Binutils mailing list <binutils.sourceware.org>
List-Unsubscribe: <https://sourceware.org/mailman/options/binutils>,
 <mailto:binutils-request@sourceware.org?subject=unsubscribe>
List-Archive: <https://sourceware.org/pipermail/binutils/>
List-Post: <mailto:binutils@sourceware.org>
List-Help: <mailto:binutils-request@sourceware.org?subject=help>
List-Subscribe: <https://sourceware.org/mailman/listinfo/binutils>,
 <mailto:binutils-request@sourceware.org?subject=subscribe>
X-List-Received-Date: Wed, 05 Jan 2022 03:17:35 -0000

Jan,

On 2022/01/04 17:01, Jan Beulich wrote:
> On 16.12.2021 12:04, Tsukasa OI via Binutils wrote:
>> --- a/opcodes/riscv-opc.c
>> +++ b/opcodes/riscv-opc.c
>> @@ -849,6 +849,12 @@ const struct riscv_opcode riscv_opcodes[] =
>>  {"sfence.vma", 0, INSN_CLASS_I,    "s,t",      MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
>>  {"wfi",        0, INSN_CLASS_I,    "",         MATCH_WFI, MASK_WFI, match_opcode, 0 },
>>  
>> +/* Zicbom and Zicboz instructions.  */
>> +{"cbo.clean",  0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
>> +{"cbo.flush",  0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
>> +{"cbo.inval",  0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
>> +{"cbo.zero",   0, INSN_CLASS_ZICBOZ, "s", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
> 
> Perhaps more a spec question / remark than one on the implementation:
> Wouldn't it be more natural for CBO.* to have memory-like operands,
> e.g. "cbo.zero (x1)" instead of "cbo.zero x1"?

I would have been agreed unless mnemonic is specified on the spec.
Actually, I used "0(s)" instead of "s" for Zicbom/z instructions until
my re-review of the specification (before submission of PATCH v1).

note: "0(s)" allows "cbo.zero (x1)", "cbo.zero 0(x1)" and its equivalents.

https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0-rc2.pdf

[5.1 - cbo.clean]
Mnemonic:
	cbo.clean base

[5.5 - prefetch.i]
Mnemonic:
	prefetch.i offset(base)

If we really want to change that, we need to talk some RISC-V guys to
change the specification.

Thanks,
Tsukasa

> 
> Jan
>