* [PATCH] x86: Add int1 as one byte opcode 0xf1
@ 2021-07-14 21:28 H.J. Lu
2021-07-15 6:29 ` Jan Beulich
0 siblings, 1 reply; 4+ messages in thread
From: H.J. Lu @ 2021-07-14 21:28 UTC (permalink / raw)
To: binutils
Also change the x86 disassembler to disassemble 0xf1 as int1, instead of
icebp.
gas/
PR gas/28088
* testsuite/gas/i386/opcode.s: Add int1.
* testsuite/gas/i386/x86-64-opcode.s: Add int1, int3 and int.
* testsuite/gas/i386/opcode-intel.d: Updated.
* testsuite/gas/i386/opcode-suffix.d: Likewise.
* testsuite/gas/i386/opcode.d: Likewise.
* testsuite/gas/i386/x86-64-opcode.d: Likewise.
opcodes/
PR gas/28088
* i386-dis.c (dis386): Replace icebp with int1.
* i386-opc.tbl: Add int1.
* i386-tbl.h: Regenerate.
---
gas/testsuite/gas/i386/opcode-intel.d | 1 +
gas/testsuite/gas/i386/opcode-suffix.d | 1 +
gas/testsuite/gas/i386/opcode.d | 1 +
gas/testsuite/gas/i386/opcode.s | 2 ++
gas/testsuite/gas/i386/x86-64-opcode.d | 3 +++
gas/testsuite/gas/i386/x86-64-opcode.s | 4 ++++
opcodes/i386-dis.c | 2 +-
opcodes/i386-opc.tbl | 1 +
opcodes/i386-tbl.h | 13 +++++++++++++
9 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/gas/testsuite/gas/i386/opcode-intel.d b/gas/testsuite/gas/i386/opcode-intel.d
index 68e1e8810e6..732b033c916 100644
--- a/gas/testsuite/gas/i386/opcode-intel.d
+++ b/gas/testsuite/gas/i386/opcode-intel.d
@@ -588,6 +588,7 @@ Disassembly of section .text:
*[0-9a-f]+: 85 c3 [ ]*test[ ]+ebx,eax
*[0-9a-f]+: 85 d8 [ ]*test[ ]+eax,ebx
*[0-9a-f]+: 85 18 [ ]*test[ ]+(DWORD PTR )?\[eax\],ebx
+ *[0-9a-f]+: f1[ ]+int1[ ]+
[ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovp edx,DWORD PTR \[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp edx,DWORD PTR \[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp dx,WORD PTR \[eax-0x6f6f6f70\]
diff --git a/gas/testsuite/gas/i386/opcode-suffix.d b/gas/testsuite/gas/i386/opcode-suffix.d
index 8d7716b6fa8..6a9c4cd8717 100644
--- a/gas/testsuite/gas/i386/opcode-suffix.d
+++ b/gas/testsuite/gas/i386/opcode-suffix.d
@@ -588,6 +588,7 @@ Disassembly of section .text:
*[0-9a-f]+: 85 c3 [ ]*testl[ ]+%eax,%ebx
*[0-9a-f]+: 85 d8 [ ]*testl[ ]+%ebx,%eax
*[0-9a-f]+: 85 18 [ ]*testl[ ]+%ebx,\(%eax\)
+ *[0-9a-f]+: f1[ ]+int1[ ]+
[ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovpl -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnpl -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovpw -0x6f6f6f70\(%eax\),%dx
diff --git a/gas/testsuite/gas/i386/opcode.d b/gas/testsuite/gas/i386/opcode.d
index cc57b9edb80..9c1f67f5fd1 100644
--- a/gas/testsuite/gas/i386/opcode.d
+++ b/gas/testsuite/gas/i386/opcode.d
@@ -587,6 +587,7 @@ Disassembly of section .text:
9f5: 85 c3 [ ]*test %eax,%ebx
9f7: 85 d8 [ ]*test %ebx,%eax
9f9: 85 18 [ ]*test %ebx,\(%eax\)
+ 9fb: f1 [ ]*int1
[ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%dx
diff --git a/gas/testsuite/gas/i386/opcode.s b/gas/testsuite/gas/i386/opcode.s
index 1f803c38e5d..d3255f2b80c 100644
--- a/gas/testsuite/gas/i386/opcode.s
+++ b/gas/testsuite/gas/i386/opcode.s
@@ -585,6 +585,8 @@ foo:
test %ebx,%eax
test (%eax),%ebx
+ int1
+
cmovpe 0x90909090(%eax),%edx
cmovpo 0x90909090(%eax),%edx
cmovpe 0x90909090(%eax),%dx
diff --git a/gas/testsuite/gas/i386/x86-64-opcode.d b/gas/testsuite/gas/i386/x86-64-opcode.d
index ab55d2ca350..c925938fdc4 100644
--- a/gas/testsuite/gas/i386/x86-64-opcode.d
+++ b/gas/testsuite/gas/i386/x86-64-opcode.d
@@ -325,6 +325,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f 07 sysretq *
[ ]*[a-f0-9]+: 0f 01 f8 swapgs
[ ]*[a-f0-9]+: 66 68 22 22 pushw \$0x2222
+[ ]*[a-f0-9]+: f1 int1 +
+[ ]*[a-f0-9]+: cc int3 +
+[ ]*[a-f0-9]+: cd 90 int \$0x90
[ ]*[a-f0-9]+: f6 c9 01 test \$(0x)?0*1,%cl
[ ]*[a-f0-9]+: 66 f7 c9 02 00 test \$(0x)?0*2,%cx
[ ]*[a-f0-9]+: f7 c9 04 00 00 00 test \$(0x)?0*4,%ecx
diff --git a/gas/testsuite/gas/i386/x86-64-opcode.s b/gas/testsuite/gas/i386/x86-64-opcode.s
index 28c100f812e..6575cc33438 100644
--- a/gas/testsuite/gas/i386/x86-64-opcode.s
+++ b/gas/testsuite/gas/i386/x86-64-opcode.s
@@ -454,6 +454,10 @@
pushw $0x2222
+ int1
+ int3
+ int $0x90
+
.byte 0xf6, 0xc9, 0x01
.byte 0x66, 0xf7, 0xc9, 0x02, 0x00
.byte 0xf7, 0xc9, 0x04, 0x00, 0x00, 0x00
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 21e40850544..122f4af0b46 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1965,7 +1965,7 @@ static const struct dis386 dis386[] = {
{ "outG", { indirDX, zAX }, 0 },
/* f0 */
{ Bad_Opcode }, /* lock prefix */
- { "icebp", { XX }, 0 },
+ { "int1", { XX }, 0 },
{ Bad_Opcode }, /* repne */
{ Bad_Opcode }, /* repz */
{ "hlt", { XX }, 0 },
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index b0530e5fb82..49e72d28b56 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -537,6 +537,7 @@ bts, 0xfba, 5, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8, Reg
// See gas/config/tc-i386.c for conversion of 'int $3' into the special
// int 3 insn.
int, 0xcd, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 }
+int1, 0xf1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
int3, 0xcc, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
into, 0xce, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
iret, 0xcf, None, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, {}
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index df139ba6121..15c0b47a915 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -5229,6 +5229,19 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0 } } } },
+ { "int1", 0xf1, None, 0,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0 } },
+ { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0 } } } },
{ "int3", 0xcc, None, 0,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
--
2.31.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] x86: Add int1 as one byte opcode 0xf1
2021-07-14 21:28 [PATCH] x86: Add int1 as one byte opcode 0xf1 H.J. Lu
@ 2021-07-15 6:29 ` Jan Beulich
2021-07-15 11:56 ` H.J. Lu
0 siblings, 1 reply; 4+ messages in thread
From: Jan Beulich @ 2021-07-15 6:29 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 14.07.2021 23:28, H.J. Lu via Binutils wrote:
> Also change the x86 disassembler to disassemble 0xf1 as int1, instead of
> icebp.
Is there a reason for this additional aspect? "icebp" is what this insn
is commonly referred to, after all. I also find "int1" too similar to
"int3" considering the significantly different behavior of both insns.
Jan
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] x86: Add int1 as one byte opcode 0xf1
2021-07-15 6:29 ` Jan Beulich
@ 2021-07-15 11:56 ` H.J. Lu
2021-07-15 12:11 ` Jan Beulich
0 siblings, 1 reply; 4+ messages in thread
From: H.J. Lu @ 2021-07-15 11:56 UTC (permalink / raw)
To: Jan Beulich; +Cc: Binutils
On Wed, Jul 14, 2021 at 11:29 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 14.07.2021 23:28, H.J. Lu via Binutils wrote:
> > Also change the x86 disassembler to disassemble 0xf1 as int1, instead of
> > icebp.
>
> Is there a reason for this additional aspect? "icebp" is what this insn
> is commonly referred to, after all. I also find "int1" too similar to
> "int3" considering the significantly different behavior of both insns.
"int1" is documented in Intel SDM.
--
H.J.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] x86: Add int1 as one byte opcode 0xf1
2021-07-15 11:56 ` H.J. Lu
@ 2021-07-15 12:11 ` Jan Beulich
0 siblings, 0 replies; 4+ messages in thread
From: Jan Beulich @ 2021-07-15 12:11 UTC (permalink / raw)
To: H.J. Lu; +Cc: Binutils
On 15.07.2021 13:56, H.J. Lu wrote:
> On Wed, Jul 14, 2021 at 11:29 PM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 14.07.2021 23:28, H.J. Lu via Binutils wrote:
>>> Also change the x86 disassembler to disassemble 0xf1 as int1, instead of
>>> icebp.
>>
>> Is there a reason for this additional aspect? "icebp" is what this insn
>> is commonly referred to, after all. I also find "int1" too similar to
>> "int3" considering the significantly different behavior of both insns.
>
> "int1" is documented in Intel SDM.
And a footnote says "icebp" is also commonly used. Anyway, I would have
thought keeping names which are familiar to people would be preferable,
but you appear to be thinking differently.
Jan
^ permalink raw reply [flat|nested] 4+ messages in thread
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2021-07-14 21:28 [PATCH] x86: Add int1 as one byte opcode 0xf1 H.J. Lu
2021-07-15 6:29 ` Jan Beulich
2021-07-15 11:56 ` H.J. Lu
2021-07-15 12:11 ` Jan Beulich
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