From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mailbox.box.xen0n.name (mail.xen0n.name [115.28.160.31]) by sourceware.org (Postfix) with ESMTPS id E88163858D32 for ; Tue, 13 Jun 2023 09:49:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E88163858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xen0n.name DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xen0n.name; s=mail; t=1686649779; bh=zyB1bDrve7jv0+jVLE1ET5Dcsz93CQoBeaaj5USOElw=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=sYNfocrPcqXLhopxaMNmCVynNLjQvO5bieIku/Mb8MkjS1cb7rK3c8k/YlxQPlUl3 OOSCy+gAuLm56eexk8N7oDzRFIKY+/+x6IoMRil+vQPWyllu0sS3GyVwZZI2rwwU9q Pq+5fzHs0myc0emQCoyZP0fegeae+qN2x9syvmFg= Received: from [100.100.34.13] (unknown [220.248.53.61]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 2B82A6011B; Tue, 13 Jun 2023 17:49:39 +0800 (CST) Message-ID: <4d7d191c-def8-2073-7926-6db37a2c7f64@xen0n.name> Date: Tue, 13 Jun 2023 17:49:38 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH] LoongArch: Add fcsr register names support Content-Language: en-US To: Feiyang Chen , liuzhensong@loongson.cn, xuchenghua@loongson.cn Cc: chris.chenfeiyang@gmail.com, chenhuacai@loongson.cn, binutils@sourceware.org References: <20230612083649.907511-1-chenfeiyang@loongson.cn> From: WANG Xuerui In-Reply-To: <20230612083649.907511-1-chenfeiyang@loongson.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 2023/6/12 16:36, Feiyang Chen wrote: > Add fcsr register names support for fcsr move instructions. "Support referring to FCSRs as $fcsrX" sounds clearer. Also you may mention a bit more about the justification e.g. LLVM IAS compatibility and/or correction of previous oversight (FCSRs aren't GPRs after all). > > gas/ChangeLog: > > * config/tc-loongarch.c: > (loongarch_fc_normal_name): New definition. > (loongarch_single_float_opcodes): Modify `movgr2fcsr` and > `movfcsr2gr`. > > include/ChangeLog: > > * opcode/loongarch.h (loongarch_fc_normal_name): New extern. > > opcodes/ChangeLog: > > * opcodes/loongarch-dis.c (loongarch_after_parse_args): Add > fcsr register names support. > * opcodes/loongarch-opc.c (loongarch_args_parser_can_match_arg_helper): > Likewise. > > Signed-off-by: Feiyang Chen > --- > gas/config/tc-loongarch.c | 22 +++++++++++++++++++++- > include/opcode/loongarch.h | 1 + > opcodes/loongarch-dis.c | 16 +++++++++++++++- > opcodes/loongarch-opc.c | 9 +++++++-- > 4 files changed, 44 insertions(+), 4 deletions(-) We may have to add/tweak test cases for this. > > diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c > index c55d4ee234a..97971d76a57 100644 > --- a/gas/config/tc-loongarch.c > +++ b/gas/config/tc-loongarch.c > @@ -223,6 +223,7 @@ md_parse_option (int c, const char *arg) > > static struct htab *r_htab = NULL; > static struct htab *f_htab = NULL; > +static struct htab *fc_htab = NULL; > static struct htab *c_htab = NULL; > static struct htab *cr_htab = NULL; > static struct htab *v_htab = NULL; > @@ -286,6 +287,18 @@ loongarch_after_parse_args () > str_hash_insert (f_htab, loongarch_f_normal_name[i], (void *) (i + 1), > 0); > > + if (!fc_htab) > + fc_htab = str_htab_create (), str_hash_insert (fc_htab, "", 0, 0); > + > + for (i = 0; i < ARRAY_SIZE (loongarch_fc_normal_name); i++) > + str_hash_insert (fc_htab, loongarch_fc_normal_name[i], (void *) (i + 1), > + 0); > + > + /* Add general purpose registers for backward compatibility. */ > + for (i = 0; i < ARRAY_SIZE (loongarch_r_normal_name); i++) > + str_hash_insert (fc_htab, loongarch_r_normal_name[i], (void *) (i + 1), > + 0); > + > if (!c_htab) > c_htab = str_htab_create (), str_hash_insert (c_htab, "", 0, 0); > > @@ -666,7 +679,14 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, > ret = imm - 1; > break; > case 'f': > - imm = (intptr_t) str_hash_find (f_htab, arg); > + switch (esc_ch2) > + { > + case 'c': > + imm = (intptr_t) str_hash_find (fc_htab, arg); > + break; > + default: > + imm = (intptr_t) str_hash_find (f_htab, arg); > + } > ip->match_now = 0 < imm; > ret = imm - 1; > break; > diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h > index 004bb6561ef..4ed273182c0 100644 > --- a/include/opcode/loongarch.h > +++ b/include/opcode/loongarch.h > @@ -185,6 +185,7 @@ dec2 : [1-9][0-9]? > extern const char *const loongarch_f_normal_name[32]; > extern const char *const loongarch_f_lp64_name[32]; > extern const char *const loongarch_f_lp64_name1[32]; > + extern const char *const loongarch_fc_normal_name[4]; > extern const char *const loongarch_c_normal_name[8]; > extern const char *const loongarch_cr_normal_name[4]; > extern const char *const loongarch_v_normal_name[32]; > diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c > index d064d30d553..0e7d9a88c25 100644 > --- a/opcodes/loongarch-dis.c > +++ b/opcodes/loongarch-dis.c > @@ -61,6 +61,7 @@ get_loongarch_opcode_by_binfmt (insn_t insn) > > static const char *const *loongarch_r_disname = NULL; > static const char *const *loongarch_f_disname = NULL; > +static const char *const *loongarch_fc_disname = NULL; > static const char *const *loongarch_c_disname = NULL; > static const char *const *loongarch_cr_disname = NULL; > static const char *const *loongarch_v_disname = NULL; > @@ -78,6 +79,7 @@ set_default_loongarch_dis_options (void) > > loongarch_r_disname = loongarch_r_lp64_name; > loongarch_f_disname = loongarch_f_lp64_name; > + loongarch_fc_disname = loongarch_fc_normal_name; > loongarch_c_disname = loongarch_c_normal_name; > loongarch_cr_disname = loongarch_cr_normal_name; > loongarch_v_disname = loongarch_v_normal_name; > @@ -142,7 +144,19 @@ dis_one_arg (char esc1, char esc2, const char *bit_field, > info->fprintf_func (info->stream, "%s", loongarch_r_disname[u_imm]); > break; > case 'f': > - info->fprintf_func (info->stream, "%s", loongarch_f_disname[u_imm]); > + switch (esc2) > + { > + case 'c': > + if (u_imm < 4) > + info->fprintf_func (info->stream, "%s", loongarch_fc_disname[u_imm]); > + else > + /* For backward compatibility. Display using general purpose > + register names if out of range. */ > + info->fprintf_func (info->stream, "%s", loongarch_r_normal_name[u_imm]); I don't think it's proper to call *any* of the FCSRs "GPR" (or actually, aliases to FCSR0, but that doesn't matter). What concrete scenario are you trying to keep compatible with? A test case may explain it. > + break; > + default: > + info->fprintf_func (info->stream, "%s", loongarch_f_disname[u_imm]); > + } > break; > case 'c': > switch (esc2) > diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c > index 573b691c1fd..99fbe318fd3 100644 > --- a/opcodes/loongarch-opc.c > +++ b/opcodes/loongarch-opc.c > @@ -77,6 +77,11 @@ const char *const loongarch_f_lp64_name1[32] = > "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", > }; > > +const char *const loongarch_fc_normal_name[4] = > +{ > + "$fcsr0", "$fcsr1", "$fcsr2", "$fcsr3", > +}; > + > const char *const loongarch_c_normal_name[8] = > { > "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5", "$fcc6", "$fcc7", > @@ -459,8 +464,8 @@ static struct loongarch_opcode loongarch_single_float_opcodes[] = > { 0x0114ac00, 0xfffffc00, "movgr2frh.w", "f0:5,r5:5", 0, 0, 0, 0 }, > { 0x0114b400, 0xfffffc00, "movfr2gr.s", "r0:5,f5:5", 0, 0, 0, 0 }, > { 0x0114bc00, 0xfffffc00, "movfrh2gr.s", "r0:5,f5:5", 0, 0, 0, 0 }, > - { 0x0114c000, 0xfffffc00, "movgr2fcsr", "r0:5,r5:5", 0, 0, 0, 0 }, > - { 0x0114c800, 0xfffffc00, "movfcsr2gr", "r0:5,r5:5", 0, 0, 0, 0 }, > + { 0x0114c000, 0xfffffc00, "movgr2fcsr", "fc0:5,r5:5", 0, 0, 0, 0 }, > + { 0x0114c800, 0xfffffc00, "movfcsr2gr", "r0:5,fc5:5", 0, 0, 0, 0 }, > { 0x0114d000, 0xfffffc18, "movfr2cf", "c0:3,f5:5", 0, 0, 0, 0 }, > { 0x0114d400, 0xffffff00, "movcf2fr", "f0:5,c5:3", 0, 0, 0, 0 }, > { 0x0114d800, 0xfffffc18, "movgr2cf", "c0:3,r5:5", 0, 0, 0, 0 },